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PRELIMINARY DATA

July 2004

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

NAND128-A, NAND256-A

NAND512-A, NAND01G-A

128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)

528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

Up to 1 Gbit memory array

Up to 32 Mbit spare area

Cost effective solutions for mass storage
applications

NAND INTERFACE

x8 or x16 bus width

Multiplexed Address/ Data

Pinout compatibility for all densities

SUPPLY VOLTAGE

1.8V device: V

= 1.7 to 1.95V

3.0V device: V

= 2.7 to

3.6V

PAGE SIZE

x8 device: (512 + 16 spare) Bytes

x16 device: (256 + 8 spare) Words

BLOCK SIZE

x8 device: (16K + 512 spare) Bytes

x16 device: (8K + 256 spare) Words

PAGE READ / PROGRAM

Random access: 12µs (max)

Sequential access: 50ns (min)

Page program time: 200µs (typ)

COPY BACK PROGRAM MODE

Fast page copy without external buffering

FAST BLOCK ERASE

Block erase time: 2ms (Typ)

STATUS REGISTER

ELECTRONIC SIGNATURE

CHIP ENABLE `DON'T CARE' OPTION

Simple interface with microcontroller

AUTOMATIC PAGE 0 READ AT POWER-UP
OPTION

Boot from NAND support

Automatic Memory Download

SERIAL NUMBER OPTION

Figure 1. Packages

HARDWARE DATA PROTECTION

Program/Erase locked during Power
transitions

DATA INTEGRITY

100,000 Program/Erase cycles

10 years Data Retention

DEVELOPMENT TOOLS

Error Correction Code software and
hardware models

Bad Blocks Management and Wear
Leveling algorithms

PC Demo board with simulation software

File System OS Native reference software

Hardware simulation models

TSOP48 12 x 20mm

VFBGA55 8 x 10 x 1mm
TFBGA55 8 x 10 x 1.2mm
VFBGA63 8.5 x 15 x 1mm
TFBGA63 8.5 x 15 x 1.2mm

FBGA

WSOP48 12 x 17 x 0.65mm

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NAND128-A, NAND256-A, NAND512-A, NAND01G-A

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TSOP48 and WSOP48 Connections, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. TSOP48 and WSOP48 Connections, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. FBGA55 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11
Figure 7. FBGA55 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 12
Figure 8. FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 13
Figure 9. FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 14

MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Enable (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

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Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DEVICE OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15.Sequential Row Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Sequential Row Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
P/E/R Controller Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SR5, SR4, SR3, SR2 and SR1 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Automatic Page 0 Read at Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Automatic Page 0 Read Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chip Enable Don't Care Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chip Enable Don't Care Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 20.Chip Enable Don't Care Enabled and Automatic Page 0 Read at Power-Up . . . . . . . . . 28
Figure 21.Automatic Page 0 Read at Power-Up (Chip Enable Don't Care Disabled) . . . . . . . . . . . 29

SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Figure 23.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 32

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25.Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 27.Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 29.Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 31.Page Read A/ Read B Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 34.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 35.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 36.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 37.Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 38.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 45

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 39.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 46
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 46
Figure 40.WSOP48 48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline47
Table 23. WSOP48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Mechanical Data. . . . 47
Figure 41.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 48
Table 24. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . 48
Figure 42.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline . . . . . . . . 49

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

6/56

Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data 49
Figure 43.VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . 50
Table 26. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data50
Figure 44.TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . 51
Table 27. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data51

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 45.Connection to Microcontroller, Without Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 46.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 47.Building Storage Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

SUMMARY DESCRIPTION

The NAND Flash 528 Byte/ 264 Word Page is a
family of non-volatile Flash memories that uses
NAND cell technology. The devices range from
128Mbits to 1Gbit and operate with either a 1.8V
or 3V voltage supply. The size of a Page is either
528 Bytes (512 + 16 spare) or 264 Words (256 + 8
spare) depending on whether the device has a x8
or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
put/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC). A Write
Protect pin is available to give a hardware protec-
tion against program and erase operations.
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back command is available to optimize the
management of defective blocks. When a Page
Program operation fails, the data can be pro-
grammed in another page without having to re-
send the data to be programmed.
The devices are available in the following packag-
es:

TSOP48 12 x 20mm for all products

WSOP48 12 x 17 x 0.65mm for 128Mb,
256Mb and 512Mb products

VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,
0.8mm pitch) for 128Mb and 256Mb products

TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for 512Mb Dual Die product

VFBGA63 (8.5 x 15 x 1mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product

TFBGA63 (8.5 x 15 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for the 1Gb Dual Die product

Three options are available for the NAND Flash
family:

Automatic Page 0 Read after Power-up, which
allows the microcontroller to directly download
the boot code from page 0.

Chip Enable Don't Care, which allows code to
be directly downloaded by a microcontroller,
as Chip Enable transitions during the latency
time do not stop the read operation.

A Serial Number, which allows each device to
be uniquely identified. The Serial Number
options is subject to an NDA (Non Disclosure
Agreement) and so not described in the
datasheet. For more details of this option
contact your nearest ST Sales office.

For information on how to order these options refer
to

Table 28., Ordering Information Scheme

. De-

vices are shipped from the factory with Block 0 al-
ways valid and the memory content bits, in valid
blocks, erased to '1'.
See

Table 2., Product Description

, for all the de-

vices available in the family.

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

8/56

Table 2. Product Description

Figure 2. Logic Diagram

Table 3. Signal Names

Reference

Part Number

Density

Bus

Width

Page

Size

Block

Size

Memory

Array

Operating

Voltage

Timings

Package

Random

Access

Max

Sequential

Access

Min

Page

Program

Typical

Block
Erase

Typical

NAND128-A

NAND128R3A

128Mbit

512+16

Bytes

16K+512

Bytes

32 Pages x

1024 Blocks

1.7 to 1.95V

10µs

60ns

200µs

2ms

TSOP48

WSOP48

VFBGA55

NAND128W3A

2.7 to 3.6V

10µs

50ns

200µs

NAND128R4A

x16

256+8
Words

8K+256

Words

1.7 to 1.95V

10µs

60ns

200µs

NAND128W4A

2.7 to 3.6V

10µs

50ns

200µs

NAND256-A

NAND256R3A

256Mbit

512+16

Bytes

16K+512

Bytes

32 Pages x

2048 Blocks

1.7 to 1.95V

10µs

60ns

200µs

2ms

TSOP48

WSOP48

VFBGA55

NAND256W3A

2.7 to 3.6V

10µs

50ns

200µs

NAND256R4A

x16

256+8
Words

8K+256

Words

1.7to 1.95V

10µs

60ns

200µs

NAND256W4A

2.7 to 3.6V

10µs

50ns

200µs

NAND512-A

NAND512R3A

512Mbit

512+16

Bytes

16K+512

Bytes

32 Pages x

4096 Blocks

1.7to 1.95V

10µs

60ns

200µs

2ms

TFBGA55

NAND512W3A

2.7 to 3.6V

10µs

50ns

200µs

NAND512R4A

x16

256+8
Words

8K+256

Words

1.7 to 1.95V

10µs

60ns

200µs

NAND512W4A

2.7 to 3.6V

10µs

50ns

200µs

NAND512-A

NAND512R3A

512Mbit

512+16

Bytes

16K+512

Bytes

32 Pages x

4096 Blocks

1.7to 1.95V

15µs

60ns

200µs

2ms

TSOP48

WSOP48

VFBGA63

NAND512W3A

2.7 to 3.6V

12µs

50ns

200µs

NAND512R4A

x16

256+8
Words

8K+256

Words

1.7 to 1.95V

15µs

60ns

200µs

NAND512W4A

2.7 to 3.6V

12µs

50ns

200µs

NAND01G-A

NAND01GR3A

1Gbit

512+16

Bytes

16K+512

Bytes

32 Pages x

8192 Blocks

1.7 to 1.95V

15µs

60ns

200µs

2ms

TSOP48

TFBGA63

NAND01GW3A

2.7 to 3.6V

12µs

50ns

200µs

NAND01GR4A

x16

256+8
Words

8K+256

Words

1.7 to 1.95V

15µs

60ns

200µs

NAND01GW4A

2.7 to 3.6V

12µs

50ns

200µs

AI07557C

I/O8-I/O15, x16

VDD

NAND Flash

VSS

I/O0-I/O7, x8/x16

I/O8-15

Data Input/Outputs for x16 devices

I/O0-7

Data Input/Outputs, Address Inputs,
or Command Inputs for x8 and x16
devices

Address Latch Enable

Command Latch Enable

Chip Enable

Read Enable

Ready/Busy (open-drain output)

Write Enable

Write Protect

Supply Voltage

Ground

Not Connected Internally

Do Not Use

15/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

MEMORY ARRAY ORGANIZATION

The memory array is made up of NAND structures
where 16 cells are connected in series.
The memory array is organized in blocks where
each block contains 32 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a main area
with two half pages of 256 Bytes each and a spare
area of 16 Bytes. In the x16 devices the pages are
split into a 256 Word main area and an 8 Word
spare area. Refer to

Figure 10., Memory Array Or-

ganization

Bad Blocks
The NAND Flash 528 Byte/ 264 Word Page devic-
es may contain Bad Blocks, that is blocks that con-
tain one or more invalid bits whose reliability is not
guaranteed. Additional Bad Blocks may develop
during the lifetime of the device.

The Bad Block Information is written prior to ship-
ping (refer to

Bad Block Management

section for

more details).

Table 4.

shows the minimum number of valid

blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipped and the Bad Blocks that could de-
velop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to

SOFTWARE ALGO-

RITHMS

section).

Table 4. Valid Blocks

Figure 10. Memory Array Organization

Density of Device

Min

Max

1Gbit

8032

8192

512Mbits

4016

4096

256Mbits

2008

2048

128Mbits

1004

1024

AI07587

Block = 32 Pages
Page = 528 Bytes (512+16)

512 Bytes

are

Are

2nd half Page

(256 bytes)

Bytes

Block

8 bits

Bytes

8 bits

Page

Page Buffer, 512 Bytes

1st half Page

(256 bytes)

Block = 32 Pages
Page = 264 Words (256+8)

256 Words

are

Are

Main Area

Words

16 bits

Words

16 bits

Page Buffer, 264 Words

Block

Page

x8 DEVICES

x16 DEVICES

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

16/56

SIGNAL DESCRIPTIONS

See

Figure 2., Logic Diagram

, and

Table

3., Signal Names

, for a brief overview of the sig-

nals connected to this device.
Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a command
or data during a Write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/
O7 are left floating when the device is deselected
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to
15 are only available in x16 devices. They are
used to output the data during a Read operation or
input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write
Enable. I/O8-I/O15 are left floating when the de-
vice is deselected or the outputs are disabled.
Address Latch Enable (AL). The Address Latch
Enable activates the latching of the Address inputs
in the Command Interface. When AL is high, the
inputs are latched on the rising edge of Write En-
able.
Command Latch Enable (CL). The Command
Latch Enable activates the latching of the Com-
mand inputs in the Command Interface. When CL
is high, the inputs are latched on the rising edge of
Write Enable.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
low, V

, the device is selected. If Chip Enable

goes high, v

, while the device is busy, the device

remains selected and does not go into standby
mode.
When the device is executing a Sequential Row
Read operation, Chip Enable must be held low
(from the second page read onwards) during the
time that the device is busy (t

BLBH1

). If Chip En-

able goes high during t

BLBH1

the operation is

aborted.
Read Enable (R). The Read Enable, R, controls
the sequential data output during Read opera-
tions. Data is valid t

RLQV

after the falling edge of R.

The falling edge of R also increments the internal
column address counter by one.

Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write En-
able.
During power-up and power-down a recovery time
of 1µs (min) is required before the Command Inter-
face is ready to accept a command. It is recom-
mended to keep Write Enable high during the
recovery time.
Write Protect (WP). The Write Protect pin is an
input that gives a hardware protection against un-
wanted program or erase operations. When Write
Protect is Low, V

, the device does not accept any

program or erase operations.
It is recommended to keep the Write Protect pin
Low, V

, during power-up and power-down.

Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Low, V

, a read, program or

erase operation is in progress. When the operation
completes Ready/Busy goes High, V

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Refer to the

Ready/Busy Signal Electrical Charac-

teristics

section for details on how to calculate the

value of the pull-up resistor.
V

Supply Voltage. V

provides the power

supply to the internal core of the memory device.
It is the main power supply for all operations (read,
program and erase).
An internal voltage detector disables all functions
whenever V

is below 2.5V (for 3V devices) or

1.5V (for 1.8V devices) to protect the device from
any involuntary program/erase during power-tran-
sitions.
Each device in a system should have V

decou-

pled with a 0.1µF capacitor. The PCB track widths
should be sufficient to carry the required program
and erase currents
V

Ground. Ground, V

SS,

is the reference for

the power supply. It must be connected to the sys-
tem ground.

17/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

BUS OPERATIONS

There are six standard bus operations that control
the memory. Each of these is described in this
section, see

Table 5., Bus Operations

, for a sum-

mary.
Command Input
Command Input bus operations are used to give
commands to the memory. Command are accept-
ed when Chip Enable is Low, Command Latch En-
able is High, Address Latch Enable is Low and
Read Enable is High. They are latched on the ris-
ing edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See

Figure 25.

and

Table 20.

for details of the tim-

ings requirements.
Address Input
Address Input bus operations are used to input the
memory address. Three bus cycles are required to
input the addresses for the 128Mb and 256Mb de-
vices and four bus cycles are required to input the
addresses for the 512Mb and 1Gb devices (refer
to Tables

and

, Address Insertion).

The addresses are accepted when Chip Enable is
Low, Address Latch Enable is High, Command
Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write
Enable signal. Only I/O0 to I/O7 are used to input
addresses.
See

Figure 26.

and

Table 20.

for details of the tim-

ings requirements.
Data Input
Data Input bus operations are used to input the
data to be programmed.

Data is accepted only when Chip Enable is Low,
Address Latch Enable is Low, Command Latch
Enable is Low and Read Enable is High. The data
is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the
Write Enable signal.
See

Figure 27.

and

Table 20.

and

Table 21.

for de-

tails of the timings requirements.
Data Output
Data Output bus operations are used to read: the
data in the memory array, the Status Register, the
Electronic Signature

and the Serial Number.

Data is output when Chip Enable is Low, Write En-
able is High, Address Latch Enable is Low, and
Command Latch Enable is Low.
The data is output sequentially using the Read En-
able signal.
See

Figure 28.

and

Table 21.

for details of the tim-

ings requirements.
Write Protect
Write Protect bus operations are used to protect
the memory against program or erase operations.
When the Write Protect signal is Low the device
will not accept program or erase operations and so
the contents of the memory array cannot be al-
tered. The Write Protect signal is not latched by
Write Enable to ensure protection even during
power-up.
Standby
When Chip Enable is High the memory enters
Standby mode, the device is deselected, outputs
are disabled and power consumption is reduced.

Table 5. Bus Operations

Note: 1. Only for x16 devices.

2. WP must be V

when issuing a program or erase command.

Bus Operation

I/O0 - I/O7

I/O8 - I/O15

(1)

Command Input

Rising

(2)

Command

Address Input

Rising

Address

Data Input

Rising

Data Input

Data Output

Falling

Data Output

Write Protect

Standby

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

18/56

Table 6. Address Insertion, x8 Devices

Note: 1. A8 is set Low or High by the 00h or 01h Command, see

Pointer Operations

section.

2. Any additional address input cycles will be ignored.
3. The 4th cycle is only required for 512Mb and 1Gb devices.

Table 7. Address Insertion, x16 Devices

Note: 1. A8 is Don't Care in x16 devices.

2. Any additional address input cycles will be ignored.
3. The 01h Command is not used in x16 devices.
4. The 4th cycle is only required for 512Mb and 1Gb devices.

Table 8. Address Definitions

Bus Cycle

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

A16

A15

A14

A13

A12

A11

A10

A24

A23

A22

A21

A20

A19

A18

A17

th(4)

A26

A25

Bus

Cycle

I/O8-

I/O15

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

A16

A15

A14

A13

A12

A11

A10

A24

A23

A22

A21

A20

A19

A18

A17

th(4)

A26

A25

Address

Definition

A0 - A7

Column Address

A9 - A26

Page Address

A9 - A13

Address in Block

A14 - A26

Block Address

A8 is set Low or High by the 00h or 01h Command, and is

Don't Care in x16 devices

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

20/56

DEVICE OPERATIONS

Pointer Operations
As the NAND Flash memories contain two differ-
ent areas for x16 devices and three different areas
for x8 devices (see

Figure 11.

) the read command

codes (00h, 01h, 50h) are used to act as pointers
to the different areas of the memory array (they se-
lect the most significant column address).
The Read A and Read B commands act as point-
ers to the main memory area. Their use depends
on the bus width of the device.

In x16 devices the Read A command (00h)
sets the pointer to Area A (the whole of the
main area) that is Words 0 to 255.

In x8 devices the Read A command (00h) sets
the pointer to Area A (the first half of the main
area) that is Bytes 0 to 255, and the Read B
command (01h) sets the pointer to Area B (the

second half of the main area) that is Bytes 256
to 511.

In both the x8 and x16 devices the Read C com-
mand (50h), acts as a pointer to Area C (the spare
memory area) that is Bytes 512 to 527 or Words
256 to 263.
Once the Read A and Read C commands have
been issued the pointer remains in the respective
areas until another pointer code is issued. Howev-
er, the Read B command is effective for only one
operation, once an operation has been executed
in Area B the pointer returns automatically to Area
A.
The pointer operations can also be used before a
program operation, that is the appropriate code
(00h, 01h or 50h) can be issued before the pro-
gram command 80h is issued (see

Figure 12.

Figure 11. Pointer Operations

Figure 12. Pointer Operations for Programming

AI07592

Area A

(00h)

Area B

(01h)

Area C

(50h)

Bytes 0- 255

Bytes 256-511

Bytes 512

-527

Pointer

(00h,01h,50h)

Page Buffer

Area A

(00h)

Area C

(50h)

Words 0- 255

Words 256

-263

Pointer

(00h,50h)

Page Buffer

x8 Devices

x16 Devices

ai07591

I/O

Address

Inputs

Data Input

10h

80h

Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.

AREA A

00h

Address

Inputs

Data Input

10h

80h

00h

I/O

Address

Inputs

Data Input

10h

80h

Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.

AREA B

01h

Address

Inputs

Data Input

10h

80h

01h

I/O

Address

Inputs

Data Input

10h

80h

Only Areas C can be programmed. Subsequent 50h commands can be omitted.

AREA C

50h

Address

Inputs

Data Input

10h

80h

50h

21/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Read Memory Array
Each operation to read the memory area starts
with a pointer operation as shown in the

Pointer

Operations

section. Once the area (main or spare)

has been selected using the Read A, Read B or
Read C commands four bus cycles (for 512Mb
and 1Gb devices) or three bus cycles (for 128Mb
and 256Mb devices) are required to input the ad-
dress (refer to

Table 6.

) of the data to be read.

The device defaults to Read A mode after power-
up or a Reset operation. Devices, where page0 is
read automatically at power-up, are available on
request.
When reading the spare area addresses:

A0 to A3 (x8 devices)

A0 to A2 (x16 devices)

are used to set the start address of the spare area
while addresses:

A4 to A7 (x8 devices)

A3 to A7 (x16 devices)

are ignored.
Once the Read A or Read C commands have
been issued they do not need to be reissued for
subsequent read operations as the pointer re-
mains in the respective area. However, the Read
B command is effective for only one operation,
once an operation has been executed in Area B
the pointer returns automatically to Area A and so

another Read B command is required to start an-
other read operation in Area B.
Once a read command is issued three types of op-
erations are available: Random Read, Page Read
and Sequential Row Read.
Random Read. Each time the command is is-
sued the first read is Random Read.
Page Read. After the Random Read access the
page data is transferred to the Page Buffer in a
time of

WHBH

(refer to

Table 21.

for value). Once

the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequen-
tially (from selected column address to last column
address) by pulsing the Read Enable signal.
Sequential Row Read. After the data in last col-
umn of the page is output, if the Read Enable sig-
nal is pulsed and Chip Enable remains Low then
the next page is automatically loaded into the
Page Buffer and the read operation continues. A
Sequential Row Read operation can only be used
to read within a block. If the block changes a new
read command must be issued.
Refer to

Figure 15.

and

Figure 16.

for details of Se-

quential Row Read operations.
To terminate a Sequential Row Read operation set
the Chip Enable signal to High for more than t

EHEL

Sequential Row Read is not available when the
Chip Enable Don't Care option is enabled.

Figure 13. Read (A,B,C) Operations

I/O

00h/

01h/ 50h

ai07595

Busy

Command

Code

Address Input

Data Output (sequentially)

tBLBH1

(read)

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

22/56

Figure 14. Read Block Diagrams

Note: 1. Highest address depends on device density.

Figure 15. Sequential Row Read Operations

Figure 16. Sequential Row Read Block Diagrams

AI07596

A0-A7

A9-A26(1)

Area A

(1st half Page)

Read A Command, X8 Devices

Area B

(2nd half Page)

Area C

(Spare)

Area A

(main area)

Area C

(Spare)

A0-A7

Read A Command, X16 Devices

A0-A7

Read B Command, X8 Devices

Area A

(1st half Page)

Area B

(2nd half Page)

Area C

(Spare)

A0-A3 (x8)

A0-A2 (x16)

Read C Command, X8/x16 Devices

Area A

Area A/ B

Area C

(Spare)

A9-A26(1)

A4-A7 (x8), A3-A7 (x16) are don't care

I/O

Address Inputs

ai07597

1st

Page Output

Busy

tBLBH1

(Read Busy time)

00h/

01h/ 50h

Command

Code

2nd

Page Output

Nth

Page Output

Busy

tBLBH1

AI07598

Block

Area A

(1st half Page)

Read A Command, x8 Devices

Area B

(2nd half Page)

Area C

(Spare)

Area A

(main area)

Area C

(Spare)

Read A Command, x16 Devices

Read B Command, x8 Devices

Read C Command, x8/x16 Devices

Area A

Area A/ B

Area C

(Spare)

Area A

(1st half Page)

Area B

(2nd half Page)

Area C

(Spare)

1st page

2nd page
Nth page

1st page
2nd page
Nth page

1st page

2nd page
Nth page

1st page

2nd page
Nth page

Block

23/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Page Program
The Page Program operation is the standard oper-
ation to program data to the memory array.
The main area of the memory array is pro-
grammed by page, however partial page program-
ming is allowed where any number of bytes (1 to
528) or words (1 to 264) can be programmed.
The maximum number of consecutive partial page
program operations allowed in the same page is
three. After exceeding this a Block Erase com-
mand must be issued before any further program
operations can take place in that page.
Before starting a Page Program operation a Point-
er operation can be performed to point to the area
to be programmed. Refer to the

Pointer Opera-

tions

section and

Figure 12.

for details.

Each Page Program operation consists of five
steps (see

Figure 17.

one bus cycle is required to setup the Page
Program command

four bus cycles are then required to input the
program address (refer to

Table 6.

)

the data is then input (up to 528 Bytes/ 264
Words) and loaded into the Page Buffer

one bus cycle is required to issue the confirm
command to start the P/E/R Controller.

The P/E/R Controller then programs the data
into the array.

Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During program operations
the Status Register will only flag errors for bits set
to '1' that have not been successfully programmed
to '0'.
During the program operation, only the Read Sta-
tus Register and Reset commands will be accept-
ed, all other commands will be ignored.
Once the program operation has completed the P/
E/R Controller bit SR6 is set to `1' and the Ready/
Busy signal goes High.
The device remains in Read Status Register mode
until another valid command is written to the Com-
mand Interface.

Figure 17. Page Program Operation

Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to

Pointer Operations

section for details.

I/O

Address Inputs

SR0

ai07566

Data Input

10h

70h

80h

Page Program

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH2

(Program Busy time)

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

24/56

Copy Back Program
The Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particularly useful when a portion of a block is up-
dated and the rest of the block needs to be copied
to the newly assigned block.
If the Copy Back Program operation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back operation bit error due to charge loss
cannot be detected. For this reason it is recom-
mended to limit the number of Copy Back opera-
tions on the same data and or to improve the
performance of the ECC.
The Copy Back Program operation requires three
steps:
1.

The source page must be read using the Read
A command (one bus write cycle to setup the
command and then 4 bus write cycles to input
the source page address). This operation
copies all 264 Words/ 528 Bytes from the page
into the Page Buffer.

When the device returns to the ready state
(Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus
cycles to input the target page address. Refer
to

Table 10.

for the addresses that must be the

same for the Source and Target pages.

Then the confirm command is issued to start
the P/E/R Controller.

After a Copy Back Program operation, a partial-
page program is not allowed in the target page un-
til the block has been erased.
See

Figure 18.

for an example of the Copy Back

operation.

Table 10. Copy Back Program Addresses

Figure 18. Copy Back Operation

Density

Same Address for Source and

Target Pages

128Mbit

A23

256Mbit

A24

512Mbit

A25

1Gbit

A25,A26

I/O

Source

Address Inputs

SR0

ai07590b

8Ah

70h

00h

Copy Back

Code

Read

Code

Read Status Register

Target

Address Inputs

tBLBH1

(Read Busy time)

10h

Busy

tBLBH2

(Program Busy time)

25/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Block Erase
Erase operations are done one block at a time. An
erase operation sets all of the bits in the ad-
dressed block to `1'. All previous data in the block
is lost.
An erase operation consists of three steps (refer to

Figure 19.

One bus cycle is required to setup the Block
Erase command.

Only three bus cycles for 512Mb and 1Gb
devices, or two for 128Mb and 256Mb devices

are required to input the block address. The
first cycle (A0 to A7) is not required as only
addresses A14 to A26 (highest address
depends on device density) are valid, A9 to
A13 are ignored. In the last address cycle I/O0
to I/O7 must be set to V

One bus cycle is required to issue the confirm
command to start the P/E/R Controller.

Once the erase operation has completed the Sta-
tus Register can be checked for errors.

Figure 19. Block Erase Operation

Reset
The Reset command is used to reset the Com-
mand Interface and Status Register. If the Reset
command is issued during any operation, the op-
eration will be aborted. If it was a program or erase
operation that was aborted, the contents of the
memory locations being modified will no longer be
valid as the data will be partially programmed or
erased.

If the device has already been reset then the new
Reset command will not be accepted.
The Ready/Busy signal goes Low for t

BLBH4

after

the Reset command is issued. The value of t

BLBH4

depends on the operation that the device was per-
forming when the command was issued, refer to

Table 21.

for the values.

I/O

Block Address

Inputs

SR0

ai07593

D0h

70h

60h

Block Erase

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH3

(Erase Busy time)

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

26/56

Read Status Register
The device contains a Status Register which pro-
vides information on the current or previous Pro-
gram or Erase operation. The various bits in the
Status Register convey information and errors on
the operation.
The Status Register is read by issuing the Read
Status Register command. The Status Register in-
formation is present on the output data bus (I/O0-
I/O7) on the falling edge of Chip Enable or Read
Enable, whichever occurs last. When several
memories are connected in a system, the use of
Chip Enable and Read Enable signals allows the
system to poll each device separately, even when
the Ready/Busy pins are common-wired. It is not
necessary to toggle the Chip Enable or Read En-
able signals to update the contents of the Status
Register.
After the Read Status Register command has
been issued, the device remains in Read Status
Register mode until another command is issued.
Therefore if a Read Status Register command is
issued during a Random Read cycle a new read
command must be issued to continue with a Page
Read or Sequential Row Read operation.

The Status Register bits are summarized in

Table

11., Status Register Bits

. Refer to

Table 11.

conjunction with the following text descriptions.
Write Protection Bit (SR7). The Write Protection
bit can be used to identify if the device is protected
or not. If the Write Protection bit is set to `1' the de-
vice is not protected and program or erase opera-
tions are allowed. If the Write Protection bit is set
to `0' the device is protected and program or erase
operations are not allowed.
P/E/R Controller Bit (SR6). The Program/Erase/
Read Controller bit indicates whether the P/E/R
Controller is active or inactive. When the P/E/R
Controller bit is set to `0', the P/E/R Controller is
active (device is busy); when the bit is set to `1', the
P/E/R Controller is inactive (device is ready).
Error Bit (SR0). The Error bit is used to identify if
any errors have been detected by the P/E/R Con-
troller. The Error Bit is set to '1' when a program or
erase operation has failed to write the correct data
to the memory. If the Error Bit is set to `0' the oper-
ation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are Reserved.

27/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Table 11. Status Register Bits

Read Electronic Signature
The device contains a Manufacturer Code and De-
vice Code. To read these codes two steps are re-
quired:
1.

first use one Bus Write cycle to issue the Read
Electronic Signature command (90h)

then perform two Bus Read operations the
first will read the Manufacturer Code and the
second, the Device Code. Further Bus Read
operations will be ignored.

Refer to

Table 12., Electronic Signature

, for infor-

mation on the addresses.

Table 12. Electronic Signature

Bit

Name

Logic Level

Definition

SR7

Write Protection

'1'

Not Protected

'0'

Protected

SR6

Program/ Erase/ Read

Controller

'1'

P/E/R C inactive, device ready

'0'

P/E/R C active, device busy

SR5, SR4,

SR3, SR2, SR1

Reserved

Don't Care

SR0

Generic Error

`1'

Error operation failed

`0'

No Error operation successful

Part Number

Manufacturer

Code

Device code

NAND128R3A

20h

33h

NAND128W3A

73h

NAND128R4A

0020h

0043h

NAND128W4A

0053h

NAND256R3A

20h

35h

NAND256W3A

75h

NAND256R4A

0020h

0045h

NAND256W4A

0055h

NAND512R3A

20h

36h

NAND512W3A

76h

NAND512R4A

0020h

0046h

NAND512W4A

0056h

NAND01GR3A

20h

39h

NAND01GW3A

79h

NAND01GR4A

0020h

0049h

NAND01GW4A

0059h

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

28/56

Automatic Page 0 Read at Power-Up
Automatic Page 0 Read at Power-Up is an option
available on all devices belonging to the NAND
Flash 528 Byte/264 Word Page family. It allows
the microcontroller to directly download boot code
from page 0, without requiring any command or
address input sequence. The Automatic Page 0
Read option is particularly suited for applications
that boot from the NAND.
Devices delivered with Automatic Page 0 Read at
Power-Up can have the Chip Enable Don't Care
option either enabled or disabled. For details on
how to order the different options, refer to

Table

28., Ordering Information Scheme

Automatic Page 0 Read Description. At power-
up, once the supply voltage has reached the
threshold level, V

DDth

, all digital outputs revert to

their reset state and the internal NAND device
functions (reading, writing, erasing) are enabled.
The device then automatically switches to read
mode where, as in any read operation, the device
is busy for a time t

BLBH1

during which data is trans-

ferred to the Page Buffer. Once the data transfer is

complete the Ready/Busy signal goes High. The
data can then be read out sequentially on the I/O
bus by pulsing the Read Enable, R, signal.

Figure

20.

and

Figure 21.

show the power-up waveforms

for devices featuring the Automatic Page 0 Read
option.
Chip Enable Don't Care Enabled. If the device
is delivered with Chip Enable Don't Care and Au-
tomatic Page 0 Read at Power-up, only the first
page (Page 0) will be automatically read after the
power-up sequence. Refer to

Figure 20.

Chip Enable Don't Care Disabled. If the device
is delivered with the Automatic Page 0 Read op-
tion only (Chip Enable Don't Care disabled), the
device will automatically enter Sequential Row
Read mode (Automatic Memory Download) after
the power-up sequence, and start reading Page 0,
Page 1, etc., until the last memory location is
reached, each new page being accessed after a
time t

BLBH1

The Sequential Row Read operation can be inhib-
ited or interrupted by de-asserting E (set to V

) or

by issuing a command.

Figure 20. Chip Enable Don't Care Enabled and Automatic Page 0 Read at Power-Up

Note: 1.

is equal to 2.5V for 3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.

I/O

tBLBH1

Data

N+1

Data

N+2

Last

Data

Busy

Data Output

from Address N to Last Byte or Word in Page

DDth

(1)

ai08443b

29/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Figure 21. Automatic Page 0 Read at Power-Up (Chip Enable Don't Care Disabled)

SOFTWARE ALGORITHMS

This section gives information on the software al-
gorithms that ST recommends to implement to
manage the Bad Blocks and extend the lifetime of
the NAND device.
NAND Flash memories are programmed and
erased by Fowler-Nordheim tunneling using a high
voltage. Exposing the device to a high voltage for
extended periods can cause the oxide layer to be
damaged. For this reason, the number of program
and erase cycles is limited (see

Table 14.

for val-

ue) and it is recommended to implement Garbage
Collection, a Wear-Leveling Algorithm and an Er-
ror Correction Code, to extend the number of pro-
gram and erase cycles and increase the data
retention.
To help integrate a NAND memory into an applica-
tion ST Microelectronics can provide:

A Demo board with NAND simulation software
for PCs

File System OS Native reference software,
which supports the basic commands of file
management.

Contact the nearest ST Microelectronics sales of-
fice for more details.
Bad Block Management
Devices with Bad Blocks have the same quality
level and the same AC and DC characteristics as
devices where all the blocks are valid. A Bad Block
does not affect the performance of valid blocks be-
cause it is isolated from the bit line and common
source line by a select transistor.
The devices are supplied with all the locations in-
side valid blocks erased (FFh). The Bad Block In-
formation is written prior to shipping. Any block
where the 6th Byte/ 1st Word

in the spare area of

the 1st or 2nd page (if the 1st page is Bad) does
not contain FFh is a Bad Block.
The Bad Block Information must be read before
any erase is attempted as the Bad Block Informa-
tion may be erased. For the system to be able to
recognize the Bad Blocks based on the original in-
formation it is recommended to create a Bad Block
table following the flowchart shown in

Figure 22.

Block Replacement
Over the lifetime of the device additional Bad
Blocks may develop. In this case the block has to
be replaced by copying the data to a valid block.
These additional Bad Blocks can be identified as
attempts to program or erase them will give errors
in the Status Register.
As the failure of a page program operation does
not affect the data in other pages in the same
block, the block can be replaced by re-program-
ming the current data and copying the rest of the
replaced block to an available valid block. The
Copy Back Program command can be used to
copy the data to a valid block.

See the "

Copy Back Program

" section for more de-

tails.

Refer to

Table 13.

for the recommended proce-

dure to follow if an error occurs during an opera-
tion.

Table 13. Block Failure

I/O

Page 0

Data Out

ai08444

Page 1

Data Out

Busy

tBLBH1

Page 2

Data Out

Page Nth

Data Out

Busy

tBLBH1

(Read Busy time)

Busy

Operation

Recommended Procedure

Erase

Block Replacement

Program

Block Replacement or ECC

Read

ECC

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

30/56

Figure 22. Bad Block Management Flowchart

Figure 23. Garbage Collection

Garbage Collection
When a data page needs to be modified, it is faster
to write to the first available page, and the previous
page is marked as invalid. After several updates it
is necessary to remove invalid pages to free some
memory space.
To free this memory space and allow further pro-
gram operations it is recommended to implement
a Garbage Collection algorithm. In a Garbage Col-
lection software the valid pages are copied into a
free area and the block containing the invalid pag-
es is erased (see

Figure 23.

Wear-leveling Algorithm
For write-intensive applications, it is recommend-
ed to implement a Wear-leveling Algorithm to
monitor and spread the number of write cycles per
block.
In memories that do not use a Wear-Leveling Al-
gorithm not all blocks get used at the same rate.
Blocks with long-lived data do not endure as many
write cycles as the blocks with frequently-changed
data.
The Wear-leveling Algorithm ensures that equal
use is made of all the available write cycles for
each block. There are two wear-leveling levels:

AI07588C

START

END

YES

Block Address =

Block 0

Data

= FFh?

Last

block?

Increment

Block Address

Update

Bad Block table

Valid

Page

Invalid

Page

Free

Page

(Erased)

Old Area

AI07599B

New Area (After GC)

31/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

First Level Wear-leveling, new data is
programmed to the free blocks that have had
the fewest write cycles

Second Level Wear-leveling, long-lived data is
copied to another block so that the original
block can be used for more frequently-
changed data.

The Second Level Wear-leveling is triggered when
the difference between the maximum and the min-
imum number of write cycles per block reaches a
specific threshold.
Error Correction Code
An Error Correction Code (ECC) can be imple-
mented in the Nand Flash memories to identify
and correct errors in the data.
For every 2048 bits in the device it is recommend-
ed to implement 22 bits of ECC (16 bits for line par-
ity plus 6 bits for column parity).
An ECC model is available in VHDL or Verilog.
Contact the nearest ST Microelectronics sales of-
fice for more details.

Figure 24. Error Detection

Hardware Simulation Models
Behavioral simulation models. Denali Software
Corporation models are platform independent
functional models designed to assist customers in
performing entire system simulations (typical
VHDL/Verilog). These models describe the logic
behavior and timings of NAND Flash devices, and
so allow software to be developed before hard-
ware.
IBIS simulations models. IBIS (I/O Buffer Infor-
mation Specification) models describe the behav-
ior of the I/O buffers and electrical characteristics
of Flash devices.
These models provide information such as AC
characteristics, rise/fall times and package me-
chanical data, all of which are measured or simu-
lated at voltage and temperature ranges wider
than those allowed by target specifications.
IBIS models are used to simulate PCB connec-
tions and can be used to resolve compatibility is-
sues when upgrading devices. They can be
imported into SPICETOOLS.

New ECC generated

during read

XOR previous ECC

with new ECC

All results

= zero?

22 bit data = 0

YES

11 bit data = 1

1 bit data = 1

Correctable

Error

ECC Error

No Error

ai08332

>1 bit

= zero?

YES

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

32/56

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES

The Program and Erase times and the number of
Program/ Erase cycles per block are shown in

Ta-

ble 14.

Table 14. Program, Erase Times and Program Erase Endurance Cycles

MAXIMUM RATING

Stressing the device above the ratings listed in

Ta-

ble 15., Absolute Maximum Ratings

, may cause

permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.

Table 15. Absolute Maximum Ratings

Note: 1. Minimum Voltage may undershoot to 2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may over-

shoot to V

+ 2V for less than 20ns during transitions on I/O pins.

Parameters

NAND Flash

Unit

Min

Typ

Max

Page Program Time

200

500

µs

Block Erase Time

Program/Erase Cycles (per block)

100,000

cycles

Data Retention

years

Symbol

Parameter

Value

Unit

Min

Max

BIAS

Temperature Under Bias

125

°C

STG

Storage Temperature

150

°C

(1)

Input or Output Voltage

1.8V devices

0.6

2.7

3 V devices

0.6

4.6

Supply Voltage

1.8V devices

0.6

2.7

3 V devices

0.6

4.6

33/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

DC AND AC PARAMETERS

This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-

ment Conditions summarized in

Table

16., Operating and AC Measurement Conditions

Designers should check that the operating condi-
tions in their circuit match the measurement condi-
tions when relying on the quoted parameters.

Table 16. Operating and AC Measurement Conditions

Table 17. Capacitance

Note: T

= 25°C, f = 1 MHz. C

and C

I/O

are not 100% tested.

Parameter

NAND Flash

Units

Min

Max

Supply Voltage (V

)

1.8V devices

1.7

1.95

3V devices

2.7

3.6

Ambient Temperature (T

)

Grade 1

°C

Grade 6

°C

Load Capacitance (C

) (1 TTL GATE and C

)

1.8V devices

3V devices (2.7 - 3.6V)

3V devices (3.0 - 3.6V)

100

Input Pulses Voltages

1.8V devices

3V devices

0.4

2.4

Input and Output Timing Ref. Voltages

1.8V devices

0.9

3V devices

1.5

Input Rise and Fall Times

Symbol

Parameter

Test Condition

Typ

Max

Unit

Input Capacitance

= 0V

I/O

Input/Output Capacitance

= 0V

35/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Table 19. DC Characteristics, 3V Devices

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DD1

Operating

Current

Sequential

Read

RLRL

minimum

E=V

IL,

OUT

= 0 mA

DD2

Program

DD3

Erase

DD4

Stand-by Current (TTL),

128Mb, 256Mb, 512Mb devices

E=V

, WP=0V/V

Stand-by Current (TTL)

512Mb and 1Gb Dual Die devices

DD5

Stand-By Current (CMOS)

128Mb, 256Mb, 512Mb devices

E=V

-0.2,

WP=0/V

µA

Stand-By Current (CMOS)

512Mb and 1Gb Dual Die devices

100

µA

Input Leakage Current

= 0 to V

max

±10

µA

Output Leakage Current

OUT

= 0 to V

max

±10

µA

Input High Voltage

2.0

+0.3

Input Low Voltage

0.3

0.8

Output High Voltage Level

400µA

2.4

Output Low Voltage Level

= 2.1mA

0.4

(RB)

Output Low Current (RB)

= 0.4V

LKO

Supply Voltage (Erase and

Program lockout)

2.5

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

36/56

Table 20. AC Characteristics for Command, Address, Data Input

Note: 1. If t

ELWL

is less than 10ns, t

WLWH

must be minimum 35ns, otherwise, t

WLWH

may be minimum 25ns.

Symbol

Alt.

Symbol

Parameter

1.8V

Devices

Unit

ALLWL

ALS

Address Latch Low to Write Enable Low

AL Setup time

Min

ALHWL

Address Latch High to Write Enable Low

CLHWL

CLS

Command Latch High to Write Enable Low

CL Setup time

Min

CLLWL

Command Latch Low to Write Enable Low

DVWH

Data Valid to Write Enable High

Data Setup time

Min

ELWL

Chip Enable Low to Write Enable Low

E Setup time

Min

WHALH

ALH

Write Enable High to Address Latch High

AL Hold time

Min

WHALL

Write Enable High to Address Latch Low

WHCLH

CLH

Write Enable High to Command Latch High

CL hold time

Min

WHCLL

Write Enable High to Command Latch Low

WHDX

Write Enable High to Data Transition

Data Hold time

Min

WHEH

Write Enable High to Chip Enable High

E Hold time

Min

WHWL

Write Enable High to Write Enable Low

W High Hold
time

Min

WLWH

Write Enable Low to Write Enable High

W Pulse Width

Min

(1)

WLWL

Write Enable Low to Write Enable Low

Write Cycle time

Min

37/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Table 21. AC Characteristics for Operations

Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures

and

2. To break the sequential read cycle, E must be held High for longer than t

EHEL

3. ES = Electronic Signature.

Symbol

Alt.

Symbol

Parameter

1.8V

Devices

Unit

ALLRL1

Address Latch Low to
Read Enable Low

Read Electronic Signature

Min

ALLRL2

Read cycle

Min

BHRL

Ready/Busy High to Read Enable Low

Min

BLBH1

Ready/Busy Low to
Ready/Busy High

Read Busy time, 128Mb, 256Mb,
512Mb Dual Die

Max

µs

Read Busy time, 512Mb, 1Gb

Max

µs

BLBH2

PROG

Program Busy time

Max

500

µs

BLBH3

BERS

Erase Busy time

Max

BLBH4

Reset Busy time, during ready

Max

µs

WHBH1

RST

Write Enable High to
Ready/Busy High

Reset Busy time, during read

Max

µs

Reset Busy time, during program

Max

µs

Reset Busy time, during erase

Max

500

µs

CLLRL

CLR

Command Latch Low to Read Enable Low

Min

DZRL

Data Hi-Z to Read Enable Low

Min

EHBH

CRY

Chip Enable High to Ready/Busy High (E intercepted read)

Max

60 + t

(1)

60 + t

(1)

EHEL

CEH

Chip Enable High to Chip Enable Low

(2)

Min

100

EHQZ

CHZ

Chip Enable High to Output Hi-Z

Max

ELQV

CEA

Chip Enable Low to Output Valid

Max

RHBL

Read Enable High to Ready/Busy Low

Max

100

RHRL

REH

Read Enable High to
Read Enable Low

Read Enable High Hold time

Min

RHQZ

RHZ

Read Enable High to Output Hi-Z

Min

Max

RLRH

Read Enable Low to
Read Enable High

Read Enable Pulse Width

Min

RLRL

Read Enable Low to
Read Enable Low

Read Cycle time

Min

RLQV

REA

Read Enable Low to
Output Valid

Read Enable Access time

Max

Read ES Access time

(3)

WHBH

Write Enable High to
Ready/Busy High

Read Busy time, 128Mb, 256Mb,
512Mb Dual Die

Max

µs

Read Busy time, 512Mb, 1Gb

Max

µs

WHBL

Write Enable High to Ready/Busy Low

Max

100

WHRL

WHR

Write Enable High to Read Enable Low

Min

WLWL

Write Enable Low to
Write Enable Low

Write Cycle time

Min

45/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Ready/Busy Signal Electrical Characteristics
Figures

and

show the electrical charac-

teristics for the Ready/Busy signal. The value re-
quired for the resistor R

can be calculated using

the following equation:

So,

where I

is the sum of the input currents of all the

devices tied to the Ready/Busy signal. R

max is

determined by the maximum value of t

Figure 36. Ready/Busy AC Waveform

Figure 37. Ready/Busy Load Circuit

Figure 38. Resistor Value Versus Waveform Timings For Ready/Busy Signal

Note: T = 25°C.

min

VDDmax VOLmax

(

)

IOL

------------------------------------------------------------

min 1,8V

(

)

1,85V

3mA

---------------------------

min 3V

(

)

3,2V

8mA

---------------------------

AI07564B

busy

VOH

ready VDD

VOL

AI07563B

VDD

VSS

DEVICE

Open Drain Output

ibusy

ai07565B

RP (K

)

100

300

200

t r

, t

(ns)

1.7

0.85

30
1.7

1.7

ibusy

400

RP (K

)

100

300

200

ibusy

(mA)

2.4

1.2

0.8

0.6

100

200

300

400

3.6

400

VDD = 1.8V, CL = 30pF

VDD = 3.3V, CL = 100pF

t r

, t

(ns)

ibusy

(mA)

120

0.57

0.43

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

52/56

PART NUMBERING

Table 28. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits, in valid blocks, erased to '1'.
For further information on any aspect of this device, please contact your nearest ST Sales Office.

Example:

NAND512R3A

A ZA

Device Type
NAND = NAND Flash Memory

Density
128 = 128Mb
256 = 256Mb
512 = 512Mb
01G = 1Gb

Operating Voltage
R = V

= 1.7 to 1.95V

W = V

= 2.7 to 3.6V

Bus Width
3 = x8
4 = x16

Family Identifier
A = 528 Bytes/ 264 Word Page

Device Options
0 = No Options
1 = Automatic Page 0 Read at Power-up
2 = Chip Enable Don't Care Enabled
3 = Chip Enable Don't Care Enabled and Automatic Page 0 Read at Power-up

Product Version
A = 120nm process technology
(Single Die 128Mb, 256Mb, 512Mb) (Dual Die 512Mb, 1Gb)

Package
N = TSOP48 12 x 20mm (all devices)
V = WSOP48 12 x 17 x 0.65mm (128Mbit, 256Mbit and 512Mbit devices)
ZA = VFBGA55 8 x 10 x 1mm, 6x8 ball array, 0.8mm pitch (128Mbit and 256Mbit devices)
ZB = TFBGA55 8 x 10 x 1.2mm, 6x8 ball array, 0.8mm pitch (512Mbit Dual Die devices)
ZA = VFBGA63 8.5 x 15 x 1mm, 6x8 ball array, 0.8mm pitch (512Mbit devices)
ZB = TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit Dual Die devices)

Temperature Range
1 = 0 to 70 °C
6 = 40 to 85 °C

Option
blank = Standard Packing
T = Tape & Reel Packing
E = Lead Free Package, Standard Packing
F = Lead Free Package, Tape & Reel Packing

53/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

APPENDIX A. HARDWARE INTERFACE EXAMPLES

Nand Flash devices can be connected to a micro-
controller system bus for code and data storage.
For microcontrollers that have an embedded
NAND controller the NAND Flash can be connect-
ed without the addition of glue logic (see

Figure 45.

). However a minimum of glue logic is

required for general purpose microcontrollers that
do not have an embedded NAND controller. The
glue logic usually consists of a flip-flop to hold the
Chip Enable, Address Latch Enable and Com-
mand Latch Enable signals stable during com-
mand and address latch operations, and some
logic gates to simplify the firmware or make the de-
sign more robust.

Figure 46.

gives an example of how to connect a

NAND Flash to a general purpose microcontroller.
The additional OR gates allow the microcontrol-
ler's Output Enable and Write Enable signals to be
used for other peripherals. The OR gate between

A3 and CSn maps the flip-flop and NAND I/O in
different address spaces inside the same chip se-
lect unit, which improves the setup and hold times
and simplifies the firmware. The structure uses the
microcontroller DMA (Direct Memory Access) en-
gines to optimize the transfer between the NAND
Flash and the system RAM.
For any interface with glue logic, the extra delay
caused by the gates and flip-flop must be taken
into account. This delay must be added to the mi-
crocontroller's AC characteristics and register set-
tings to get the NAND Flash setup and hold times.
For mass storage applications (hard disk emula-
tions or systems where a huge amount of storage
is required) NAND Flash memories can be con-
nected together to build storage modules (see

Fig-

ure 47.

Figure 45. Connection to Microcontroller, Without Glue Logic

AI08045b

I/O

CSn

AD(24:16)

Microcontroller

NAND
Flash

PWAITEN

AD17

AD16

VDD

VDD or VSS

or General Purpose I/O

55/56

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

RELATED DOCUMENTATION

STMicroelectronics has published a set of application notes to support the NAND Flash memories. They
are available from the ST Website

www.st.com

. or from your local ST Distributor.

REVISION HISTORY

Table 29. Document Revision History

Date

Version

Revision Details

06-Jun-2003

1.0

First Issue

07-Aug-2003

2.0

Design Phase

27-Oct-2003

3.0

Engineering Phase

03-Dec-2003

4.0

Document promoted from Target Specification to Preliminary Data status.
V

changed to V

and I

to I

Title of

Table 2.

. changed to "

Product Description

" and Page Program Typical Timing

for NANDXXXR3A devices corrected.

Table 1., Product List

, inserted on page 2.

13-Apr-2004

5.0

WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed.

Figure 19., Cache Program Operation

, modified and note 2 modified. Note removed

for t

WLWH

timing in

Table 20., AC Characteristics for Command, Address, Data Input

Meaning of t

BLBH4

modified, partly replaced by t

WHBH1

and t

WHRL

min for 3V devices

modified in

Table 21., AC Characteristics for Operations

References removed from

Document Outline

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Document Outline

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