PRELIMINARY DATA

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

February 2006

Rev 1.0

1/58

NAND04GW3B

4 Gbit, 2112 Byte/1056 Word Page

3V, NAND Flash Memory

Feature summary

High density NAND Flash Memory

4 Gbit memory array

Up to 128 Mbit spare area

Cost effective solution for mass storage

applications

NAND Interface

x8 bus width

Multiplexed Address/ Data

Supply voltage

3.0V device: V

= 2.7 to 3.6V

Page size

(2048 + 64 spare) Bytes

Block size

(128K + 4K spare) Bytes

Page Read/Program

Random access: 25µs (max)

Sequential access: 30ns (min)

Page program time: 200µs (typ)

Copy Back Program mode

Fast page copy without external buffering

Cache Program and Cache Read modes

Internal Cache Register to improve the

program and read throughputs

Fast Block Erase

Block erase time: 2ms (typ)

Status Register

Electronic Signature

Chip Enable `don't care'

for simple interface with microcontroller

Serial Number option

Data protection

Hardware and Software Block Locking

Hardware Program/Erase locked during

Power transitions

Data integrity

100,000 Program/Erase cycles

10 years Data Retention

ECOPACK

package

Development tools

Error Correction Code software and

hardware models

Bad Blocks Management and Wear

Leveling algorithms

File System OS Native reference software

Hardware simulation models

TSOP48 12 x 20mm

www.st.com

Contents

NAND04GW3B

2/58

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1

Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2

Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3

Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5

Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6

Power-Up Read Enable, Lock/Unlock Enable (PRL) . . . . . . . . . . . . . . . . 13

3.7

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.8

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.9

Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.10

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.11

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1

Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2

Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3

Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4

Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5

Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1

Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1.1

Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1.2

Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

NAND04GW3B

Contents

3/58

6.2

Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3

Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.1

Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3.2

Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4

Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.5

Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6

Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.7

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.8

Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.1

Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.2

P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 28

6.8.3

P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.4

Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.8.5

Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.8.6

SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.9

Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1

Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2

Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3

Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.4

Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1

Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2

Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.3

Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4

Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.5

Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.6

Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.6.1

Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.6.2

IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 40

NAND04GW3B

List of tables

5/58

List of tables

Table 1.

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2.

Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3.

Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4.

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.

Address Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6.

Address Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7.

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8.

Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9.

Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10.

Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11.

Electronic Signature Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12.

Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13.

Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 14.

Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40

Table 15.

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 16.

Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 17.

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18.

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 19.

AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 20.

AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 21.

TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 55

Table 22.

Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 23.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

List of figures

NAND04GW3B

6/58

List of figures

Figure 1.

Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.

Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.

TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.

Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6.

Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.

Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8.

Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9.

Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10.

Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11.

Page Copy Back Program with Random Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12.

Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13.

Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14.

Blocks Unlock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15.

Read Block Lock Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16.

Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 17.

Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18.

Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 19.

Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20.

Equivalent Testing Circuit for AC Characteristics Measurement . . . . . . . . . . . . . . . . . . . . 43

Figure 21.

Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22.

Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 23.

Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 24.

Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 25.

Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 26.

Read Electronic Signature AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 27.

Page Read Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 28.

Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 29.

Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 30.

Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 31.

Program/Erase Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 32.

Program/Erase Disable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 33.

Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 34.

Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 35.

Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . . . 54

Figure 36.

Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 37.

TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 55

NAND04GW3B

Summary description

7/58

1 Summary

description

The NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories
that uses NAND cell technology. The NAND04GW3B has a density of 4 Gbit and operates
from a 3V voltage supply. The size of a Page is 2112 Bytes (2048 + 64 spare).

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8
Input/Output bus. This interface reduces the pin count and makes it possible to migrate to
other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of
NAND Flash devices it is strongly recommended to implement an Error Correction Code
(ECC).

The device has hardware and software security features:

A Write Protect pin is available to give a hardware protection against program and
erase operations.

A Block Locking scheme is available to provide user code and/or data protection.

The device features an open-drain Ready/Busy output that can be used to identify if the
Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output
allows the Ready/Busy pins from several memories to be connected to a single pull-up
resistor.

A Copy Back Program command is available to optimize the management of defective
blocks. When a Page Program operation fails, the data can be programmed in another page
without having to resend the data to be programmed.

The NAND04GW3B has Cache Program and Cache Read features which improve the
program and read throughputs for large files. During Cache Programming, the device loads
the data in a Cache Register while the previous data is transferred to the Page Buffer and
programmed into the memory array. During Cache Reading, the device loads the data in a
Cache Register while the previous data is transferred to the I/O Buffers to be read.

The device has the Chip Enable Don't Care feature, which allows code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the read operation.

The NAND04GW3B has the option of a Unique Identifier (serial number), which allows each
device to be uniquely identified.

The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not
described in the datasheet. For more details of this option contact your nearest ST Sales
office.

The device is available in a TSOP48 (12 x 20mm) package. In order to meet environmental
requirements, ST offers the NAND04GW3B in ECOPACK

package. ECOPACK packages

are Lead-free. The category of second Level Interconnect is marked on the package and on
the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings
related to soldering conditions are also marked on the inner box label. ECOPACK is an ST
trademark.

For information on how to order these options refer to

Table 22: Ordering Information

Scheme

. Devices are shipped from the factory with Block 0 always valid and the memory

content bits, in valid blocks, erased to '1'.

NAND04GW3B

Memory array organization

11/58

Memory array organization

The memory array is made up of NAND structures where 32 cells are connected in series.

The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.

The pages are split into a 2048 Byte main area and a spare area of 64 Bytes. Refer to

Figure 4: Memory Array Organization

2.1 Bad

Blocks

The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is
blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional
Bad Blocks may develop during the lifetime of the device.

The Bad Block Information is written prior to shipping (refer to

Section 8.1: Bad Block

Management

for more details).

Table 3

shows the minimum number of valid blocks. The values shown include both the Bad

Blocks that are present when the device is shipped and the Bad Blocks that could develop
later on.

These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to

Section 8: Software algorithms

Table 3.

Valid Blocks

Density of Device

Min

Max

4 Gbits

4016

4096

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Signal descriptions

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3 Signal

descriptions

See

Figure 2: Logic Diagram

, and

Table 2: Signal Names

, for a brief overview of the signals

connected to this device.

3.1 Inputs/Outputs

(I/O0-I/O7)

Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read
operation or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.

3.2

Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command
Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.

3.3

Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command
Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.

3.4 Chip

Enable

(E)

The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is low, V

, the device is selected. If Chip Enable goes

high, v

, while the device is busy, the device remains selected and does not go into standby

mode.

3.5 Read

Enable

(R)

The Read Enable pin, R, controls the sequential data output during Read operations. Data
is valid t

RLQV

after the falling edge of R. The falling edge of R also increments the internal

column address counter by one.

3.6

Power-Up Read Enable, Lock/Unlock Enable (PRL)

The Power-Up Read Enable, Lock/Unlock Enable input, PRL, is used to enable and disable
the lock mechanism. When PRL is High, V

, the device is in Block Lock mode.

If the Power-Up Read Enable, Lock/Unlock Enable input is not required, the PRL pin should
be left unconnected (Not Connected) or connected to V

Signal descriptions

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3.7 Write

Enable

(W)

The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.

During power-up and power-down a recovery time of 10µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.

3.8

Write Protect (WP)

The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V

, the device does not accept any

program or erase operations.

It is recommended to keep the Write Protect pin Low, V

, during power-up and power-down.

3.9 Ready/Busy

(RB)

The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
Controller is currently active.

When Ready/Busy is Low, V

, a read, program or erase operation is in progress. When the

operation completes Ready/Busy goes High, V

The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.

Refer to the

Section 11.1: Ready/Busy Signal Electrical Characteristics

for details on how to

calculate the value of the pull-up resistor.

3.10 V

Supply Voltage

provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (read, program and erase).

An internal voltage detector disables all functions whenever V

is below V

LKO

(see

Table 18

) to protect the device from any involuntary program/erase during power-transitions.

Each device in a system should have V

decoupled with a 0.1µF capacitor. The PCB track

widths should be sufficient to carry the required program and erase currents

3.11 V

Ground

Ground, V

SS,

is the reference for the power supply. It must be connected to the system

ground.

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Bus operations

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4 Bus

operations

There are six standard bus operations that control the memory. Each of these is described
in this section, see

Table 4: Bus Operations

, for a summary.

Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.

4.1 Command

Input

Command Input bus operations are used to give commands to the memory.

The Commands are input on I/O0-I/O7. Commands are accepted when Chip Enable is Low,
Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write Enable signal.

See

Figure 21

and

Table 19

for details of the timings requirements.

4.2 Address

Input

Address Input bus operations are used to input the memory addresses.

Addresses are input on I/O0-I/O7. Five bus cycles are required to input the addresses (refer
to

Table 5: Address Insertion

The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal.

See

Figure 22

and

Table 19

for details of the timings requirements.

4.3 Data

Input

Data Input bus operations are used to input the data to be programmed.

Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.

See

Figure 23

and

Table 19

and

Table 20

for details of the timings requirements.

4.4 Data

Output

Data Output bus operations are used to read: the data in the memory array, the Status
Register, the lock status, the Electronic Signature

and the Unique Identifier.

Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.

The data is output sequentially using the Read Enable signal.

See

Figure 24

and

Table 20

for details of the timings requirements.

Bus operations

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4.5 Write

Protect

Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.

4.6 Standby

When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.

Command set

Table 4.

Bus Operations

Bus Operation

I/O0 - I/O7

Command Input

Rising

(1)

WP must be V

when issuing a program or erase command.

Command

Address Input

Rising

Address

Data Input

Rising

Data Input

Data Output

Falling

Data Output

Write Protect

Standby

Table 5.

Address Insertion

Bus

Cycle

(1)

Any additional address input cycles will be ignored.

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

A11

A10

A19

A18

A17

A16

A15

A14

A13

A12

A27

A26

A25

A24

A23

A22

A21

A20

A29

A28

Table 6.

Address Definition

Address

Definition

A0 - A11

Column Address

A12 - A17

Page Address

A18 - A29

Block Address

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Command set

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5 Command

set

All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.

The Commands are summarized in

Table 7

Table 7.

Commands

Command

Bus Write Operations

(1)

Commands

accepted

during busy

cycle

Read

00h

(2)

30h

Random Data Output

05h

E0h

Cache Read

00h

31h

Exit Cache Read

34h

Yes

(3)

Page Program

(Sequential Input default)

80h

10h

Random Data Input

85h

Copy Back Program

00h

35h

85h

10h

Cache Program

80h

15h

Block Erase

60h

D0h

Reset

FFh

Yes

Read Electronic Signature

90h

Read Status Register

70h

Yes

Read Block Lock Status

7Ah

Blocks Unlock

23h

24h

Blocks Lock

2Ah

Blocks Lock-Down

2Ch

The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are
not shown.

For consecutive Read operations the 00h command does not need to be repeated.

Only during Cache Read busy.

Device operations

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6 Device

operations

The following section gives the details of the device operations.

6.1 Read

Memory

Array

At Power-Up the device defaults to Read mode. To enter Read mode from another mode the
Read command must be issued, see

Table 7: Commands

. Once a Read command is

issued, subsequent consecutive Read commands only require the confirm command code
(30h).

Once a Read command is issued two types of operations are available: Random Read and
Page Read.

6.1.1 Random

Read

Each time the Read command is issued the first read is Random Read.

6.1.2 Page

Read

After the first Random Read access, the page data (2112 Bytes) are transferred to the Page
Buffer in a time of t

WHBH

(refer to

Table 20

for value). Once the transfer is complete the

Ready/Busy signal goes High. The data can then be read out sequentially (from selected
column address to last column address) by pulsing the Read Enable signal.

The device can output random data in a page, instead of the consecutive sequential data, by
issuing a Random Data Output command.

The Random Data Output command can be used to skip some data during a sequential
data output.

The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command.

The Random Data Output command can be issued as many times as required within a
page.

The Random Data Output command is not accepted during Cache Read operations.

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Device operations

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6.2 Cache

Read

The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.

An Cache Read operation consists of three steps (see

Table 7: Commands

One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)

2. Five

(refer

Table 5: Address Insertion

) bus cycles are then required to input the Start

Address

One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.

The Start Address must be at the beginning of a page (Column Address = 00h, see

Table 6:

Address Definition

). This allows the data to be output uninterrupted after the latency time

BLBH1

), see

Figure 7: Cache Read Operation

The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.

Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.

During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = `0'), or has completed (SR5 = `1'), while SR6 indicates whether the Cache Register
is ready to download new data.

To exit the Cache Read operation an Exit Cache Read command must be issued (see

Table 7: Commands

If the Exit Cache Read command is issued while the device is internally reading page n+1,
page n will still be output, but not page n+1.

Figure 7.

Cache Read Operation

I/O

Address

Inputs

ai08661b

00h

Read

Setup

Code

31h

Cache

Read

Confirm

Code

Busy

tBLBH1

(Read Busy time)

1st page

Data Output

2nd page

3rd page

last page

34h

Exit

Cache

Read

Code

Block N

tRHRL2

Device operations

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6.3 Page

Program

The Page Program operation is the standard operation to program data to the memory
array. Generally, data is programmed sequentially, however the device does support
Random Input within a page.

The memory array is programmed by page, however partial page programming is allowed
where any number of Bytes (1 to 2112) can be programmed.

The maximum number of consecutive partial page program operations allowed in the same
page is four. After exceeding this a Block Erase command must be issued before any further
program operations can take place in that page.

6.3.1 Sequential

Input

To input data sequentially the addresses must be sequential and remain in one block.

For Sequential Input each Page Program operation consists of five steps (see

Figure 8:

Page Program Operation

One bus cycle is required to setup the Page Program (Sequential Input) command (see

Table 7: Commands

)

Five bus cycles are then required to input the program address (refer to

Table 5:

Address Insertion

The data is then loaded into the Data Registers

One bus cycle is required to issue the Page Program confirm command to start the
P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3.

the P/E/R Controller then programs the data into the array.

6.3.2

Random Data Input

During a Sequential Input operation, the next sequential address to be programmed can be
replaced by a random address, by issuing a Random Data Input command. The following
two steps are required to issue the command:

One bus cycle is required to setup the Random Data Input command (see

Table 7:

Commands

)

Two bus cycles are then required to input the new column address (refer to

Table 5:

Address Insertion

)

Random Data Input can be repeated as often as required in any given page.

Once the program operation has started the Status Register can be read using the Read
Status Register command. During program operations the Status Register will only flag
errors for bits set to '1' that have not been successfully programmed to '0'.

During the program operation, only the Read Status Register and Reset commands will be
accepted, all other commands will be ignored.

Once the program operation has completed the P/E/R Controller bit SR6 is set to `1' and the
Ready/Busy signal goes High.

The device remains in Read Status Register mode until another valid command is written to
the Command Interface.

Device operations

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6.4

Copy Back Program

The Copy Back Program operation is used to copy the data stored in one page and
reprogram it in another page.

The Copy Back Program operation does not require external memory and so the operation
is faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.

If the Copy Back Program operation fails an error is signalled in the Status Register.
However as the standard external ECC cannot be used with the Copy Back Program
operation bit error due to charge loss cannot be detected. For this reason it is recommended
to limit the number of Copy Back Program operations on the same data and or to improve
the performance of the ECC.

The Copy Back Program operation requires four steps:

The first step reads the source page. The operation copies all 2112 Bytes from the
page into the Data Buffer. It requires:

One bus write cycle to setup the command

4 bus write cycles to input the source page address

One bus write cycle to issue the confirm command code

When the device returns to the ready state (Ready/Busy High), the next bus write cycle
of the command is given with the 4 bus cycles to input the target page address.

Then the confirm command is issued to start the P/E/R Controller.

To see the Data Input cycle for modifying the source page and an example of the Copy Back
Program operation refer to

Figure 10: Copy Back Program

A data input cycle to modify a portion or a multiple distant portion of the source page, is
shown in

Figure 11: Page Copy Back Program with Random Data Input

Figure 10.

Copy Back Program

Copy back program is only permitted between odd address pages or even address pages.

I/O

Source

Add Inputs

ai09858b

85h

Copy Back

Code

Read

Code

Read Status Register

Target

Add Inputs

tBLBH1

(Read Busy time)

Busy

tBLBH2

(Program Busy time)

00h

10h

70h

SR0

Busy

35h

Device operations

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6.5 Cache

Program

The Cache Program operation is used to improve the programming throughput by
programming data using the Cache Register. The Cache Program operation can only be
used within one block. The Cache Register allows new data to be input while the previous
data that was transferred to the Page Buffer is programmed into the memory array.

Each Cache Program operation consists of five steps (refer to

Figure 12: Cache Program

Operation

First of all the program setup command is issued (one bus cycle to issue the program
setup command then four bus write cycles to input the address), the data is then input
(up to 2112 Bytes) and loaded into the Cache Register.

One bus cycle is required to issue the confirm command to start the P/E/R Controller.

The P/E/R Controller then transfers the data to the

Page Buffer. During this the device

is busy for a time of t

WHBH2

Once the data is loaded into the Page Buffer the P/E/R Controller programs the data
into the memory array. As soon as the Cache Registers are empty (after t

WHBH2

) a new

Cache program command can be issued, while the internal programming is still
executing.

Once the program operation has started the Status Register can be read using the Read
Status Register command. During Cache Program operations SR5 can be read to find out
whether the internal programming is ongoing (SR5 = `0') or has completed (SR5 = `1') while
SR6 indicates whether the Cache Register is ready to accept new data. If any errors have
been detected on the previous page (Page N-1), the Cache Program Error Bit SR1 will be
set to `1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1'.

When the next page (Page N) of data is input with the Cache Program command, t

WHBH2

affected by the pending internal programming. The data will only be transferred from the
Cache Register to the Page Buffer when the pending program cycle is finished and the Page
Buffer is available.

If the system monitors the progress of the operation using only the Ready/Busy signal, the
last page of data must be programmed with the Page Program confirm command (10h).

If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must
be polled to find out if the last programming is finished before starting any other operations.

Figure 12.

Cache Program Operation

Up to 64 pages can be programmed in one Cache Program operation.

CACHEPG

is the program time for the last page + the program time for the (last

page

(Program command cycle time

+ Last page data loading time).

I/O

Address

Inputs

ai08672

80h

Page

Program

Code

Read Status

Busy

Data

Inputs

15h

Cache

Program

Code

80h

Page

Program

Code

15h

Cache Program

Confirm Code

Busy

Last Page

tBLBH5

(Cache Busy time)

tBLBH5

tCACHEPG

SR0

70h

80h

10h

Page

Program

Confirm Code

Busy

First Page

Second Page

(can be repeated up to 63 times)

Address

Inputs

Data

Inputs

Address

Inputs

Data

Inputs

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Device operations

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6.6 Block

Erase

Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to `1'. All previous data in the block is lost.

An erase operation consists of three steps (refer to

Figure 13: Block Erase Operation

One bus cycle is required to setup the Block Erase command. Only addresses A18-
A29 are used, the other address inputs are ignored.

Three bus cycles are then required to load the address of the block to be erased. Refer
to

Table 6: Address Definition

for the block addresses of each device.

One bus cycle is required to issue the Block Erase confirm command to start the P/E/R
Controller.

The operation is initiated on the rising edge of write Enable, W, after the confirm command
is issued. The P/E/R Controller handles Block Erase and implements the verify process.

During the Block Erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.

Once the program operation has completed the P/E/R Controller bit SR6 is set to `1' and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit
SR0 is `0', otherwise it is set to `1'.

Figure 13.

Block Erase Operation

6.7 Reset

The Reset command is used to reset the Command Interface and Status Register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.

If the device has already been reset then the new Reset command will not be accepted.

The Ready/Busy signal goes Low for t

BLBH4

after the Reset command is issued. The value

of t

BLBH4

depends on the operation that the device was performing when the command was

issued, refer to

Table 20

for the values.

I/O

Block Address

Inputs

SR0

ai07593

D0h

70h

60h

Block Erase

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH3

(Erase Busy time)

Device operations

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6.8

Read Status Register

The device contains a Status Register which provides information on the current or previous
Program or Erase operation. The various bits in the Status Register convey information and
errors on the operation.

The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the Status
Register.

After the Read Status Register command has been issued, the device remains in Read
Status Register mode until another command is issued. Therefore if a Read Status Register
command is issued during a Random Read cycle a new Read command must be issued to
continue with a Page Read operation.

The Status Register bits are summarized in

Table 8: Status Register Bits

,. Refer to

Table 8:

Status Register Bits

in conjunction with the following text descriptions.

6.8.1

Write Protection Bit (SR7)

The Write Protection bit can be used to identify if the device is protected or not. If the Write
Protection bit is set to `1' the device is not protected and program or erase operations are
allowed. If the Write Protection bit is set to `0' the device is protected and program or erase
operations are not allowed.

6.8.2 P/E/R

Controller

and

Cache Ready/Busy Bit (SR6)

Status Register bit SR6 has two different functions depending on the current operation.

During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which
indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0',
the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to
accept new data.

During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the
P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R
Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive
(device is ready).

6.8.3

P/E/R Controller Bit (SR5)

The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is
busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready).

6.8.4

Cache Program Error Bit (SR1)

The Cache Program Error bit can be used to identify if the previous page (page N-1) has
been successfully programmed or not in a Cache Program operation. SR1 is set to '1' when

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Device operations

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the Cache Program operation has failed to program the previous page (page N-1) correctly.
If SR1 is set to `0' the operation has completed successfully.

The Cache Program Error bit is only valid during Cache Program operations, during other
operations it is Don't Care.

6.8.5

Error Bit (SR0)

The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The
Error Bit is set to '1' when a program or erase operation has failed to write the correct data to
the memory. If the Error Bit is set to `0' the operation has completed successfully. The Error
Bit SR0, in a Cache Program operation, indicates a failure on Page N.

6.8.6

SR4, SR3 and SR2 are Reserved

Table 8.

Status Register Bits

Bit

Name

Logic Level

Definition

SR7

Write Protection

'1'

Not Protected

'0'

Protected

SR6

(1)

Program/ Erase/ Read

Controller

'1'

P/E/R C inactive, device ready

'0'

P/E/R C active, device busy

Cache Ready/Busy

'1'

Cache Register ready (Cache Program only)

'0'

Cache Register busy (Cache Program only)

SR5

Program/ Erase/ Read

Controller

(2)

'1'

P/E/R C inactive, device ready

'0'

P/E/R C active, device busy

SR4, SR3, SR2

Reserved

Don't Care

SR1

Cache Program Error

(3)

'1'

Page N-1 failed in Cache Program operation

'0'

Page N-1 programmed successfully

SR0

(1)

Generic Error

`1'

Error operation failed

`0'

No Error operation successful

Cache Program Error

`1'

Page N failed in Cache Program operation

`0'

Page N programmed successfully

The SR6 bit and SR0 bit have a different meaning during Cache Program and Cache Read operations.

Only valid for Cache Program operations, for other operations it is same as SR6.

Only valid for Cache Program operations, for other operations it is Don't Care.

Device operations

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6.9

Read Electronic Signature

The device contains a Manufacturer Code and Device Code. To read these codes three steps
are required:

One Bus Write cycle to issue the Read Electronic Signature command (90h)

One Bus Write cycle to input the address (00h)

Four Bus Read Cycles to sequentially output the data (as shown in

Table 9: Electronic

Signature

Table 9.

Electronic Signature

Byte 1

Byte 2

Byte 3

Byte 4

Manufacturer Code

Device code

20h

DCh

80h

(see

Table 10

)

95h

(see

Table 11

)

Table 10.

Electronic Signature Byte 3

I/O

Definition

Value

Description

I/O1-I/O0

Internal Chip number

0 0

0 1

1 0

1 1

I/O3-I/O2

Cell Type

0 0

0 1

1 0

1 1

2-level cell

4-level cell

8-level cell

16-level cell

I/O5-I/O4

Number of simultaneously

programmed pages

0 0

0 1

1 0

1 1

I/O6

Interleaved Programming
between multiple devices

Not supported

Supported

I/O7

Cache Program

Not supported

Supported

Data Protection

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7 Data

Protection

The device has both hardware and software features to protect against program and erase
operations.

It features a Write Protect, WP, pin, which can be used to protect the device against program
and erase operations. It is recommended to keep WP at V

during power-up and power-

down.

In addition, to protect the memory from any involuntary program/erase operations during
power-transitions, the device has an internal voltage detector which disables all functions
whenever V

is below V

LKO

(see

Table 18: DC Characteristics

The device features a Block Lock mode, which is enabled by setting the Power-Up Read
Enable, Lock/Unlock Enable, PRL, signal to High.

The Block Lock mode has two levels of software protection.

Blocks Lock/Unlock

Blocks Lock-down

Refer to

Figure 16: Block Protection State Diagram

for an overview of the protection

mechanism.

7.1 Blocks

Lock

All the blocks are locked simultaneously by issuing a Blocks Lock command (see

Table 7:

Commands

All blocks are locked after power-up and when the Write Protect signal is Low.

Once all the blocks are locked, one sequence of consecutive blocks can be unlocked by
using the Blocks Unlock command.

Refer to

Figure 21: Command Latch AC Waveforms

for details on how to issue the

command.

7.2 Blocks

Unlock

A sequence of consecutive locked blocks can be unlocked, to allow program or erase
operations, by issuing an Blocks Unlock command (see

Table 7: Commands

The Blocks Unlock command consists of four steps:

One bus cycle to setup the command

Three bus cycles to give the Start Block Address (refer to

Table 6: Address Definition

and

Figure 14: Blocks Unlock Operation

)

One bus cycle to confirm the command

Three bus cycles to give the End Block Address (refer to

Table 6: Address Definition

and

Figure 14: Blocks Unlock Operation

The Start Block Address must be nearer the logical LSB (Least Significant Bit) than End
Block Address.

NAND04GW3B

Data Protection

33/58

If the Start Block Address is the same as the End Block Address, only one block is unlocked.

Only one consecutive area of blocks can be unlocked at any one time. It is not possible to
unlock multiple areas.

Figure 14.

Blocks Unlock Operation

7.3 Blocks

Lock-Down

The Lock-Down feature provides an additional level of protection. A Locked-down block
cannot be unlocked by a software command. Locked-Down blocks can only be unlocked by
setting the Write Protect signal to Low for a minimum of 100ns.

Only locked blocks can be locked-down. The command has no affect on unlocked blocks.

Refer to

Figure 21: Command Latch AC Waveforms

for details on how to issue the

command.

7.4 Block

Lock

Status

In Block Lock mode (PRL High) the Block Lock Status of each block can be checked by
issuing a Read Block Lock Status command (see

Table 7: Commands

The command consists of:

One bus cycle to give the command code

Three bus cycles to give the block address

After this, a read cycle will then output the Block Lock Status on the I/O pins on the falling
edge of Chip Enable or Read Enable, whichever occurs last. Chip Enable or Read Enable
do not need to be toggled to update the status.

The Read Block Lock Status command will not be accepted while the device is busy (RB
Low).

The device will remain in Read Block Lock Status mode until another command is issued.

I/O

Start Block Address, 3 cycles

ai08670

23h

Blocks Unlock

Command

Add1

Add2

Add3

24h

Add1

Add2

Add3

End Block Address, 3 cycles

Software algorithms

NAND04GW3B

36/58

8 Software

algorithms

This section gives information on the software algorithms that ST recommends to implement
to manage the Bad Blocks and extend the lifetime of the NAND device.

NAND Flash memories are programmed and erased by Fowler-Nordheim tunnelling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see

Table 14: Program, Erase Times and Program Erase Endurance Cycles

for

value) and it is recommended to implement Garbage Collection, a Wear-Leveling Algorithm
and an Error Correction Code, to extend the number of program and erase cycles and
increase the data retention.

To help integrate a NAND memory into an application ST Microelectronics can provide a File
System OS Native reference software, which supports the basic commands of file
management.

Contact the nearest ST Microelectronics sales office for more details.

8.1 Bad

Block

Management

Devices with Bad Blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A Bad Block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.

The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad
Block Information is written prior to shipping. Any block, where the 1st and 6th Bytes, or 1st
Word,

in the spare area of the 1st page, does not contain FFh, is a Bad Block.

The Bad Block Information must be read before any erase is attempted as the Bad Block
Information may be erased. For the system to be able to recognize the Bad Blocks based on
the original information it is recommended to create a Bad Block table following the
flowchart shown in

Figure 17: Bad Block Management Flowchart

8.2 Block

Replacement

Over the lifetime of the device additional Bad Blocks may develop. In this case the block has
to be replaced by copying the data to a valid block. These additional Bad Blocks can be
identified as attempts to program or erase them will give errors in the Status Register.

As the failure of a page program operation does not affect the data in other pages in the
same block, the block can be replaced by re-programming the current data and copying the
rest of the replaced block to an available valid block. The Copy Back Program command can
be used to copy the data to a valid block.

See

Section 6.4: Copy Back Program

for more details.

Refer to

Table 13: Block Failure

for the recommended procedure to follow if an error occurs

during an operation.

Software algorithms

NAND04GW3B

38/58

8.3 Garbage

Collection

When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.

To free this memory space and allow further program operations it is recommended to
implement a Garbage Collection algorithm. In a Garbage Collection software the valid
pages are copied into a free area and the block containing the invalid pages is erased (see

Figure 18: Garbage Collection

8.4 Wear-leveling

Algorithm

For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm
to monitor and spread the number of write cycles per block.

In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.

The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:

First Level Wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles

Second Level Wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.

The Second Level Wear-leveling is triggered when the difference between the maximum
and the minimum number of write cycles per block reaches a specific threshold.

8.5

Error Correction Code

An Error Correction Code (ECC) can be implemented in the NAND Flash memories to
identify and correct errors in the data.

For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for
line parity plus 6 bits for column parity).

An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics
sales office for more details.

NAND04GW3B

Software algorithms

39/58

Figure 19.

Error Detection

8.6

Hardware simulation models

8.6.1

Behavioral simulation models

Denali Software Corporation models are platform independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND Flash devices, and so allow
software to be developed before hardware.

8.6.2 IBIS

simulations

models

IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers
and electrical characteristics of Flash devices.

These models provide information such as AC characteristics, rise/fall times and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.

IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.

New ECC generated

during read

XOR previous ECC

with new ECC

All results

= zero?

22 bit data = 0

YES

11 bit data = 1

1 bit data = 1

Correctable

Error

ECC Error

No Error

ai08332

>1 bit

= zero?

YES

NAND04GW3B

Maximum rating

41/58

10 Maximum

rating

Stressing the device above the ratings listed in

Table 15: Absolute Maximum Ratings

, may

cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 15.

Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

Min

Max

BIAS

Temperature Under Bias

125

°C

STG

Storage Temperature

150

°C

(1)

Minimum Voltage may undershoot to 2V for less than 20ns during transitions on input and I/O pins.
Maximum voltage may overshoot to V

+ 2V for less than 20ns during transitions on I/O pins.

Input or Output Voltage

0.6

4.6

Supply Voltage

0.6

4.6

DC and AC parameters

NAND04GW3B

42/58

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in

Table 16

. Designers should check that the operating conditions in their circuit match the

measurement conditions when relying on the quoted parameters.

Table 16.

Operating and AC Measurement Conditions

Parameter

NAND Flash

Units

Min

Max

Supply Voltage (V

)

2.7

3.6

Ambient Temperature (T

)

Grade 1

°C

Grade 6

°C

Load Capacitance (C

) (1 TTL GATE

and C

)

Input Pulses Voltages

Input and Output Timing Ref. Voltages

Output Circuit Resistor R

ref

8.35

Input Rise and Fall Times

Table 17.

Capacitance

(1)

= 25°C, f = 1MHz. C

and C

I/O

are not 100% tested.

Symbol

Parameter

Test Condition

Typ

Max

Unit

Input Capacitance

= 0V

I/O

Input/Output
Capacitance

(2)

Input/output capacitances double in stacked devices.

= 0V

NAND04GW3B

DC and AC parameters

43/58

Figure 20.

Equivalent Testing Circuit for AC Characteristics Measurement

Ai11085

NAND Flash

2Rref

VDD

2Rref

GND

Table 18.

DC Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DD1

Operating

Current

Sequential

Read

RLRL

minimum

E=V

IL,

OUT

= 0 mA

DD2

Program

DD3

Erase

DD4

Standby current (TTL)

(1)

E=V

, WP=0/V

DD5

Standby Current (CMOS)

(1)

E=V

-0.2,

WP=0/V

µA

Input Leakage Current

(1)

= 0 to V

max

±10

µA

Output Leakage Current

(1)

OUT

= 0 to V

max

±10

µA

Input High Voltage

0.8V

+0.3

Input Low Voltage

-0.3

0.2V

Output High Voltage Level

= -400µA

2.4

Output Low Voltage Level

= 2.1mA

0.4

(RB)

Output Low Current (RB)

= 0.4V

LKO

Supply Voltage (Erase and

Program lockout)

1.7

leakage current and standby current double in stacked devices.

DC and AC parameters

NAND04GW3B

44/58

Table 19.

AC Characteristics for Command, Address, Data Input

Symbol

Alt.

Symbol

Parameter

NAND04GW3B Unit

ALLWH

ALS

Address Latch Low to Write Enable high

AL Setup time

Min

ALHWH

Address Latch High to Write Enable high

CLHWH

CLS

Command Latch High to Write Enable high

CL Setup time

Min

CLLWH

Command Latch Low to Write Enable high

DVWH

Data Valid to Write Enable High

Data Setup time

Min

ELWH

Chip Enable Low to Write Enable high

E Setup time

Min

WHALH

ALH

Write Enable High to Address Latch High

AL Hold time

Min

WHCLH

CLH

Write Enable High to Command Latch High

CL hold time

Min

WHCLL

Write Enable High to Command Latch Low

WHDX

Write Enable High to Data Transition

Data Hold time

Min

WHEH

Write Enable High to Chip Enable High

E Hold time

Min

WHWL

Write Enable High to Write Enable Low

W High Hold
time

Min

WLWH

Write Enable Low to Write Enable High

W Pulse Width

Min

WLWL

Write Enable Low to Write Enable Low

Write Cycle time

Min

Table 20.

AC Characteristics for Operations

(1)(2)

Symbol

Alt.

Symbol

Parameter

NAND04GW3B

Unit

ALLRL1

Address Latch Low to
Read Enable Low

Read Electronic Signature

Min

ALLRL2

Read cycle

Min

BHRL

Ready/Busy High to Read Enable Low

Min

BLBH1

Ready/Busy Low to
Ready/Busy High

Read Busy time

Max

µs

BLBH2

PROG

Program Busy time

Max

700

µs

BLBH3

BERS

Erase Busy time

Max

BLBH4

Reset Busy time, during ready

Max

µs

BLBH5

CBSY

Cache Busy time

Typ

µs

Max

700

µs

WHBH1

RST

Write Enable High to
Ready/Busy High

Reset Busy time, during read

Max

µs

Reset Busy time, during program

Max

µs

Reset Busy time, during erase

Max

500

µs

CLLRL

CLR

Command Latch Low to Read Enable Low

Min

DZRL

Data Hi-Z to Read Enable Low

Min

EHQZ

CHZ

Chip Enable High to Output Hi-Z

Max

RHQZ

RHZ

Read Enable High to Output Hi-z

Max

NAND04GW3B

DC and AC parameters

45/58

ELQV

CEA

Chip Enable Low to Output Valid

Max

RHRL1

REH

Read Enable High to
Read Enable Low

Read Enable High Hold time

Min

EHQX

COH

Chip Enable high to Output Hold

Min

RLRH

Read Enable Low to
Read Enable High

Read Enable Pulse Width

Min

RLRL

Read Enable Low to
Read Enable Low

Read Cycle time

Min

RLQV

REA

Read Enable Low to
Output Valid

Read Enable Access time

Max

Read ES Access time

(3)

WHBH

Write Enable High to
Ready/Busy High

Read Busy time

Max

µs

WHBL

Write Enable High to Ready/Busy Low

Max

100

WHRL

WHR

Write Enable High to Read Enable Low

Min

RHRL2

CRRH

Read Enable High hold time during Cache Read operation

Min

100

WHWH

ADL

(4)

Last Address latched to Data Loading Time during Program
operations

Min

100

VHWH

VLWH

(5)

Write Protection time

Min

100

The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See

Figure 33

Figure 34

and

Figure 35

To break the sequential read cycle, E must be held High for longer than t

EHEL

ES = Electronic Signature.

ADL

is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.

During a Program/Erase Enable Operation, t

is the delay from WP high to W High.

During a Program/Erase Disable Operation, t

is the delay from WP Low to W High.

Table 20.

AC Characteristics for Operations

(1)(2)

(continued)

NAND04GW3B

58/58

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