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PRELIMINARY DATA
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD935G2
Configurable Memory System on a Chip
for 8-Bit Microcontrollers
FEATURES SUMMARY
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5 V10% Single Supply Voltage:
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Up to 4 Mbit of Primary Flash Memory (8
uniform sectors)
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256Kbit Secondary Flash Memory (4 uniform
sectors)
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Up to 64 Kbit SRAM
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Over 3,000 Gates of PLD: DPLD
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52 Reconfigurable I/O ports
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Enhanced JTAG Serial Port
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Programmable power management
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High Endurance:
100,000 Erase/Write Cycles of Flash Memory
1,000 Erase/Write Cycles of PLD
Figure 1. Packages
TQFP80 (U)
1
1.0
Introduction
PSD9XX Family
PSD935G2
Configurable Memory System on a Chip
for 8-Bit Microcontrollers
The PSD9XX series of Programmable Microcontroller (MCU) Peripherals brings
In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a
simple and flexible solution for embedded designs. PSD9XX devices combine many of the
peripheral functions found in MCU based applications:
4 Mbit of Flash memory
A secondary Flash memory for boot or data
Over 3,000 gates of Flash programmable logic
64 Kbit SRAM
Reconfigurable I/O ports
Programmable power management.
PSD9XX Family
PSD935G2
2
1.0
Introduction
(Cont.)
Please refer to the revision block at the end of this
document for updated information.
The PSD935G2 device offers two methods to program PSD Flash memory while the PSD
is soldered to a circuit board.
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In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG-ISP interface is included on the PSD enabling the
entire device (both flash memories, the PLD, and all configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation,
which means the PSD can be programmed anytime, even while completely blank.
The innovative JTAG interface to flash memories is an industry first, solving key
problems faced by designers and manufacturing houses, such as:
First time programming How do I get firmware into the flash the very first time?
JTAG is the answer, program the PSD while blank with no MCU involvement.
Inventory build-up of pre-programmed devices How do I maintain an accurate
count of pre-programmed flash memory and PLD devices based on customer
demand? How many and what version? JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and then custom program just before
they are shipped to customer. No more labels on chips and no more wasted
inventory.
Expensive sockets How do I eliminate the need for expensive and unreliable
sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program
first time and subsequent times with JTAG. No need to handle devices and bend the
fragile leads.
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In-Application re-Programming (IAP)
Two independent flash memory arrays are included so the MCU can execute code
from one memory while erasing and programming the other. Robust product firmware
updates in the field are possible over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture. Designers are relieved of these
problems:
Simultaneous read and write to flash memory How can the MCU program the
same memory from which it is executing code? It cannot. The PSD allows the MCU
to operate the two flash memories concurrently, reading code from one while erasing
and programming the other during IAP.
Complex memory mapping How can I map these two memories efficiently?
A Programmable Decode PLD is embedded in the PSD. The concurrent PSD
memories can be mapped anywhere in MCU address space, segment by segment
with extremely high address resolution. As an option, the secondary flash memory
can be swapped out of the system memory map when IAP is complete. A built-in
page register breaks the MCU address limit.
Separate program and data space How can I write to flash memory while it
resides in "program" space during field firmware updates, my 80C51 won't allow it
The flash PSD provides means to "reclassify" flash memory as "data" space during
IAP, then back to "program" space when complete.
PSDsoft ST's software development tool guides you through the design
process step-by-step making it possible to complete an embedded MCU design
capable of ISP/IAP in just hours. Select your MCU and PSDsoft will take you through
the remainder of the design with point and click entry, covering...PSD selection, pin
definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C
code generation for your MCU, and merging your MCU firmware with the PSD design.
When complete, two different device programmers are supported directly from PSDsoft
FlashLINK (JTAG) and PSDpro.
The PSD935G2 is available in an 80-pin TQFP package.
PSD935G2
PSD9XX Family
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A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80188, 80C251
Motorola 68HC11 and 68HC16
Philips 8031 and 80C51XA
Zilog Z80, Z8 and Z180
Infineon C500 family
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4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
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Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
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64 Kbit SRAM. The SRAM's contents can be protected from a power failure by
connecting an external battery.
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General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
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Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
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52 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
I/O ports may be configured as open-drain outputs.
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Standby current as low as 50 A for 5 V devices.
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Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
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Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
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Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD9XX into Power Down Mode.
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Erase/Write cycles:
Flash memory 100,000 minimum
PLD 1,000 minimum
2.0
Key Features
3
3.0 PSD9XX
Series
Part #
Flash
Flash
Main
Boot
Serial ISP
Memory
Memory
PSD9XX
I/O
PLD
Input
Output
PLD
JTAG/ISP
Kbit
Kbit
SRAM
Supply
Series
Device
Pins
Inputs Macrocells Macrocells Outputs
Port
8 Sectors
(4 Sectors)
Kbit
Voltage
PSD935G2
52
66
24
Yes
4096
256
64
5V
PSD9XX
PSD913G2
27
57
19
Yes
1024
256
16
5V
PSD934F2
27
57
19
Yes
2048
256
64
5V
Table 1. PSD9XX Product Matrix
PSD9XX Family
PSD935G2
4
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0 AD15
*
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
4 MBIT MAIN FLASH
MEMORY
8 SECTORS
VSTDBY
PA0 PA7
PROG.
PORT
PORT
F
PROG.
PORT
PORT
G
PROG.
PORT
PORT
E
PB0 PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PF0 PF7
PG0 PG7
PE0 PE7
PC0 PC7
PD0 PD3
ADDRESS/DATA/CONTROL BUS
66
66
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
64 KBIT BATTERY
BACKUP SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
GPLD OUTPUT
GPLD OUTPUT
GPLD OUTPUT
I/O PORT PLD INPUT
CSIOP
FLASH ISP PLD
(GPLD)
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
(PE6)
PAGE
REGISTER
EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
Figure 1. PSD935G2 Block Diagram
*
Additional address lines can be brought into PSD via Port A, B, C, D, or F.
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