February 1998
1/64
This is advance information from SGS-THOMS ON. Details are subject to change withoutnotice.
R
ST6373
8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY
CONTROLLED MULTISYNC/MULTISTANDARD MONITORS
s
4.5V to 6V Operating Supply Voltage Range
s
Low Current Consumption
s
0 to +70
C Operating Temperature Range
s
8 MHz clock Oscillator
s
16K bytes ROM/OTP/EPROM
(8K and 12K ROM versions also available)
s
192 bytes RAM
s
384 bytes general purpose EEPROM
s
128 bytes dedicated EEPROM for DDC SPI
s
22 fully programmable I/O pins, offering direct
LED drive capability, as well as interrupt
generation for keyboard inputs
s
Digital WATCHDOG timer
s
Three Timers, each comprising an 8-bit counter
and a 7- bit Prescaler
s
SYNC Processor:
12-bits HSYNC Event Counter
12-bits VSYNC Period Counter
HSYNC and VSYNC Polarity Detection
HSYNC and VSYNC Outputs
HFLYBACK and VFLYBACK Inputs
CLAMP and BLANK Outputs
s
14-bit (PWM + BRM) D/A Converter
s
Nine 7-bit PWM D/A Converter Outputs
s
8-bit A/D Converter with 8 multiplexed inputs
s
DDC SPI with interrupt and 4 operating modes
s
A further SPI with interrupt and 2 operating
modes
s
Remote Control Signal Input (Non Maskable
Interrupt)
s
VSYNC Interrupt Input
s
Five Interrupt Vectors
s
XOR Register (Instruction Set expansion)
s
MIRROR Register (Instruction Set expansion)
PSDIP42
CSDIP42
(Refer to end of Document for Ordering Information)
1
Table of Contents
64
2/64
ST6373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.1 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.3.4 Data RAM/EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.5 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.2 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.3 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.4 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 21
3.4 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.4.1 Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.2 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.3 Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.4 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.5 ST6373 Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1.1 Details of I/O Ports A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.2 Details of I/O Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.3 I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.2 Timer Status Control Registers (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.3 Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table of Contents
3/64
1
4.2.4 Timer Prescaler Registers (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 SYNC PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.1 Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.2 Period Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.3 Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.4 Output Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.5 Video Blanking Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5 14-BIT PWM D/A CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5.1 Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.5.2 HDA Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6 7-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6.1 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7 SERIAL PERIPHERAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.7.1 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.8 MIRROR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.9 XOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ST6373
4/64
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
ST6373 Microcontrollers are members of the 8-bit
HCMOS ST637x family, a series of devices spe-
cially intended for Digitally Controlled Multi Fre-
quency Monitor applications. All ST637x devices
are based on a building block approach: a com-
mon core is surrounded by a combination of on-
chip peripherals (macrocells) available from a
standard library.
ST6373 devices are available in functionally iden-
tical
ROM,
OTP
(ST63T73)
and
EPROM
(ST63E73) versions, all with the same pinout.
ROM devices are available with 8, 12 or 16K Pro-
gram memory, whereas OTP and EPROM ver-
sions are both available in 16K versions only. For
details relating to sales types, refer to Section 7.2.
Since ROM, OTP and EPROM versions are
functionally identical, the present Datasheet
will refer to the generic ST6373 device, except
where specific versions differ in detail.
The ST6373 devices feature:
Nine PWM outputs, which can be used as Digital
to Analog converter outputs (with external RC fil-
ters). These are suitable for tuning and other
functions.
A PWM output with Bit Rate Multiplier, to which
the above comments apply.
An Event Counter especially designed to calcu-
late the HSYNC (or HDRIV) Frequency, using
one of the on-chip timers.
A Period Counter especially designed to calcu-
late the VSYNC Period.
A Polarity Detector for HSYNC (or HDRIV) and
VSYNC.
HSYNC and VSYNC outputs with controlled po-
larity.
Video Blanking and Clamping Outputs.
Two I/O ports A & B usable for a keyboard wake-
up feature since an interrupt input ored on each
of their pins.
An Analog to Digital converter connected to port
B which can be used to decode an analog key-
board or for AFC.
A VSYNC input pin connected to an interrupt
vector and to the DDC SPI for DDC1 protocol.
An NMI input which can be used, for example, as
a Remote Control input for a TV application.
A hardware DDC SPI able to manage DDC1
(VSYNC as clock), DDC2B and DDC2AB (I
2
C
BUS
Multimaster
and
Slave).
A
128-byte
dedicated EEPROM memory is available for
DDC1 and DDC2B.
Hardware I
2
C SPI for internal monitor bus and to
manage, for example, an OSD.
A Mirror Register and a XOR Register are includ-
ed to complement the basic ST6 instruction set.
Table 1. ST6373 Device Summary
Note: See Ordering Information in Table 23 at the end of the Datasheet.
DEVICE
CONFIGURATION
Program
Memory
(Bytes)
RAM
(Bytes)
EEPROM
(Bytes)
A/D
Inputs
14-bit
D/ (PWM)
Output
7-bit
D/A (PWM)
Output
EMULATING
DEVICES
ST6373
8K ROM
12K ROM
16K ROM
192
512
8
1
9
ST63E73,ST63T73
ST63T73
16K OTP
192
512
8
1
9
-
ST63E73
16K EPROM
192
512
8
1
9
-
ST6373
5/64
Figure 1. ST6373 Block Diagram
TEST
NMI
INTERRUPT
16 KBytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
192 Bytes
PORT A
PORT B
PORT C
8 BIT CORE
TEST/V
PP
(
**
)
TIMER 1
PA0 -> PA7*
V
DD
V
SS
OSCin OSCout
RESET
VSYNC
PWRIN
USER PROGRAM
MEMORY
TIMER 2
DIGITAL
WATCHD OG/TIMER
Inputs
DATA EEPROM
384 Bytes
PB0 -> PB7*
PC0 -> PC7*
DDC SPI (1)
I C SPI
EEPROM
128 Bytes (1)
TIMER 3
SCLD, SDAD
VSYNC, EXTCLK
SCLI, SDAI
HDA, DA0 -> DA8
AD0 -> AD7
D/A Outputs
A/D Inputs
SYNC
PROCESSOR
HSYNC O, VSYNCO
HSYNC I, VSYNCI
HDRIV
HFLY, VFLY
CLMPO, BLKO
(*)Refer to Pin Description for Additional Information
(
**
) V
PP
input for OTP/EPROM device programming
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