Электронный компонент: ST72260G1

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Rev. 1.7

August 2003

1/171

ST72260G, ST72262G,

ST72264G

8-BIT MCU WITH FLASH OR ROM MEMORY,

ADC, TWO 16-BIT TIMERS, I

2

C, SPI, SCI INTERFACES

s

Memories

� 4 K or 8 Kbytes Program memory: ROM or

Single voltage extended Flash (XFlash) with

read-out protection write protection and In-

Circuit Programming and In-Application Pro-

gramming (ICP and IAP). 10K write/erase cy-

cles guaranteed, data retention: 20 years at

55�C.

� 256 bytes RAM

s

Clock, Reset and Supply Management

� Enhanced reset system
� Enhanced low voltage supply supervisor

(LVD) with 3 programmable levels and auxil-

iary voltage detector (AVD) with interrupt ca-

pability for implementing safe power-down

procedures

� Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator, clock security

system and bypass for external clock

� PLL for 2x frequency multiplication
� Clock-out capability
� 4 Power Saving Modes: Halt, Active Halt,Wait

and Slow

s

Interrupt Management

� Nested interrupt controller
� 10 interrupt vectors plus TRAP and RESET
� 22 external interrupt lines (on 2 vectors)

s

22 I/O Ports

� 22 multifunctional bidirectional I/O lines
� 20 alternate function lines
� 8 high sink outputs

s

4 Timers

� Main Clock Controller with Real time base and

Clock-out capabilities

� Configurable watchdog timer

� Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and Pulse generator modes

s

3 Communications Interfaces

� SPI synchronous serial interface
� I

2

C multimaster interface

� SCI asynchronous serial interface (LIN com-

patible)

s

1 Analog peripheral

� 10-bit ADC with 6 input channels

s

Instruction Set

� 8-bit data manipulation
� 63 basic instructions
� 17 main addressing modes
� 8 x 8 unsigned multiply instruction

s

Development Tools

� Full hardware/software development package

Device Summary

SDIP32

SO28

LFBGA 6x6mm

Features

ST72260G1

ST72262G1

ST72262G2

ST72264G1

ST72264G2

Program memory - bytes

4K

4K

8K

4K

8K

RAM (stack) - bytes

256 (128)

Peripherals

Watchdog timer,

RTC,

Two16-bit timers,

SPI

Watchdog timer, RTC

Two 16-bit timers,

SPI, ADC

Watchdog timer, RTC

Two 16-bit timers,

SPI, SCI, I

2

C, ADC

Operating Supply

2.4 V to 5.5 V

CPU Frequency

Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 Mhz

Operating Temperature

-40� C to +85� C

0� C to +70� C

Packages

SO28 / SDIP32

LFBGA

1

Table of Contents

171

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ST72260G, ST72262G,
ST72264G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

4.3

PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4

ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5

MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6

REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3

CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1

PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2

MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3

RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4

SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2

MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3

INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4

CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5

INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.2

SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.3

WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.4

ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.5

HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3

I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.4

UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.5

LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.7

DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2

Table of Contents

3/171

9.8

I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53

11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149

13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 157

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

3

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17 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

18 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19.2 I/O PORT B AND C CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

19.3 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.4 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.5 MINIMUM OPERATING VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.6 CSS FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 67

19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD . . . . . . . . . . . . . . . . . . . . 167

19.8 EXTERNAL CLOCK WITH PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

19.9 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . 168

19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 168

19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 168

19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 168

19.13 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

19.14 FUNCTIONAL EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

20 DEVICE MARKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

21 ERRATA SHEET REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet
Please note that an errata sheet can be found at the end of this document on

page 166

.

ST72260G, ST72262G, ST72264G

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1 INTRODUCTION

The ST72260G, ST72262G and ST72264G devic-
es are members of the ST7 microcontroller family.
They can be grouped as follows :

� ST72264G devices are designed for mid-range

applications with ADC, I

2

C and SCI interface ca-

pabilities.

� ST72262G devices target the same range of ap-

plications but without I

2

C interface or SCI.

� ST72260G devices are for applications that do

not need ADC, I

2

C peripherals or SCI.

All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.

The ST72F260G, ST72F262G, and ST72F264G
versions feature single-voltage FLASH memory

with byte-by-byte In-Circuit Programming (ICP)
capabilities.

Under software control, all devices can be placed
in WAIT, SLOW, Active-HALT or HALT mode, re-
ducing power consumption when the application is
in idle or stand-by state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.

For easy reference, all parametric data is located
in

Section 13 on page 122

.

Figure 1. General Block Diagram

8-BIT CORE

ALU

A

DDRE

S

S

A

ND DA

T

A

B

U

S

OSC1

OSC2

RESET

PORT B

16-BIT TIMER A

PORT A

SPI

PORT C

10-BIT ADC*

PB7:0

(8 bits)

PC5:0

(6 bits)

MULTI OSC

Internal
CLOCK

CONTROL

RAM

(256 Bytes)

PA7:0

(8 bits)

V

SS

V

DD

POWER

SUPPLY

16-BIT TIMER B

PROGRAM

(4 or 8K Bytes)

LVD

+

CLOCK FILTER

SCI*

MEMORY

ICD

WATCHDOG

I

2

C*

*Not available on some devices, see device summary on page 1.

MCC/RTC

Document Outline

• 1 INTRODUCTION
• 2 PIN DESCRIPTION
• 3 REGISTER & MEMORY MAP
• 4 FLASH PROGRAM MEMORY
  • 4.1 Introduction
  • 4.2 Main Features
  • 4.3 PROGRAMMING MODES
    • 4.3.1 In-Circuit Programming (ICP)
    • 4.3.2 In Application Programming (IAP)
  • 4.4 ICC interface
  • 4.5 Memory Protection
    • 4.5.1 Read out Protection
    • 4.5.2 Flash Write/Erase Protection
  • 4.6 Register Description
• 5 CENTRAL PROCESSING UNIT
  • 5.1 INTRODUCTION
  • 5.2 MAIN FEATURES
  • 5.3 CPU REGISTERS
• 6 SUPPLY, RESET AND CLOCK MANAGEMENT
  • 6.1 PHASE LOCKED LOOP
  • 6.2 MULTI-OSCILLATOR (MO)
  • 6.3 RESET SEQUENCE MANAGER (RSM)
    • 6.3.1 Introduction
    • 6.3.2 Asynchronous External RESET pin
    • 6.3.3 External Power-On RESET
    • 6.3.4 Internal Low Voltage Detector (LVD) RESET
    • 6.3.5 Internal Watchdog RESET
  • 6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
    • 6.4.1 Low Voltage Detector (LVD)
    • 6.4.2 Auxiliary Voltage Detector (AVD)
      • 6.4.2.1 Monitoring the VDD Main Supply
    • 6.4.3 Clock Security System (CSS)
      • 6.4.3.1 Clock Filter Control
      • 6.4.3.2 Clock detection Control
    • 6.4.4 Low Power Modes
      • 6.4.4.1 Interrupts
    • 6.4.5 Register Description
• 7 INTERRUPTS
  • 7.1 INTRODUCTION
  • 7.2 Masking and Processing Flow
  • 7.3 Interrupts and Low Power Modes
  • 7.4 Concurrent & Nested Management
  • 7.5 Interrupt Register Description
• 8 POWER SAVING MODES
  • 8.1 INTRODUCTION
  • 8.2 SLOW MODE
  • 8.3 WAIT MODE
  • 8.4 ACTIVE-HALT AND HALT MODES
    • 8.4.1 ACTIVE-HALT MODE
  • 8.5 HALT MODE
    • 8.5.0.1 Halt Mode Recommendations
• 9 I/O PORTS
  • 9.1 INTRODUCTION
  • 9.2 FUNCTIONAL DESCRIPTION
    • 9.2.1 Input Modes
    • 9.2.2 Output Modes
    • 9.2.3 Alternate Functions
  • 9.3 I/O PORT IMPLEMENTATION
  • 9.4 UNUSED I/O PINS
  • 9.5 LOW POWER MODES
  • 9.6 INTERRUPTS
  • 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
  • 9.8 I/O PORT REGISTER DESCRIPTION
• 10 MISCELLANEOUS REGISTERS
  • 10.1 I/O PORT INTERRUPT SENSITIVITY
  • 10.2 I/O PORT ALTERNATE FUNCTIONS
  • 10.3 MISCELLANEOUS REGISTER DESCRIPTION
• 11 ON-CHIP PERIPHERALS
  • 11.1 WATCHDOG TIMER (WDG)
    • 11.1.1 Introduction
    • 11.1.2 Main Features
    • 11.1.3 Functional Description
    • 11.1.4 How to Program the Watchdog Timeout
    • 11.1.5 Low Power Modes
    • 11.1.6 Hardware Watchdog Option
    • 11.1.7 Using Halt Mode with the WDG (WDGHALT option)
    • 11.1.8 Interrupts
    • 11.1.9 Register Description
  • 11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC)
    • 11.2.1 Real Time Clock Timer (RTC)
    • 11.2.2 Low Power Modes
    • 11.2.3 Interrupts
    • 11.2.4 Register Description
  • 11.3 16-BIT TIMER
    • 11.3.1 Introduction
    • 11.3.2 Main Features
    • 11.3.3 Functional Description
      • 11.3.3.1 Counter
      • 11.3.3.2 External Clock
      • 11.3.3.3 Input Capture
      • 11.3.3.4 Output Compare
      • 11.3.3.5 One Pulse Mode
      • 11.3.3.6 Pulse Width Modulation Mode
    • 11.3.4 Low Power Modes
    • 11.3.5 Interrupts
    • 11.3.6 Summary of Timer modes
    • 11.3.7 Register Description
  • 11.4 SERIAL PERIPHERAL INTERFACE (SPI)
    • 11.4.1 Introduction
    • 11.4.2 Main Features
    • 11.4.3 General Description
      • 11.4.3.1 Functional Description
      • 11.4.3.2 Slave Select Management
      • 11.4.3.3 Master Mode Operation
      • 11.4.3.4 Master Mode Transmit Sequence
      • 11.4.3.5 Slave Mode Operation
      • 11.4.3.6 Slave Mode Transmit Sequence
    • 11.4.4 Clock Phase and Clock Polarity
    • 11.4.5 Error Flags
      • 11.4.5.1 Master Mode Fault (MODF)
      • 11.4.5.2 Overrun Condition (OVR)
      • 11.4.5.3 Write Collision Error (WCOL)
      • 11.4.5.4 Single Master and Multimaster Configurations
    • 11.4.6 Low Power Modes
      • 11.4.6.1 Using the SPI to wake-up the Device from Halt mode
    • 11.4.7 Interrupts
    • 11.4.8 Register Description
  • 11.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
    • 11.5.1 Introduction
    • 11.5.2 Main Features
    • 11.5.3 General Description
    • 11.5.4 Functional Description
      • 11.5.4.1 Serial Data Format
      • 11.5.4.2 Transmitter
      • 11.5.4.3 Receiver
      • 11.5.4.4 Conventional Baud Rate Generation
      • 11.5.4.5 Extended Baud Rate Generation
      • 11.5.4.6 Receiver Muting and Wake-up Feature
      • 11.5.4.7 Parity Control
    • 11.5.5 Low Power Modes
    • 11.5.6 Interrupts
    • 11.5.7 Register Description
  • 11.6 I2C BUS INTERFACE (I2C)
    • 11.6.1 Introduction
    • 11.6.2 Main Features
    • 11.6.3 General Description
    • 11.6.4 Functional Description
      • 11.6.4.1 Slave Mode
      • 11.6.4.2 Master Mode
    • 11.6.5 Low Power Modes
    • 11.6.6 Interrupts
    • 11.6.7 Register Description
  • 11.7 10-BIT A/D CONVERTER (ADC)
    • 11.7.1 Introduction
    • 11.7.2 Main Features
    • 11.7.3 Functional Description
      • 11.7.3.1 Analog Power Supply
      • 11.7.3.2 Digital A/D Conversion Result
      • 11.7.3.3 A/D Conversion
    • 11.7.4 Low Power Modes
    • 11.7.5 Interrupts
    • 11.7.6 Register Description
• 12 INSTRUCTION SET
  • 12.1 CPU ADDRESSING MODES
    • 12.1.1 Inherent
    • 12.1.2 Immediate
    • 12.1.3 Direct
    • 12.1.4 Indexed (No Offset, Short, Long)
    • 12.1.5 Indirect (Short, Long)
    • 12.1.6 Indirect Indexed (Short, Long)
    • 12.1.7 Relative mode (Direct, Indirect)
  • 12.2 INSTRUCTION GROUPS
• 13 ELECTRICAL CHARACTERISTICS
  • 13.1 PARAMETER CONDITIONS
    • 13.1.1 Minimum and Maximum values
    • 13.1.2 Typical values
    • 13.1.3 Typical curves
    • 13.1.4 Loading capacitor
    • 13.1.5 Pin input voltage
  • 13.2 ABSOLUTE MAXIMUM RATINGS
    • 13.2.1 Voltage Characteristics
    • 13.2.2 Current Characteristics
    • 13.2.3 Thermal Characteristics
  • 13.3 OPERATING CONDITIONS
    • 13.3.1 General Operating Conditions
    • 13.3.2 Low Voltage Detector (LVD) Thresholds
    • 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
  • 13.4 SUPPLY CURRENT CHARACTERISTICS
    • 13.4.1 RUN, SLOW, WAIT and SLOW WAIT Modes
    • 13.4.2 HALT and ACTIVE-HALT Modes
    • 13.4.3 Supply and Clock Managers
    • 13.4.4 On-chip peripherals
  • 13.5 CLOCK AND TIMING CHARACTERISTICS
    • 13.5.1 General Timings
    • 13.5.2 External Clock Source
    • 13.5.3 Crystal and Ceramic Resonator Oscillators
    • 13.5.4 RC Oscillators
    • 13.5.5 Clock Security System (CSS)
    • 13.5.6 PLL Characteristics
  • 13.6 MEMORY CHARACTERISTICS
    • 13.6.1 RAM and Hardware Registers
    • 13.6.2 XFlash Program Memory
  • 13.7 EMC CHARACTERISTICS
    • 13.7.1 Functional EMS
    • 13.7.2 Electro Magnetic Interference (EMI)
    • 13.7.3 Absolute Electrical Sensitivity
      • 13.7.3.1 Electro-Static Discharge (ESD)
      • 13.7.3.2 Static and Dynamic Latch-Up
      • 13.7.3.3 Designing hardened software to avoid noise problems
    • 13.7.4 ESD Pin Protection Strategy
  • 13.8 I/O PORT PIN CHARACTERISTICS
    • 13.8.1 General Characteristics
    • 13.8.2 Output Driving Current
  • 13.9 CONTROL PIN CHARACTERISTICS
    • 13.9.1 Asynchronous RESET Pin
  • 13.10 TIMER PERIPHERAL CHARACTERISTICS
    • 13.10.1 16-Bit Timer
  • 13.11 COMMUNICATION INTERFACE CHARACTERISTICS
    • 13.11.1 SPI - Serial Peripheral Interface
    • 13.11.2 I2C - Inter IC Control Interface
  • 13.12 10-BIT ADC CHARACTERISTICS
    • 13.12.0.1 General PCB Design Guidelines
• 14 PACKAGE CHARACTERISTICS
  • 14.1 PACKAGE MECHANICAL DATA
  • 14.2 THERMAL CHARACTERISTICS
  • 14.3 SOLDERING AND GLUEABILITY INFORMATION
• 15 DEVICE CONFIGURATION AND ORDERING INFORMATION
  • 15.1 OPTION BYTES
  • 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
  • 15.3 DEVELOPMENT TOOLS
    • 15.3.1 Socket and Emulator Adapter Information
    • 15.3.2 PACKAGE/SOCKET FOOTPRINT PROPOSAL
  • 15.4 ST7 APPLICATION NOTES
• 16 SUMMARY OF CHANGES
• ERRATA SHEET
  • 17 SILICON IDENTIFICATION
  • 18 REFERENCE SPECIFICATION
  • 19 SILICON LIMITATIONS
    • 19.1 EXECUTION OF BTJX INSTRUCTION
    • 19.2 I/O PORT B AND C CONFIGURATION
    • 19.3 16-BIT TIMER PWM MODE
    • 19.4 SPI MULTIMASTER MODE
    • 19.5 MINIMUM OPERATING VOLTAGE
    • 19.6 CSS FUNCTION
    • 19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD
    • 19.8 EXTERNAL CLOCK WITH PLL
    • 19.9 HALT MODE POWER CONSUMPTION WITH ADC ON
    • 19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT
    • 19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION
    • 19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY
    • 19.13 ADC CONVERSION SPURIOUS RESULTS
    • 19.14 FUNCTIONAL EMS
  • 20 DEVICE MARKING
  • 21 ERRATA SHEET REVISION HISTORY
• ST72260G, ST72262G, ST72264G