Document Outline

• 1 INTRODUCTION 7
• 2 PIN DESCRIPTION 8
• 3 REGISTER & MEMORY MAP 13
• 4 FLASH PROGRAM MEMORY 17
  • 4.1 Introduction 17
  • 4.2 Main Features 17
  • 4.3 Structure 17
  • 4.3.1 Read-out Protection 17
    • 4.4 ICC Interface 18
    • 4.5 ICP (In-Circuit Programming) 19
    • 4.6 IAP (In-Application Programming) 19
    • 4.7 Related Documentation 19
  • 4.7.1 Register Description 19
• 5 CENTRAL PROCESSING UNIT 20
  • 5.1 INTRODUCTION 20
  • 5.2 MAIN FEATURES 20
  • 5.3 CPU REGISTERS 20
• 6 SUPPLY, RESET AND CLOCK MANAGEMENT 23
  • 6.1 PHASE LOCKED LOOP 23
  • 6.2 MULTI-OSCILLATOR (MO) 24
  • 6.3 RESET SEQUENCE MANAGER (RSM) 25
  • 6.3.1 Introduction 25
  • 6.3.2 Asynchronous External RESET pin 25
  • 6.3.3 External Power-On RESET 26
  • 6.3.4 Internal Low Voltage Detector (LVD) RESET 26
  • 6.3.5 Internal Watchdog RESET 26
    • 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) 27
  • 6.4.1 Low Voltage Detector (LVD) 27
  • 6.4.2 Auxiliary Voltage Detector (AVD) 28
  • 6.4.3 Clock Security System (CSS) 30
  • 6.4.4 Low Power Modes 30
  • 6.4.5 Register Description 31
• 7 INTERRUPTS 32
  • 7.1 INTRODUCTION 32
  • 7.2 Masking and Processing Flow 32
  • 7.3 Interrupts and Low Power Modes 34
  • 7.4 Concurrent & Nested Management 34
  • 7.5 Interrupt Register Description 35
  • 7.6 EXTERNAL INTERRUPTS 37
  • 7.6.1 I/O Port Interrupt Sensitivity 37
    • 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) 39
• 8 POWER SAVING MODES 41
  • 8.1 INTRODUCTION 41
  • 8.2 SLOW MODE 41
  • 8.3 WAIT MODE 42
  • 8.4 ACTIVE-HALT AND HALT MODES 43
  • 8.4.1 ACTIVE-HALT MODE 43
  • 8.4.2 HALT MODE 44
• 9 I/O PORTS 46
  • 9.1 INTRODUCTION 46
  • 9.2 FUNCTIONAL DESCRIPTION 46
  • 9.2.1 Input Modes 46
  • 9.2.2 Output Modes 46
  • 9.2.3 Alternate Functions 46
    • 9.3 I/O PORT IMPLEMENTATION 49
    • 9.4 LOW POWER MODES 49
    • 9.5 INTERRUPTS 49
  • 9.5.1 I/O Port Implementation 50
• 10 ON-CHIP PERIPHERALS 52
  • 10.1 WATCHDOG TIMER (WDG) 52
  • 10.1.1 Introduction 52
  • 10.1.2 Main Features 52
  • 10.1.3 Functional Description 52
  • 10.1.4 How to Program the Watchdog Timeout 53
  • 10.1.5 Low Power Modes 55
  • 10.1.6 Hardware Watchdog Option 55
  • 10.1.7 Using Halt Mode with the WDG (WDGHALT option) 55
  • 10.1.8 Interrupts 55
  • 10.1.9 Register Description 55
    • 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) 57
  • 10.2.1 Programmable CPU Clock Prescaler 57
  • 10.2.2 Clock-out Capability 57
  • 10.2.3 Real Time Clock Timer (RTC) 57
  • 10.2.4 Beeper 57
  • 10.2.5 Low Power Modes 58
  • 10.2.6 Interrupts 58
  • 10.2.7 Register Description 58
    • 10.3 PWM AUTO-RELOAD TIMER (ART) 60
  • 10.3.1 Introduction 60
  • 10.3.2 Functional Description 61
  • 10.3.3 Register Description 65
    • 10.4 16-BIT TIMER 69
  • 10.4.1 Introduction 69
  • 10.4.2 Main Features 69
  • 10.4.3 Functional Description 69
  • 10.4.4 Low Power Modes 81
  • 10.4.5 Interrupts 81
  • 10.4.6 Summary of Timer modes 81
  • 10.4.7 Register Description 82
    • 10.5 SERIAL PERIPHERAL INTERFACE (SPI) 88
  • 10.5.1 Introduction 88
  • 10.5.2 Main Features 88
  • 10.5.3 General Description 88
  • 10.5.4 Clock Phase and Clock Polarity 92
  • 10.5.5 Error Flags 93
  • 10.5.6 Low Power Modes 95
  • 10.5.7 Interrupts 95
  • 10.5.8 Register Description 96
    • 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 99
  • 10.6.1 Introduction 99
  • 10.6.2 Main Features 99
  • 10.6.3 General Description 99
  • 10.6.4 Functional Description 101
  • 10.6.5 Low Power Modes 107
  • 10.6.6 Interrupts 107
  • 10.6.7 Register Description 108
    • 10.7 I2C BUS INTERFACE (I2C) 114
  • 10.7.1 Introduction 114
  • 10.7.2 Main Features 114
  • 10.7.3 General Description 114
  • 10.7.4 Functional Description 116
  • 10.7.5 Low Power Modes 120
  • 10.7.6 Interrupts 120
  • 10.7.7 Register Description 121
    • 10.8 10-BIT A/D CONVERTER (ADC) 127
  • 10.8.1 Introduction 127
  • 10.8.2 Main Features 127
  • 10.8.3 Functional Description 128
  • 10.8.4 Low Power Modes 128
  • 10.8.5 Interrupts 128
  • 10.8.6 Register Description 129
• 11 INSTRUCTION SET 131
  • 11.1 CPU ADDRESSING MODES 131
  • 11.1.1 Inherent 132
  • 11.1.2 Immediate 132
  • 11.1.3 Direct 132
  • 11.1.4 Indexed (No Offset, Short, Long) 132
  • 11.1.5 Indirect (Short, Long) 132
  • 11.1.6 Indirect Indexed (Short, Long) 133
  • 11.1.7 Relative mode (Direct, Indirect) 133
    • 11.2 INSTRUCTION GROUPS 134
• 12 ELECTRICAL CHARACTERISTICS 137
  • 12.1 PARAMETER CONDITIONS 137
  • 12.1.1 Minimum and Maximum values 137
  • 12.1.2 Typical values 137
  • 12.1.3 Typical curves 137
  • 12.1.4 Loading capacitor 137
  • 12.1.5 Pin input voltage 137
    • 12.2 ABSOLUTE MAXIMUM RATINGS 138
  • 12.2.1 Voltage Characteristics 138
  • 12.2.2 Current Characteristics 138
  • 12.2.3 Thermal Characteristics 139
    • 12.3 OPERATING CONDITIONS 139
  • 12.3.1 Operating Conditions 139
    • 12.4 LVD/AVD CHARACTERISTICS 140
  • 12.4.1 Low Voltage Detector (LVD) thresholds 140
  • 12.4.2 Auxiliary Voltage Detector (AVD) Thresholds 140
  • 12.4.3 External Voltage Detector (EVD) Thresholds 140
    • 12.5 SUPPLY CURRENT CHARACTERISTICS 141
  • 12.5.1 CURRENTCONSUMPTION 141
  • 12.5.2 Supply and Clock Managers 143
  • 12.5.3 On-Chip Peripherals 144
    • 12.6 CLOCK AND TIMING CHARACTERISTICS 145
  • 12.6.1 General Timings 145
  • 12.6.2 External Clock Source 145
  • 12.6.3 Crystal and Ceramic Resonator Oscillators 146
  • 12.6.4 RC Oscillators 148
  • 12.6.5 Clock Security System (CSS) 149
  • 12.6.6 PLL Characteristics 149
    • 12.7 MEMORY CHARACTERISTICS 150
  • 12.7.1 RAM and Hardware Registers 150
  • 12.7.2 FLASH Memory 150
    • 12.8 EMC CHARACTERISTICS 151
  • 12.8.1 Functional EMS 151
  • 12.8.2 Electro Magnetic Interference (EMI) 151
  • 12.8.3 Absolute Electrical Sensitivity 152
  • 12.8.4 ESD Pin Protection Strategy 154
    • 12.9 I/O PORT PIN CHARACTERISTICS 156
  • 12.9.1 General Characteristics 156
  • 12.9.2 Output Driving Current 157
    • 12.10 CONTROL PIN CHARACTERISTICS 159
  • 12.10.1 Asynchronous RESET Pin 159
  • 12.10.2 ICCSEL/VPP Pin 160
    • 12.11 TIMER PERIPHERAL CHARACTERISTICS 161
  • 12.11.1 8-Bit PWM-ART Auto-Reload Timer 161
  • 12.11.2 16-Bit Timer 161
    • 12.12 COMMUNICATION INTERFACE CHARACTERISTICS 162
  • 12.12.1 SPI - Serial Peripheral Interface 162
  • 12.12.2 I2C - Inter IC Control Interface 164
    • 12.13 10-BIT ADC CHARACTERISTICS 165
  • 12.13.1 Analog Power Supply and Reference Pins 167
  • 12.13.2 General PCB Design Guidelines 167
  • 12.13.3 ADC Accuracy 168
• 13 PACKAGE CHARACTERISTICS 169
  • 13.1 PACKAGE MECHANICAL DATA 169
  • 13.2 THERMAL CHARACTERISTICS 170
  • 13.3 SOLDERING AND GLUEABILITY INFORMATION 171
• 14 ST72321B CONFIGURATION AND ORDERING INFORMATION 172
  • 14.1 FLASH OPTION BYTES 172
  • 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 174
  • 14.2.1 Version-Specific Sales Conditions 176
    • 14.3 DEVELOPMENT TOOLS 176
  • 14.3.1 Socket and Emulator Adapter Information 176
    • 14.4 ST7 APPLICATION NOTES 176
• 15 KNOWN LIMITATIONS 181
  • 15.1 External RC option 181
  • 15.2 CSS Function 181
  • 15.3 Safe Connection of OSC1/OSC2 Pins 181
  • 15.4 Unexpected Reset Fetch 181
  • 15.5 16-bit Timer PWM Mode 181
  • 15.6 Limitations in 32K ROM Devices only 181
• 16 SUMMARY OF CHANGES 182
  • ST72321B
• 64/44-PIN, 8-BIT MCU WITH 32 TO 60K FLASH/ROM,
• FIVE TIMERS, SPI, SCI, I2C INTERFACE
• 1 INTRODUCTION
  • Figure 1. Device Block Diagram
• 2 PIN DESCRIPTION
  • Figure 2. 64-Pin TQFP 14x14 and 10x10 Package Pinout
  • Figure 3. 44-pin Device Pinout
  • PIN DESCRIPTION (Cont�d)
    • Table 1. Device Pin Description
• 3 REGISTER & MEMORY MAP
  • Figure 4. Memory Map
    • Table 2. Hardware Register Map
• 4 FLASH PROGRAM MEMORY
  • 4.1 Introduction
  • 4.2 Main Features
  • 4.3 Structure
    • Table 3. Sectors available in Flash devices
    • 4.3.1 Read-out Protection
    • Figure 5. Memory Map and Sector Address
  • FLASH PROGRAM MEMORY (Cont�d)
    • 4.4 ICC Interface
      • Figure 6. Typical ICC Interface
  • FLASH PROGRAM MEMORY (Cont�d)
    • 4.5 ICP (In-Circuit Programming)
    • 4.6 IAP (In-Application Programming)
    • 4.7 Related Documentation
      • 4.7.1 Register Description
        • Table 4. Flash Control/Status Register Address and Reset Value
• 5 CENTRAL PROCESSING UNIT
  • 5.1 INTRODUCTION
  • 5.2 MAIN FEATURES
  • 5.3 CPU REGISTERS
    • Figure 7 . CPU Registers
  • CENTRAL PROCESSING UNIT (Cont�d)
  • CENTRAL PROCESSING UNIT (Cont�d)
    • Figure 8 . Stack Manipulation Example
• 6 SUPPLY, RESET AND CLOCK MANAGEMENT
  • 6.1 PHASE LOCKED LOOP
    • Figure 9. PLL Block Diagram
    • Figure 10. Clock, Reset and Supply Block Diagram
  • 6.2 MULTI-OSCILLATOR (MO)
    • Table 5. ST7 Clock Sources
  • 6.3 RESET SEQUENCE MANAGER (RSM)
    • 6.3.1 Introduction
    • Figure 11. RESET Sequence Phases
      • 6.3.2 Asynchronous External RESET pin
    • Figure 12. Reset Block Diagram
  • RESET SEQUENCE MANAGER (Cont�d)
    • 6.3.3 External Power-On RESET
    • 6.3.4 Internal Low Voltage Detector (LVD) RESET
    • 6.3.5 Internal Watchdog RESET
    • Figure 13. RESET Sequences
    • 6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
      • 6.4.1 Low Voltage Detector (LVD)
      • Figure 14. Low Voltage Detector vs Reset
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 6.4.2 Auxiliary Voltage Detector (AVD)
      • 6.4.2.1 Monitoring the VDD Main Supply
    • Figure 15. Using the AVD to Monitor VDD (AVDS bit=0)
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 6.4.2.2 Monitoring a Voltage on the EVD pin
    • Figure 16. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 6.4.3 Clock Security System (CSS)
      • 6.4.3.1 Clock Filter Control
      • 6.4.3.2 Clock detection Control
    • 6.4.4 Low Power Modes
      • 6.4.4.1 Interrupts
    • Figure 17. Clock Filter Function
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 6.4.5 Register Description
• 7 INTERRUPTS
  • 7.1 INTRODUCTION
  • 7.2 Masking and Processing Flow
    • Table 6. Interrupt Software Priority Levels
    • Figure 18 . Interrupt Processing Flowchart
  • INTERRUPTS (Cont�d)
    • Figure 19 . Priority Decision Process
  • INTERRUPTS (Cont�d)
    • 7.3 Interrupts and Low Power Modes
    • 7.4 Concurrent & Nested Management
      • Figure 20 . Concurrent Interrupt Management
      • Figure 21 . Nested Interrupt Management
  • INTERRUPTS (Cont�d)
    • 7.5 Interrupt Register Description
  • INTERRUPTS (Cont�d)
    • Table 7. Dedicated Interrupt Instruction Set
  • INTERRUPTS (Cont�d)
    • Table 8. Interrupt Mapping
    • 7.6 EXTERNAL INTERRUPTS
      • 7.6.1 I/O Port Interrupt Sensitivity
      • Figure 22. External Interrupt Control bits
  • INTERRUPTS (Cont�d)
    • 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
  • INTERRUPTS (Cont�d)
    • Table 9. Nested Interrupts Register Map and Reset Values
• 8 POWER SAVING MODES
  • 8.1 INTRODUCTION
    • Figure 23. Power Saving Mode Transitions
  • 8.2 SLOW MODE
    • Figure 24. SLOW Mode Clock Transitions
  • POWER SAVING MODES (Cont�d)
    • 8.3 WAIT MODE
      • Figure 25. WAIT Mode Flow-chart
  • POWER SAVING MODES (Cont�d)
    • 8.4 ACTIVE-HALT AND HALT MODES
      • 8.4.1 ACTIVE-HALT MODE
      • Figure 26. ACTIVE-HALT Timing Overview
      • Figure 27. ACTIVE-HALT Mode Flow-chart
  • POWER SAVING MODES (Cont�d)
    • 8.4.2 HALT MODE
    • Figure 28. HALT Timing Overview
    • Figure 29. HALT Mode Flow-chart
  • POWER SAVING MODES (Cont�d)
    • 8.4.2.1 Halt Mode Recommendations
• 9 I/O PORTS
  • 9.1 INTRODUCTION
  • 9.2 FUNCTIONAL DESCRIPTION
    • 9.2.1 Input Modes
    • 9.2.2 Output Modes
    • 9.2.3 Alternate Functions
  • I/O PORTS (Cont�d)
    • Figure 30. I/O Port General Block Diagram
      • Table 10. I/O Port Mode Options
  • I/O PORTS (Cont�d)
    • Table 11. I/O Port Configurations
  • I/O PORTS (Cont�d)
    • 9.3 I/O PORT IMPLEMENTATION
      • Figure 31. Interrupt I/O Port State Transitions
    • 9.4 LOW POWER MODES
    • 9.5 INTERRUPTS
  • I/O PORTS (Cont�d)
    • 9.5.1 I/O Port Implementation
      • Table 12. Port Configuration
  • I/O PORTS (Cont�d)
    • Table 13. I/O Port Register Map and Reset Values
• 10 ON-CHIP PERIPHERALS
  • 10.1 WATCHDOG TIMER (WDG)
    • 10.1.1 Introduction
    • 10.1.2 Main Features
    • 10.1.3 Functional Description
    • Figure 32 . Watchdog Block Diagram
  • WATCHDOG TIMER (Cont�d)
    • 10.1.4 How to Program the Watchdog Timeout
    • Figure 33 . Approximate Timeout Duration
  • WATCHDOG TIMER (Cont�d)
    • Figure 34 . Exact Timeout Duration (tmin and tmax)
  • WATCHDOG TIMER (Cont�d)
    • 10.1.5 Low Power Modes
    • 10.1.6 Hardware Watchdog Option
    • 10.1.7 Using Halt Mode with the WDG (WDGHALT option)
    • 10.1.8 Interrupts
    • 10.1.9 Register Description
      • Table 14. Watchdog Timer Register Map and Reset Values
    • 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
      • 10.2.1 Programmable CPU Clock Prescaler
      • 10.2.2 Clock-out Capability
      • 10.2.3 Real Time Clock Timer (RTC)
      • 10.2.4 Beeper
      • Figure 35. Main Clock Controller (MCC/RTC) Block Diagram
  • MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont�d)
    • 10.2.5 Low Power Modes
    • 10.2.6 Interrupts
    • 10.2.7 Register Description
  • MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont�d)
    • Table 15. Main Clock Controller Register Map and Reset Values
    • 10.3 PWM AUTO-RELOAD TIMER (ART)
      • 10.3.1 Introduction
      • Figure 36. PWM Auto-Reload Timer Block Diagram
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • 10.3.2 Functional Description
    • Figure 37. Output compare control
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Figure 38. PWM Auto-reload Timer Function
    • Figure 39. PWM Signal from 0% to 100% Duty Cycle
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Figure 40. External Event Detector Example (3 counts)
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Figure 41. Input Capture Timing Diagram
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • 10.3.3 Register Description
  • PWM AUTO-RELOAD TIMER (Cont�d)
  • PWM AUTO-RELOAD TIMER (Cont�d)
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Table 16. PWM Auto-Reload Timer Register Map and Reset Values
    • 10.4 16-BIT TIMER
      • 10.4.1 Introduction
      • 10.4.2 Main Features
      • 10.4.3 Functional Description
        • 10.4.3.1 Counter
  • 16-BIT TIMER (Cont�d)
    • Figure 42. Timer Block Diagram
  • 16-BIT TIMER (Cont�d)
    • 10.4.3.2 External Clock
  • 16-BIT TIMER (Cont�d)
    • Figure 43. Counter Timing Diagram, internal clock divided by 2
    • Figure 44. Counter Timing Diagram, internal clock divided by 4
    • Figure 45. Counter Timing Diagram, internal clock divided by 8
  • 16-BIT TIMER (Cont�d)
    • 10.4.3.3 Input Capture
  • 16-BIT TIMER (Cont�d)
    • Figure 46. Input Capture Block Diagram
    • Figure 47. Input Capture Timing Diagram
  • 16-BIT TIMER (Cont�d)
    • 10.4.3.4 Output Compare
  • 16-BIT TIMER (Cont�d)
    • Figure 48. Output Compare Block Diagram
  • 16-BIT TIMER (Cont�d)
    • Figure 49. Output Compare Timing Diagram, fTIMER =fCPU/2
    • Figure 50. Output Compare Timing Diagram, fTIMER =fCPU/4
  • 16-BIT TIMER (Cont�d)
    • 10.4.3.5 One Pulse Mode
  • 16-BIT TIMER (Cont�d)
    • Figure 51. One Pulse Mode Timing Example
    • Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
  • 16-BIT TIMER (Cont�d)
    • 10.4.3.6 Pulse Width Modulation Mode
  • 16-BIT TIMER (Cont�d)
    • 10.4.4 Low Power Modes
    • 10.4.5 Interrupts
    • 10.4.6 Summary of Timer modes
  • 16-BIT TIMER (Cont�d)
    • 10.4.7 Register Description
  • 16-BIT TIMER (Cont�d)
    • Table 17. Clock Control Bits
  • 16-BIT TIMER (Cont�d)
  • CONTROL/STATUS REGISTER (CSR)
  • 16-BIT TIMER (Cont�d)
  • 16-BIT TIMER (Cont�d)
  • 16-BIT TIMER (Cont�d)
    • Table 18. 16-Bit Timer Register Map and Reset Values
    • 10.5 SERIAL PERIPHERAL INTERFACE (SPI)
      • 10.5.1 Introduction
      • 10.5.2 Main Features
      • 10.5.3 General Description
      • Figure 53. Serial Peripheral Interface Block Diagram
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.3.1 Functional Description
    • Figure 54. Single Master/ Single Slave Application
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.3.2 Slave Select Management
    • Figure 55. Generic SS Timing Diagram
    • Figure 56. Hardware/Software Slave Select Management
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.3.3 Master Mode Operation
    • 10.5.3.4 Master Mode Transmit Sequence
    • 10.5.3.5 Slave Mode Operation
    • 10.5.3.6 Slave Mode Transmit Sequence
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.4 Clock Phase and Clock Polarity
    • Figure 57. Data Clock Timing Diagram
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.5 Error Flags
      • 10.5.5.1 Master Mode Fault (MODF)
      • 10.5.5.2 Overrun Condition (OVR)
      • 10.5.5.3 Write Collision Error (WCOL)
    • Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.5.4 Single Master Systems
    • Figure 59. Single Master / Multiple Slave Configuration
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.6 Low Power Modes
      • 10.5.6.1 Using the SPI to wakeup the MCU from Halt mode
    • 10.5.7 Interrupts
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 10.5.8 Register Description
      • Table 19. SPI Master mode SCK Frequency
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • Table 20. SPI Register Map and Reset Values
    • 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
      • 10.6.1 Introduction
      • 10.6.2 Main Features
      • 10.6.3 General Description
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • Figure 60. SCI Block Diagram
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.4 Functional Description
      • 10.6.4.1 Serial Data Format
    • Figure 61. Word Length Programming
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.4.2 Transmitter
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.4.3 Receiver
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.4.4 Conventional Baud Rate Generation
    • 10.6.4.5 Extended Baud Rate Generation
    • 10.6.4.6 Receiver Muting and Wake-up Feature
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.4.7 Parity Control
      • Table 21. Frame Formats
    • 10.6.4.8 SCI Clock Tolerance
    • 10.6.4.9 Clock Deviation Causes
    • Figure 63 . Bit Sampling in Reception Mode
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.5 Low Power Modes
    • 10.6.6 Interrupts
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 10.6.7 Register Description
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • Table 22. Baudrate Selection
  • SERIAL COMMUNICATION INTERFACE (Cont�d)
    • Table 23. SCI Register Map and Reset Values
    • 10.7 I2C BUS INTERFACE (I2C)
      • 10.7.1 Introduction
      • 10.7.2 Main Features
      • 10.7.3 General Description
      • Figure 64. I2C BUS Protocol
  • I2C BUS INTERFACE (Cont�d)
    • Figure 65. I2C Interface Block Diagram
  • I2C BUS INTERFACE (Cont�d)
    • 10.7.4 Functional Description
      • 10.7.4.1 Slave Mode
  • I2C BUS INTERFACE (Cont�d)
    • 10.7.4.2 Master Mode
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
    • Figure 66. Transfer Sequencing
  • I2C BUS INTERFACE (Cont�d)
    • 10.7.5 Low Power Modes
    • 10.7.6 Interrupts
    • Figure 67. Event Flags and Interrupt Generation
  • I2C BUS INTERFACE (Cont�d)
    • 10.7.7 Register Description
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
  • I�C BUS INTERFACE (Cont�d)
    • Table 24. I2C Register Map and Reset Values
    • 10.8 10-BIT A/D CONVERTER (ADC)
      • 10.8.1 Introduction
      • 10.8.2 Main Features
      • Figure 68. ADC Block Diagram
  • 10-BIT A/D CONVERTER (ADC) (Cont�d)
    • 10.8.3 Functional Description
      • 10.8.3.1 A/D Converter Configuration
      • 10.8.3.2 Starting the Conversion
      • 10.8.3.3 Changing the conversion channel
    • 10.8.4 Low Power Modes
    • 10.8.5 Interrupts
  • 10-BIT A/D CONVERTER (ADC) (Cont�d)
    • 10.8.6 Register Description
  • 10-BIT A/D CONVERTER (Cont�d)
    • Table 25. ADC Register Map and Reset Values
• 11 INSTRUCTION SET
  • 11.1 CPU ADDRESSING MODES
    • Table 26. CPU Addressing Mode Overview
  • INSTRUCTION SET OVERVIEW (Cont�d)
    • 11.1.1 Inherent
    • 11.1.2 Immediate
    • 11.1.3 Direct
    • 11.1.4 Indexed (No Offset, Short, Long)
    • 11.1.5 Indirect (Short, Long)
  • INSTRUCTION SET OVERVIEW (Cont�d)
    • 11.1.6 Indirect Indexed (Short, Long)
      • Table 27. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
    • 11.1.7 Relative mode (Direct, Indirect)
  • INSTRUCTION SET OVERVIEW (Cont�d)
    • 11.2 INSTRUCTION GROUPS
  • INSTRUCTION SET OVERVIEW (Cont�d)
  • INSTRUCTION SET OVERVIEW (Cont�d)
• 12 ELECTRICAL CHARACTERISTICS
  • 12.1 PARAMETER CONDITIONS
    • 12.1.1 Minimum and Maximum values
    • 12.1.2 Typical values
    • 12.1.3 Typical curves
    • 12.1.4 Loading capacitor
    • Figure 69. Pin loading conditions
      • 12.1.5 Pin input voltage
    • Figure 70. Pin input voltage
  • 12.2 ABSOLUTE MAXIMUM RATINGS
    • 12.2.1 Voltage Characteristics
    • 12.2.2 Current Characteristics
    • 12.2.3 Thermal Characteristics
  • 12.3 OPERATING CONDITIONS
    • 12.3.1 Operating Conditions
    • Figure 71. fCPU Max Versus VDD
  • OPERATING CONDITIONS (Cont�d)
    • 12.4 LVD/AVD CHARACTERISTICS
      • 12.4.1 Low Voltage Detector (LVD) thresholds
      • 12.4.2 Auxiliary Voltage Detector (AVD) Thresholds
      • 12.4.3 External Voltage Detector (EVD) Thresholds
    • 12.5 SUPPLY CURRENT CHARACTERISTICS
      • 12.5.1 CURRENTCONSUMPTION
  • SUPPLY CURRENT CHARACTERISTICS (Cont�d)
    • Figure 72. Typical IDD in RUN vs. fCPU
    • Figure 73. Typical IDD in WAIT vs. fCPU
    • Figure 74. Typical IDD in SLOW vs. fCPU
    • Figure 75. Typical IDD in SLOW-WAIT vs. fCPU
  • SUPPLY CURRENT CHARACTERISTICS (Cont�d)
    • 12.5.2 Supply and Clock Managers
  • SUPPLY CURRENT CHARACTERISTICS (Cont�d)
    • 12.5.3 On-Chip Peripherals
    • 12.6 CLOCK AND TIMING CHARACTERISTICS
      • 12.6.1 General Timings
      • 12.6.2 External Clock Source
      • Figure 76. Typical Application with an External Clock Source
  • CLOCK AND TIMING CHARACTERISTICS (Cont�d)
    • 12.6.3 Crystal and Ceramic Resonator Oscillators
    • Figure 77. Typical Application with a Crystal or Ceramic Resonator
  • CLOCK AND TIMING CHARACTERISTICS (Cont�d)
  • CLOCK CHARACTERISTICS (Cont�d)
    • 12.6.4 RC Oscillators
    • Figure 78. Typical fOSC(RCINT) vs TA
      • Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitor...
  • CLOCK CHARACTERISTICS (Cont�d)
    • 12.6.5 Clock Security System (CSS)
    • 12.6.6 PLL Characteristics
    • Figure 79. PLL Jitter vs. Signal frequency1
    • 12.7 MEMORY CHARACTERISTICS
      • 12.7.1 RAM and Hardware Registers
      • 12.7.2 FLASH Memory
    • 12.8 EMC CHARACTERISTICS
      • 12.8.1 Functional EMS
      • 12.8.2 Electro Magnetic Interference (EMI)
  • EMC CHARACTERISTICS (Cont�d)
    • 12.8.3 Absolute Electrical Sensitivity
      • 12.8.3.1 Electro-Static Discharge (ESD)
    • Figure 80. Typical Equivalent ESD Circuits
  • EMC CHARACTERISTICS (Cont�d)
    • 12.8.3.2 Static and Dynamic Latch-Up
    • 12.8.3.3 Designing hardened software to avoid noise problems
    • Figure 81. Simplified Diagram of the ESD Generator for DLU
  • EMC CHARACTERISTICS (Cont�d)
    • 12.8.4 ESD Pin Protection Strategy
    • Figure 82. Positive Stress on a Standard Pad vs. VSS
    • Figure 83. Negative Stress on a Standard Pad vs. VDD
  • EMC CHARACTERISTICS (Cont�d)
    • Figure 84. Positive Stress on a True Open Drain Pad vs. VSS
    • Figure 85. Negative Stress on a True Open Drain Pad vs. VDD
    • Figure 86. Multisupply Configuration
    • 12.9 I/O PORT PIN CHARACTERISTICS
      • 12.9.1 General Characteristics
      • Figure 87. Connecting Unused I/O Pins
      • Figure 88. Typical IPU vs. VDD with VIN=VSS
  • I/O PORT PIN CHARACTERISTICS (Cont�d)
    • 12.9.2 Output Driving Current
    • Figure 89. Typical VOL at VDD=5V (std. ports)
    • Figure 90. Typ. VOL at VDD=5V (high-sink ports)
    • Figure 91. Typical VOH at VDD=5V
  • I/O PORT PIN CHARACTERISTICS (Cont�d)
    • Figure 92. Typical VOL vs. VDD (std. ports)
    • Figure 93. Typical VOL vs. VDD (high-sink ports)
    • Figure 94. Typical VOH vs. VDD
    • 12.10 CONTROL PIN CHARACTERISTICS
      • 12.10.1 Asynchronous RESET Pin
      • Figure 95. Typical Application with RESET pin 6)7)8)
  • CONTROL PIN CHARACTERISTICS (Cont�d)
    • 12.10.2 ICCSEL/VPP Pin
    • Figure 96. Two typical Applications with ICCSEL/VPP Pin 2)
    • 12.11 TIMER PERIPHERAL CHARACTERISTICS
      • 12.11.1 8-Bit PWM-ART Auto-Reload Timer
      • 12.11.2 16-Bit Timer
    • 12.12 COMMUNICATION INTERFACE CHARACTERISTICS
      • 12.12.1 SPI - Serial Peripheral Interface
      • Figure 97. SPI Slave Timing Diagram with CPHA=0 3)
  • COMMUNICATION INTERFACE CHARACTERISTICS (Cont�d)
    • Figure 98. SPI Slave Timing Diagram with CPHA=11)
    • Figure 99. SPI Master Timing Diagram 1)
  • COMMUNICATION INTERFACE CHARACTERISTICS (Cont�d)
    • 12.12.2 I2C - Inter IC Control Interface
    • Figure 100. Typical Application with I2C Bus and Timing Diagram 4)
    • 12.13 10-BIT ADC CHARACTERISTICS
      • Figure 101. RAIN max. vs fADC with CAIN=0pF3)
      • Figure 102. Recommended CAIN & RAIN values.4)
  • ADC CHARACTERISTICS (Cont�d)
    • Figure 103. Typical A/D Converter Application
  • ADC CHARACTERISTICS (Cont�d)
    • 12.13.1 Analog Power Supply and Reference Pins
    • 12.13.2 General PCB Design Guidelines
    • Figure 104. Power Supply Filtering
  • 10-BIT ADC CHARACTERISTICS (Cont�d)
    • 12.13.3 ADC Accuracy
    • Figure 105. ADC Accuracy Characteristics
• 13 PACKAGE CHARACTERISTICS
  • 13.1 PACKAGE MECHANICAL DATA
    • Figure 106. 64-Pin 14 x 14 Thin Quad Flat Package
    • Figure 107. 64-Pin 10 x 10 Thin Quad Flat Package
    • Figure 108. 44-Pin Thin Quad Flat Package
  • 13.2 THERMAL CHARACTERISTICS
  • 13.3 SOLDERING AND GLUEABILITY INFORMATION
    • Figure 109. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
    • Figure 110. Recommended Reflow Soldering Oven Profile (MID JEDEC)
• 14 ST72321B CONFIGURATION AND ORDERING INFORMATION
  • 14.1 FLASH OPTION BYTES
  • ST72321B CONFIGURATION AND ORDERING INFORMATION (Cont�d)
  • ST72321B CONFIGURATION AND ORDERING INFORMATION (Cont�d)
    • 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
      • Table 28. Orderable Flash Device Types (available soon)
      • Figure 111. ROM Factory Coded Device Types
  • ST72321B DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont�d)
  • DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont�d)
    • 14.2.1 Version-Specific Sales Conditions
    • 14.3 DEVELOPMENT TOOLS
      • 14.3.1 Socket and Emulator Adapter Information
        • Table 29. STMicroelectronics Development Tools
        • Table 30. Suggested List of Socket Types
    • 14.4 ST7 APPLICATION NOTES
• 15 KNOWN LIMITATIONS
  • 15.1 External RC option
  • 15.2 CSS Function
  • 15.3 Safe Connection of OSC1/OSC2 Pins
  • 15.4 Unexpected Reset Fetch
  • 15.5 16-bit Timer PWM Mode
  • 15.6 Limitations in 32K ROM Devices only
• 16 SUMMARY OF CHANGES
  • Australia � Belgium - Brazil - Canada - China � Czech Republic - Finland - France - Germany - Hon...
  • www.st.com