Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

Rev. 1.6

October 2002

1/156

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

ST72324J/K

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,

4 TIMERS, SPI, SCI INTERFACE

PRELIMINARY DATA

Memories

8 to 32K dual voltage High Density Flash (HD-

Flash) or ROM with read-out protection capa-

bility. In-Application Programming and In-

Circuit Programming for HDFlash devices

384 to 1K bytes RAM
HDFlash endurance: 100 cycles, data reten-

tion: 20 years at 55°C

Clock, Reset And Supply Management

Enhanced low voltage supervisor (LVD) for

main supply with 3 programmable reset

thresholds and auxiliary voltage detector

(AVD) with interrupt capability

Clock sources: crystal/ceramic resonator os-

cillators, internal or external RC oscillator,

clock security system and bypass for external

clock

PLL for 2x frequency multiplication
Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

Interrupt Management

Nested interrupt controller
10 interrupt vectors plus TRAP and RESET
9/6 external interrupt lines (on 4 vectors)

Up to 32 I/O Ports

32/24 multifunctional bidirectional I/O lines
22/17 alternate function lines
12/10 high sink outputs

4 Timers

Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

Configurable watchdog timer
16-bit Timer A with: 1 input capture, 1 output

compare, external clock input, fixed freq.

PWM and pulse generator modes

16-bit Timer B with: 2 input captures, 2 output

compares, variable freq. PWM and pulse gen-

erator modes

2 Communication Interfaces

SPI synchronous serial interface
SCI asynchronous serial interface (LIN com-

patible)

1 Analog Peripheral

10-bit ADC with up to 12 input pins

Instruction Set

8-bit Data Manipulation
63 Basic Instructions
17 main Addressing Modes
8 x 8 Unsigned Multiply Instruction

Development Tools

Full hardware/software development package
In-Circuit Testing capability

Device Summary

TQFP44

10 x 10

SDIP42
600 mil

SDIP32
400 mil

TQFP32

7 x 7

Features

ST72(F)324(J/K)6

ST72(F)324(J/K)4

ST72(F)324(J/K)2

Program memory - bytes

32K

16K

RAM (stack) - bytes

1024 (256)

512 (256)

384 (256)

Operating Voltage

3.8V to 5.5V (low voltage version planned with 3.0 to 3.6V range)

Temp. Range (ROM)

up to -40°C to +125°C

Temp. Range (Flash)

up to -40°C to +125°C

-40°C to +85 °C

Packages

SDIP42 (JxB), TQFP44 10x10 (JxT),SDIP32 (KxB), TQFP32 7x7 (KxT)

Table of Contents

156

2/156

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

4.3

STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.1

Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.4

ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5

ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6

IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6.1

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

5.3

CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1

PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2

MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.3

RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3.2

Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3.3

External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.4

Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.5

Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4

SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4.1

Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4.2

Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.3

Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.4

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.5

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2

MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.3

INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.4

CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.5

INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.6

EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.6.1

I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.7

EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 37

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.2

SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.3

WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table of Contents

156

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8.4

ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.4.1

ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.4.2

HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.2

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.2.1

Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.2.2

Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.2.3

Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.3

I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.4

LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.5

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.5.1

I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 55

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.3.1 General Operating Conditions (standard voltage ROM and Flash devices) . . . . . 114
12.3.2 General Operating Conditions for low voltage ROM and Flash devices (planned) 115
12.3.3 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 116
12.3.4 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4.1 RUN and SLOW Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.4.2 WAIT and SLOW WAIT Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.4.3 RUN and SLOW Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table of Contents

156

5/156

12.4.4 WAIT and SLOW WAIT Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.4.5 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.4.6 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.4.7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 139

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

12.12.1ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

14 ST72324J/K DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . 148

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 150

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

14.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

ST72324J/K

6/156

1 INTRODUCTION

The ST72324K and ST72324J devices are mem-
bers of the ST7 microcontroller family. They can
be grouped as follows:

The 32-pin ST72324K devices are designed for

mid-range applications

The 42/44-pin ST72324J devices target the

same range of applications requiring more than
24 I/O ports.

All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM pro-
gram memory.

Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

ESS

D
A

OSC1

CONTROL

PROGRAM

(8K - 60K Bytes)

RESET

PORT F

PF7:6,4,2:0

TIMER A

BEEP

PORT A

RAM

(384 - 2048 Bytes)

PORT C

10-BIT ADC

AREF

SSA

PORT B

PB4:0

PORT E

PE1:0

(2 bits)

SCI

TIMER B

PA7:3

(5 bits on J devices)

PORT D

PD5:0

SPI

PC7:0

(8 bits)

WATCHDOG

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on J devices)
(3 bits on K devices)

(6 bits on J devices)
(2 bits on K devices)

(6 bits on J devices)
(5 bits on K devices)

ST72324J/K

7/156

2 PIN DESCRIPTION

Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts

/ A

I
N

/
PF

BEEP

/ (

)
P

(
H

A /

/ P

AP1

/ (

)
P

/
(

DD_

/ P

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

ei2

ei3

ei0

ei1

PB3

(HS) PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

RDI / PE1

PB0

PB1

PB2

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

SS_1

DD_1

PA3 (HS)

PC7 / SS / AIN15

ESET

/ IC

SEL

PA7

(

)

PA6

(

)

PA5

(

)

PA4

(

)

PE0

(HS) PB4

AIN0 / PD0

AIN12 / OCMP2_B / PC0

EXTCLK_A / (HS) PF7

ICAP1_A / (HS) PF6

AIN10 / OCMP1_A / PF4

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

AIN5 / PD5

AIN4 / PD4

AIN3 / PD3

AIN2 / PD2

AIN1 / PD1

SSA

AREF

PB3

PB2

PA4 (HS)

PA5 (HS)

PA6 (HS)

PA7 (HS)

/ ICCSEL

RESET

PE0 / TDO

PE1 / RDI

PB0

PB1

OSC1

OSC2

ei3

ei0

ei2

ei1

AIN14 / MOSI / PC5

ICCDATA / MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B/ (HS) PC2

AIN13 / OCMP1_B / PC1

PC6 / SCK / ICCCLK

PC7 / SS / AIN15

PA3 (HS)

DD_1

SS_1

eix

associated external interrupt vector

(HS) 20mA high sink capability

ST72324J/K

8/156

PIN DESCRIPTION (Cont'd)

Figure 3. 32-Pin SDIP Package Pinout

Figure 4. 32-Pin TQFP 7x7 Package Pinout

(HS) PB4

AIN0 / PD0

AIN14 / MOSI / PC5

ICCDATA/ MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B / (HS) PC2

AIN13 / OCMP1_B / PC1

AIN12 / OCMP2_B / PC0

EXTCLK_A / (HS) PF7

BEEP / (HS) PF1

MCO / AIN8 / PF0

SSA

AREF

AIN1 / PD1

ICAP1_A / (HS) PF6

OCMP1_A / AIN10 / PF4

PB3

PB0

PC6 / SCK / ICCCLK

PC7 / SS / AIN15

PA3 (HS)

PA4 (HS)

PA6 (HS)

PA7 (HS)

/ ICCSEL

OSC2

OSC1

PE0 / TDO

PE1 / RDI

RESET

ei0

ei3

ei2

ei1

eix

associated external interrupt vector

(HS) 20mA high sink capability

A /

MISO

/ PC

AIN

/ PC

/ S

/ PC

AIN

/ PC

(

/ O

MP1

/ PC

B /

(

B /

(

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

ei1

ei3

ei0

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

/ ICCSEL

PA7 (HS)

PA6 (HS)

PA4 (HS)

OSC1

OSC2

RESET

PB0

PE1

PE0

/ AI

PB4

(

)

PB3

ei2

eix

associated external interrupt vector

(HS) 20mA high sink capability

ST72324J/K

9/156

PIN DESCRIPTION (Cont'd)

For external pin connection guidelines, refer to See "ELECTRICAL CHARACTERISTICS" on page 112.

Legend / Abbreviations for

Table 1

Type:

I = input, O = output, S = supply

Input level:

A = Dedicated analog input

In/Output level: C = CMOS 0.3V

/0.7V

= CMOS 0.3V

/0.7V

with input trigger

Output level:

HS = 20mA high sink (on N-buffer only)

Port and control configuration:

Input:

float = floating, wpu = weak pull-up, int = interrupt

, ana = analog

Output:

OD = open drain

, PP = push-pull

Refer to

"I/O PORTS" on page 44

for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.

Table 1. Device Pin Description

Pin n°

Pin Name

ype

Level

Port

Main

function

(after

reset)

Alternate Function

FP44

IP42

FP32

IP32

put

tput

Input

Output

flo

1 30 1

PB4 (HS)

I/O C

ei3

Port B4

2 31 2

PD0/AIN0

I/O C

Port D0

ADC Analog Input 0

3 32 3

PD1/AIN1

I/O C

Port D1

ADC Analog Input 1

PD2/AIN2

I/O C

Port D2

ADC Analog Input 2

10 5

PD3/AIN3

I/O C

Port D3

ADC Analog Input 3

11 6

PD4/AIN4

I/O C

Port D4

ADC Analog Input 4

12 7

PD5/AIN5

I/O C

Port D5

ADC Analog Input 5

13 8

AREF

Analog Reference Voltage for ADC

14 9

SSA

Analog Ground Voltage

15 10 3

PF0/MCO/AIN8

I/O C

ei1

Port F0

Main clock
out (f

OSC

/2)

ADC Analog
Input 8

16 11 4

PF1 (HS)/BEEP

I/O C

ei1

Port F1

Beep signal output

17 12

PF2 (HS)

I/O C

ei1

Port F2

18 13 5

PF4/OCMP1_A/
AIN10

I/O C

Port F4

Timer A Out-
put Com-
pare 1

ADC Analog
Input 10

19 14 6

PF6 (HS)/ICAP1_A

I/O C

Port F6

Timer A Input Capture 1

20 15 7 10

PF7 (HS)/
EXTCLK_A

I/O C

Port F7

Timer A External Clock
Source

DD_0

Digital Main Supply Voltage

SS_0

Digital Ground Voltage

23 16 8 11

PC0/OCMP2_B/
AIN12

I/O C

Port C0

Timer B Out-
put Com-
pare 2

ADC Analog
Input 12

ST72324J/K

10/156

24 17 9 12

PC1/OCMP1_B/
AIN13

I/O C

Port C1

Timer B Out-
put Com-
pare 1

ADC Analog
Input 13

25 18 10 13 PC2 (HS)/ICAP2_B

I/O C

Port C2

Timer B Input Capture 2

26 19 11 14 PC3 (HS)/ICAP1_B

I/O C

Port C3

Timer B Input Capture 1

27 20 12 15

PC4/MISO/ICCDA-
TA

I/O C

Port C4

SPI Master
In / Slave
Out Data

ICC Data In-
put

28 21 13 16 PC5/MOSI/AIN14

I/O C

Port C5

SPI Master
Out / Slave
In Data

ADC Analog
Input 14

29 22 14 17 PC6/SCK/ICCCLK

I/O C

Port C6

SPI Serial
Clock

ICC Clock
Output

30 23 15 18 PC7/SS/AIN15

I/O C

Port C7

SPI Slave
Select (ac-
tive low)

ADC Analog
Input 15

31 24 16 19 PA3 (HS)

I/O C

ei0

Port A3

32 25

DD_1

Digital Main Supply Voltage

33 26

SS_1

Digital Ground Voltage

34 27 17 20 PA4 (HS)

I/O C

Port A4

35 28

PA5 (HS)

I/O C

Port A5

36 29 18 21 PA6 (HS)

I/O C

Port A6

37 30 19 22 PA7 (HS)

I/O C

Port A7

38 31 20 23 V

/ICCSEL

Must be tied low. In the flash pro-
gramming mode, this pin acts as the
programming voltage input V

. See

Section 12.9.2

for more details. High

voltage must not be applied to ROM
devices.

39 32 21 24 RESET

I/O C

Top priority non maskable interrupt.

40 33 22 25 V

SS_2

Digital Ground Voltage

41 34 23 26 OSC2

Resonator oscillator inverter output or
capacitor input for RC oscillator

42 35 24 27 OSC1

External clock input or Resonator os-
cillator inverter input or resistor input
for RC oscillator

43 36 25 28 V

DD_2

Digital Main Supply Voltage

44 37 26 29 PE0/TDO

I/O C

Port E0

SCI Transmit Data Out

1 38 27 30 PE1/RDI

I/O C

Port E1

SCI Receive Data In

2 39 28 31 PB0

I/O C

ei2

Port B0

3 40

PB1

I/O C

ei2

Port B1

4 41

PB2

I/O C

ei2

Port B2

5 42 29 32 PB3

I/O C

ei2

Port B3

Pin n°

Pin Name

Typ

Level

Port

Main

function

(after

reset)

Alternate Function

TQFP

SDIP

TQFP

SDIP

Inpu

Outp

Input

Output

floa

wpu

int

ana

ST72324J/K

13/156

Table 2. Hardware Register Map

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

0000h
0001h
0002h

Port A

PADR
PADDR
PAOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

00h

00h
00h

R/W
R/W
R/W

0003h
0004h
0005h

Port B

PBDR
PBDDR
PBOR

Port B Data Register
Port B Data Direction Register
Port B Option Register

00h

00h
00h

R/W
R/W
R/W

0006h
0007h
0008h

Port C

PCDR
PCDDR
PCOR

Port C Data Register
Port C Data Direction Register
Port C Option Register

00h

00h
00h

R/W
R/W
R/W

0009h

000Ah
000Bh

Port D

PDDR
PDDDR
PDOR

Port D Data Register
Port D Data Direction Register
Port D Option Register

00h

00h
00h

R/W
R/W
R/W

000Ch
000Dh
000Eh

Port E

PEDR
PEDDR
PEOR

Port E Data Register
Port E Data Direction Register
Port E Option Register

00h

00h
00h

R/W
R/W

R/W

000Fh
0010h
0011h

Port F

PFDR
PFDDR
PFOR

Port F Data Register
Port F Data Direction Register
Port F Option Register

00h

00h
00h

R/W
R/W
R/W

0012h

0020h

Reserved Area (15 Bytes)

0021h
0022h
0023h

SPI

SPIDR
SPICR
SPICSR

SPI Data I/O Register
SPI Control Register
SPI Control/Status Register

xxh
0xh

00h

R/W
R/W
R/W

0024h
0025h
0026h
0027h

ITC

ISPR0
ISPR1
ISPR2
ISPR3

Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3

FFh
FFh
FFh
FFh

R/W
R/W
R/W
R/W

0028h

EICR

External Interrupt Control Register

00h

R/W

0029h

FLASH

FCSR

Flash Control/Status Register

00h

R/W

002Ah

WATCHDOG

WDGCR

Watchdog Control Register

7Fh

R/W

002Bh

SICSR

System Integrity Control/Status Register

000x 000x b R/W

002Ch
002Dh

MCC

MCCSR
MCCBCR

Main Clock Control / Status Register
Main Clock Controller: Beep Control Register

00h
00h

R/W
R/W

002Eh

0030h

Reserved Area (3 Bytes)

ST72324J/K

14/156

Legend: x=undefined, R/W=read/write

0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h

003Ah
003Bh
003Ch
003Dh
003Eh
003Fh

TIMER A

TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Reserved

Reserved

00h
00h

xxh
xxh
xxh

80h
00h

FFh

FCh

FFh

FCh

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only

0040h

Reserved Area (1 Byte)

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h

004Ah
004Bh
004Ch
004Dh
004Eh
004Fh

TIMER B

TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

00h
00h

xxh
xxh
xxh

80h
00h

FFh

FCh

FFh

FCh

xxh
xxh

80h
00h

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h

SCI

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register

C0h

xxh

00xx xxxxb

xxh

00h
00h

---

00h

Read Only
R/W
R/W
R/W
R/W
R/W

R/W

0070h
0071h
0072h

ADC

ADCCSR
ADCDRH
ADCDRL

Control/Status Register
Data High Register
Data Low Register

00h

xxh

0000 00xxb

R/W
Read Only
Read Only

0073h
007Fh

Reserved Area (13 Bytes)

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

ST72324J/K

16/156

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
sis using an external V

supply.

The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).

The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.

4.2 Main Features

Three Flash programming modes:

Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-

grammed or erased.

ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro-

grammed or erased without removing the de-

vice from the application board.

IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro-

grammed or erased without removing the de-

vice from the application board and while the

application is running.

ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM

Read-out protection against piracy

4.3 Structure

The Flash memory is organised in sectors and can
be used for both code and data storage.

Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see

Table 3

). Each of these sectors can

be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes
(see

Figure 6

). They are mapped in the upper part

of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).

Table 3. Sectors available in Flash devices

4.3.1 Read-out Protection

Read-out protection, when selected, makes it im-
possible to extract the memory content from the
microcontroller, thus preventing piracy. Even ST
cannot access the user code.

In flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased.

Read-out protection selection depends on the de-
vice type:

In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

In ROM devices it is enabled by mask option

specified in the Option List.

Figure 6. Memory Map and Sector Address

Flash Size (bytes)

Available Sectors

Sector 0

Sectors 0,1

> 8K

Sectors 0,1, 2

4 Kbytes

2 Kbytes

SECTOR 1

SECTOR 0

16 Kbytes

SECTOR 2

16K

32K

60K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8 Kbytes

40 Kbytes 52 Kbytes

9FFFh

BFFFh

D7FFh

10K

24K

48K

ST72324J/K

17/156

FLASH PROGRAM MEMORY (Cont'd)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see

Figure 7

These pins are:

RESET: device reset
V

: device power supply ground

ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/V

: programming voltage

OSC1(or OSCIN): main clock input for exter-

nal source (optional)

: application board power supply (option-

al, see

Figure 7

, Note 3)

Figure 7. Typical ICC Interface

Notes:

1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.

2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external

reset is generated by the application during the
ICC session.

3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.

4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.

5. In the application, when the RESET pin is low,
the ICCCLK pin must always be in pull-up or high
impedance state. For instance, it must never be
forced to ground or connected to an external pull-
down. This is to avoid entering ICC mode unex-
pectedly during normal application operation.

ICC CONNECTOR

ESET

HE10 CONNECTOR TYPE

APPLICATION
POWER SUPPLY

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

OPTIONAL
(See Note 3)

10k

SEL

/VPP

ST7

OPTIONAL

See Note 1

See Notes 1 and 5

See Note 2

APPLICATION
RESET SOURCE

APPLICATION

I/O

(See Note 4)

ST72324J/K

18/156

FLASH PROGRAM MEMORY (Cont'd)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).

When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see

Figure 7

). For more details on

the pin locations, refer to the device pinout de-
scription.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).

This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming

mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro-
tected to allow recovery in case errors occur dur-
ing the programming operation.

4.6.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read /Write

Reset Value: 0000 0000 (00h)

This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations. For details on customizing
Flash programming methods and In-Circuit Test-
ing, refer to the ST7 Flash Programming Refer-
ence Manual.

Table 4. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

Register

Label

0029h

FCSR
Reset Value

ST72324J/K

19/156

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

5.2 MAIN FEATURES

Enable executing 63 basic instructions

Fast 8-bit by 8-bit multiply

17 main addressing modes (with indirect
addressing mode)

Two 8-bit index registers

16-bit stack pointer

Low power HALT and WAIT modes

Priority maskable hardware interrupts

Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The 6 CPU registers shown in

Figure 8

are not

present in the memory mapping and are accessed
by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt auto-
matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

Figure 8. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1 I1 H I0 N Z

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE = 1

1 1 X 1 X X

RESET VALUE = XXh

X = Undefined Value

ST72324J/K

20/156

CENTRAL PROCESSING UNIT (Cont'd)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-
terrupt masks

and four flags representative of the

result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.

These bits can be individually tested and/or con-
trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.

0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It's a copy of the re-
sult 7

bit.

0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-
tions.

Bit 1 = Z

Zero

This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test
instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the "bit test and branch", shift and
rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0

Interrupt

The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more
details.

Interrupt Software Priority

Level 0 (main)

Level 1

Level 2

Level 3 (= interrupt disable)

ST72324J/K

21/156

CENTRAL PROCESSING UNIT (Cont'd)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see

Figure 9

Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.

The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in

Figure 9

When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.

Figure 9. Stack Manipulation Example

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

CALL

Subroutine

Interrupt

Event

PUSH Y

POP Y

IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh
Stack Lower Address = 0100h

ST72324J/K

22/156

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in

Figure 11

For more details, refer to dedicated parametric
section.

Main features

Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)

Reset Sequence Manager (RSM)

Multi-Oscillator Clock Management (MO)

5 Crystal/Ceramic resonator oscillators
1 External RC oscillator
1 Internal RC oscillator

System Integrity Management (SI)

Main supply Low voltage detection (LVD)
Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supplyClock

Security System (CSS) with Clock Filter and

Backup Safe Oscillator (enabled by option

byte)

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f

OSC2

of 4 to 8

MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f

OSC2 =

OSC

/2.

Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
"PLL Characteristics" on page 127.

Figure 10. PLL Block Diagram

Figure 11. Clock, Reset and Supply Block Diagram

PLL OPTION BIT

PLL x 2

OSC2

/ 2

OSC

LOW VOLTAGE

DETECTOR

(LVD)

OSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

RESET SEQUENCE

MANAGER

(RSM)

CLOCK

FILTER

SAFE

OSC

CLOCK SECURITY SYSTEM

(CSS)

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD LVD

CSS

WDG

OSC

OSC2

(option)

CPU

ST72324J/K

23/156

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:

an external source

4 crystal or ceramic resonator oscillators

an external RC oscillator

an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in

Table 5

. Refer to the

electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to

Section 14.1 on page 148

for more details on

the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.

These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.

External RC Oscillator

This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components. The corresponding formula
is

OSC

=5/(R

)

Internal RC Oscillator

The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-

ing the resistance and the capacitance of the de-
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.

In this mode, the two oscillator pins have to be tied
to ground.

Table 5. ST7 Clock Sources

Hardware Configuration

Ext

ernal

Clock

Cry

stal/C

eram

sonat

ors

Exte

rnal

scillat

Inter

nal

Osc

illator

OSC1

OSC2

EXTERNAL

ST7

SOURCE

OSC1

OSC2

LOAD

CAPACITORS

ST7

OSC1

OSC2

ST7

OSC1

OSC2

ST7

ST72324J/K

24/156

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RE-
SET sources as shown in

Figure 13

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-
ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases
as shown in

Figure 12

Active Phase depending on the RESET source

256 or 4096 CPU clock cycle delay (selected by
option byte)

RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see

Section 14.1 on page 148

The RESET vector fetch phase duration is 2 clock
cycles.

Figure 12. RESET Sequence Phases

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain
output with integrated R

weak pull-up resistor.

This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It

can be pulled

low by external circuitry to reset the device. See

"CONTROL PIN CHARACTERISTICS" on
page 137

for more details.

A RESET signal originating from an external
source must have a duration of at least t

h(RSTL)in

order to be recognized (see

Figure 14

). This de-

tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.

Figure 13. Reset Block Diagram

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET

LVD RESET

INTERNAL
RESET

PULSE

GENERATOR

Filter

ST72324J/K

25/156

RESET SEQUENCE MANAGER (Cont'd)

The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.

If the external RESET pulse is shorter than
t

w(RSTL)out

(see short ext. Reset in

Figure 14

), the

signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in

Figure 14

). Starting from the external RE-

SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
t

w(RSTL)out

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V

is over the minimum

level specified for the selected f

OSC

frequency.

(see

"OPERATING CONDITIONS" on page 114

)

A proper reset signal for a slow rising V

supply

can generally be provided by an external RC net-
work connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)
RESET

Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:

Power-On RESET

Voltage Drop RESET

The device RESET pin acts as an output that is
pulled low when V

IT+

(rising edge) or

IT-

(falling edge) as shown in

Figure 14

The LVD filters spikes on V

larger than t

g(VDD)

avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow is shown in

Figure 14

Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t

w(RSTL)out

Figure 14. RESET Sequences

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

w(RSTL)out

RUN

h(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

w(RSTL)out

RUN

RESET

RESET
SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

w(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

DELAY

ST72324J/K

26/156

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains
the Low Voltage Detector (LVD), Auxiliary Voltage
Detector (AVD) and Clock Security System (CSS)
functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) gener-
ates a static reset when the V

supply voltage is

below a V

IT-

reference value. This means that it

secures the power-up as well as the power-down
keeping the ST7 in reset.

The V

IT-

reference value for a voltage drop is lower

than the V

IT+

reference value for power-on in order

to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when
V

is below:

IT+

when V

is rising

IT-

when V

is falling

The LVD function is illustrated in

Figure 15

The voltage threshold can be configured by option
byte to be low, medium or high.

Provided the minimum V

value (guaranteed for

the oscillator frequency) is above V

IT-

, the MCU

can only be in two modes:

under full software control
in static safe reset

In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.

Notes:

The LVD allows the device to be used without any
external RESET circuitry.

The LVD is an optional function which can be se-
lected by option byte.

Figure 15. Low Voltage Detector vs Reset

IT+

RESET

IT-

hys

ST72324J/K

27/156

SYSTEM INTEGRITY MANAGEMENT (Cont'd)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on
an analog comparison between a V

IT-(AVD)

and

IT+(AVD)

reference value and the V

main sup-

ply. The V

IT-

reference value for falling voltage is

lower than the V

IT+

reference value for rising volt-

age in order to avoid parasitic detection (hystere-
sis).

The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.

6.4.2.1 Monitoring the V

Main Supply

The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see

Section 14.1 on page 148

If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V

IT+(AVD)

IT-(AVD)

threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See

Figure 16

The interrupt on the rising edge is used to inform
the application that the V

warning state is over.

If the voltage rise time t

is less than 256 or 4096

CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when V

IT+(AVD)

is reached.

If t

is greater than 256 or 4096 cycles then:

If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then 2 AVD inter-

rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.

If the AVD interrupt is enabled after the V

IT+(AVD)

threshold is reached then only one AVD interrupt
will occur.

Figure 16. Using the AVD to Monitor V

IT+(AVD)

IT-(AVD)

AVDF bit

RESET VALUE

IF AVDIE bit = 1

hyst

AVD INTERRUPT
REQUEST

INTERRUPT PROCESS

IT+(LVD)

IT-(LVD)

LVD RESET

Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)

VOLTAGE RISE TIME

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SYSTEM INTEGRITY MANAGEMENT (Cont'd)

6.4.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the
ST7 against breakdowns, spikes and overfrequen-
cies occurring on the main clock source (f

OSC

). It

is based on a clock filter and a clock detection con-
trol with an internal safe oscillator (f

SFOSC

6.4.3.1 Clock Filter Control

The PLL has an integrated glitch filtering capability
making it possible to protect the internal clock from
overfrequencies created by individual spikes. This
feature is available only when the PLL is enabled.
If glitches occur on f

OSC

(for example, due to loose

connection or noise), the CSS filters these auto-
matically, so the internal CPU frequency (f

CPU

)

continues deliver a glitch-free signal (s

ee Figure

17)

6.4.3.2 Clock detection Control

If the clock signal disappears (due to a broken or
disconnected resonator...), the safe oscillator de-
livers a low frequency clock signal (f

SFOSC

) which

allows the ST7 to perform some rescue opera-
tions.

Automatically, the ST7 clock source switches back
from the safe oscillator (f

SFOSC

) if the main clock

source (f

OSC

) recovers.

When the internal clock (f

CPU

) is driven by the safe

oscillator (f

SFOSC

), the application software is noti-

fied by hardware setting the CSSD bit in the SIC-
SR register. An interrupt can be generated if the

CSSIE bit has been previously set.
These two bits are described in the SICSR register
description.

6.4.4 Low Power Modes

6.4.4.1 Interrupts

The CSS or AVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).

Figure 17. Clock Filter Function

Mode Description

WAIT

No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.

HALT

The CRSR register is frozen.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
"exit from HALT mode" capability or from
the counter reset value when the MCU is
woken up by a RESET.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

CSS event detection
(safe oscillator acti-
vated as main clock)

CSSD

CSSIE

Yes

AVD event

AVDF

AVDIE

Yes

OSC2

CPU

OSC2

CPU

SFOSC

Clock Filter Function

Clock Detection Function

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SYSTEM INTEGRITY MANAGEMENT (Cont'd)

6.4.5 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read /Write

Reset Value: 000x 000x (00h)

Bit 6 = AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled

Bit 5 = AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value. Refer to

Figure 16

and to

Section 6.4.2.1

for additional de-

tails.
0: V

over V

IT+(AVD)

threshold

1: V

under V

IT-(AVD)

threshold

Bit 4 = LVDRF

LVD reset flag

This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE

Clock security syst

interrupt enable

This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled

1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.

Bit 1 = CSSD

Clock security system detection

This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
signal (f

OSC

). It is set by hardware and cleared by

reading the SICSR register when the original oscil-
lator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.

Bit 0 = WDGRF

Watchdog reset flag

This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.

Application notes

The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.

CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.

AVD

LVD

CSS

WDG

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management pro-
vides the following features:

Hardware interrupts

Software interrupt (TRAP)

Nested or concurrent interrupt management
with flexible interrupt priority and level
management:

Up to 4 software programmable nesting levels
Up to 16 interrupt vectors fixed by hardware
2 non maskable events: RESET, TRAP

This interrupt management is based on:

Bit 5 and bit 3 of the CPU CC register (I1:0),

Interrupt software priority registers (ISPRx),

Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see

Table 6

). The process-

ing flow is shown in

Figure 18

When an interrupt request has to be serviced:

Normal processing is suspended at the end of

the current instruction execution.

The PC, X, A and CC registers are saved onto

the stack.

I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers
of the serviced interrupt vector.

The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
"Interrupt Mapping" table for vector addresses).

The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Figure 18. Interrupt Processing Flowchart

Interrupt software priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= interrupt disable)

"IRET"

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

TRAP

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT
STAYS PENDING

than current one

I
n

t
e

upt

has

i
g

r
e

r
i
o

r
i
ty

t
h

ent

EXECUTE

INSTRUCTION

INTERRUPT

ST72324J/K

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INTERRUPTS (Cont'd)

Servicing Pending Interrupts

As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:

the highest software priority interrupt is serviced,

if several interrupts have the same software pri-

ority then the interrupt with the highest hardware
priority is serviced first.

Figure 19

describes this decision process.

Figure 19. Priority Decision Process

When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.

Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET and TRAP are non maskable and
they can be considered as having the highest soft-
ware priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see

Figure 18

). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.

TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in

Figure 18

RESET

The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.

External Interrupts

External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitiv-
ity is software selectable through the External In-
terrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.

Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the "Interrupt Mapping" table. A peripheral inter-
rupt occurs when a specific flag is set in the pe-
ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

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INTERRUPTS (Cont'd)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column "Exit
from HALT" in "Interrupt Mapping" table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in

Figure 19

Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following

Figure 20

and

Figure 21

show two

different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in

Figure 21

. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv-
en for each interrupt.

Warning: A stack overflow may occur without no-
tifying the software of the failure.

Figure 20. Concurrent Interrupt Management

Figure 21. Nested Interrupt Management

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

RDWA

RIT

SOFTWARE

3/0

1 1

11 / 10

1 1

RIM

IT2

IT1

IT4

TRAP

IT3

IT0

IT3

PRIORITY
LEVEL

USED

STA

YTES

MAIN

IT2

TRAP

MAIN

IT0

IT2

IT1

IT4

RAP

IT3

IT0

RDW

I
O

3/0

1 1

0 0

0 1

1 1

RIM

IT1

IT4

IT1

IT2

IT3

11 / 10

SOFTWARE
PRIORITY
LEVEL

SED

STAC

TES

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INTERRUPTS (Cont'd)

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read /Write

Reset Value: 111x 1010 (xAh)

Bit 5, 3 = I1, I0

Software Interrupt Priority

These two bits indicate the current interrupt soft-
ware priority.

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).

They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see "Interrupt Dedicated Instruction
Set" table).

*Note: TRAP and RESET events are non maska-
ble sources and can interrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only)

Reset Value: 1111 1111 (FFh)

These four registers contain the interrupt software
priority of each interrupt vector.

Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.

Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits
in the CC register.

Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).

Interrupt Software Priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= interrupt disable*)

ISPR0

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

I1_0

I0_0

ISPR1

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

ISPR2

I1_11 I0_11 I1_10 I0_10 I1_9

I0_9

I1_8

I0_8

ISPR3

I1_13 I0_13 I1_12 I0_12

Vector address

ISPRx bits

FFFBh-FFFAh

I1_0 and I0_0 bits*

FFF9h-FFF8h

I1_1 and I0_1 bits

...

FFE1h-FFE0h

I1_13 and I0_13 bits

ST72324J/K

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INTERRUPTS (Cont'd)

Table 8. Interrupt Mapping

Notes:

1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits
from ACTIVE-HALT mode only.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(

Figure 22

). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

Each external interrupt source can be generated
on four (or five) different events on the pin:

Falling edge

Rising edge

Falling and rising edge

Falling edge and low level

Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.

The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.

N°

Source

Block

Description

Register

Label

Priority

Order

Exit

from

HALT

Address

Vector

RESET

Reset

N/A

yes

FFFEh-FFFFh

TRAP

Software interrupt

FFFCh-FFFDh

Not used

FFFAh-FFFBh

MCC/RTC

CSS

Main clock controller time base interrupt
Safe oscillator activation interrupt

MCCSR

SICSR

Higher

Priority

yes

FFF8h-FFF9h

ei0

External interrupt port A3..0

N/A

yes

FFF6h-FFF7h

ei1

External interrupt port F2..0

yes

FFF4h-FFF5h

ei2

External interrupt port B3..0

yes

FFF2h-FFF3h

ei3

External interrupt port B7..4

yes

FFF0h-FFF1h

SPI

SPI peripheral interrupts

SPICSR

yes

FFECh-FFEDh

TIMER A

TIMER A peripheral interrupts

TASR

FFEAh-FFEBh

TIMER B

TIMER B peripheral interrupts

TBSR

FFE8h-FFE9h

SCI

SCI Peripheral interrupts

SCISR

Lower

Priority

FFE6h-FFE7h

AVD

Auxiliary Voltage detector interrupt

SICSR

FFE4h-FFE5h

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7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)

- ei3 (port B4)

These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).

Bit 5 = IPB

Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion

Bit 4:3 = IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:

- ei0 (port A3..0)

- ei1 (port F2..0)

These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).

Bit 2 = IPA

Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion

Bits 1:0 = Reserved, must always be kept cleared.

IS11

IS10

IPB

IS21

IS20

IPA

IS11 IS10

External Interrupt Sensitivity

IPB bit =0

IPB bit =1

Falling edge &

low level

Rising edge

& high level

Rising edge only

Falling edge only

Rising edge only

Rising and falling edge

IS11 IS10

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

IS21 IS20

External Interrupt Sensitivity

IPA bit =0

IPA bit =1

Falling edge &

low level

Rising edge

& high level

Rising edge only

Falling edge only

Rising edge only

Rising and falling edge

IS21 IS20

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

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8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see

Figure 23

): SLOW, WAIT (SLOW WAIT), AC-

TIVE HALT and HALT.

After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(f

OSC2

From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.

Figure 23. Power Saving Mode Transitions

8.2 SLOW MODE

This mode has two targets:

To reduce power consumption by decreasing the

internal clock in the device,

To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f

CPU

In this mode, the master clock frequency (f

OSC2

)

can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(f

CPU

Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.

Figure 24. SLOW Mode Clock Transitions

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

SMS

CP1:0

CPU

NEW SLOW

NORMAL RUN MODE

MCCS

FREQUENCY

REQUEST

OSC2

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POWER SAVING MODES (Cont'd)

8.3 WAIT MODE

WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
`WFI' instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to `10',
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.

Refer to

Figure 25

Figure 25. WAIT Mode Flow-chart

Note:

1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

256 OR 4096 CPU CLOCK

CYCLE DELAY

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POWER SAVING MODES (Cont'd)

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the `HALT' instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the `HALT' in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see

Section

10.2 on page 55

for more details on the MCCSR

The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see

Table 8, "Interrupt Mapping," on

page 35

) or a RESET. When exiting ACTIVE-

HALT mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see

Figure 27

When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to `10b' to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode fol-
lowing an interrupt, OIE bit of MCCSR register
must not be cleared before t

DELAY

after the inter-

rupt occurs (t

DELAY

= 256 or 4096 t

CPU

delay de-

pending on option byte). Otherwise, the ST7 en-
ters HALT mode for the remaining t

DELAY

period.

Figure 26. ACTIVE-HALT Timing Overview

Figure 27. ACTIVE-HALT Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to

Table 8, "Interrupt Mapping," on page 35

for more

details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

HALT mode

ACTIVE-HALT mode

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE=1)

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POWER SAVING MODES (Cont'd)

8.4.2 HALT MODE

The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
`HALT' instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see

Section 10.2 on page 55

for more de-

tails on the MCCSR register).

The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see

Table 8, "Interrupt

Mapping," on page 35

) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see

Fig-

ure 29

When entering HALT mode, the I[1:0] bits in the
CC register are forced to `10b'to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.

In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).

The compatibility of Watchdog operation with
HALT mode is configured by the "WDGHALT" op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see

Section 14.1 on page 148

for more details).

Figure 28. HALT Timing Overview

Figure 29. HALT Mode Flow-chart

Notes:

1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to

Table 8, "Interrupt Mapping," on page 35

for

more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE=0]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

OFF
OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR
PERIPHERALS

I[1:0] BITS

ON
ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

(MCCSR.OIE=0)

CYCLE

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POWER SAVING MODES (Cont'd)

8.4.2.1 Halt Mode Recommendations

Make sure that an external event is available to

wake up the microcontroller from Halt mode.

When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O
as "Input Pull-up with Interrupt" before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.

For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-
tionary measure.

The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.

As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).

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9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes:
transfer of data through digital inputs and outputs

and for specific pins:
external interrupt generation
alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

Data Register (DR)

Data Direction Register (DDR)

and one optional register:

Option Register (OR)

Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.

The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in

Figure 30

9.2.1 Input Modes

The input configuration is selected by clearing the
corresponding DDR register bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Different input modes can be selected by software
through the OR register.

Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register

External interrupt function

When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.

Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.

Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.

The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.

Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.

DR register value and output pin status:

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.

When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).

When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.

Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.

Push-pull

Open-drain

Vss

Floating

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I/O PORTS (Cont'd)

CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.

It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.

WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.

Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in

Figure 31

Other transitions

are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.

Figure 31. Interrupt I/O Port State Transitions

9.4 LOW POWER MODES

9.5 INTERRUPTS

The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).

Mode Description

WAIT

No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.

HALT

No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on
selected external
event

DDRx

ORx

Yes

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

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I/O PORTS (Cont'd)

9.5.1 I/O Port Implementation

The I/O port register configurations are summa-
rised as follows.

Standard Ports

PA5:4, PC7:0, PD5:0,
PE1:0, PF7:6, 4

Interrupt Ports

PB4, PB2:0, PF1:0 (with pull-up)

PA3, PB3, PF2 (without pull-up)

True Open Drain Ports

PA7:6

Table 12. Port Configuration

MODE

DDR

floating input

pull-up input

open drain output

push-pull output

MODE

DDR

floating input

pull-up interrupt input

open drain output

push-pull output

MODE

DDR

floating input

floating interrupt input

open drain output

push-pull output

MODE

DDR

floating input

open drain (high sink ports)

Port

Pin name

Input

Output

OR = 0

OR = 1

OR = 0

OR = 1

Port A

PA7:6

floating

true open-drain

PA5:4

floating

pull-up

open drain

push-pull

PA3

floating

floating interrupt

open drain

push-pull

Port B

PB3

floating

floating interrupt

open drain

push-pull

PB4, PB2:0

floating

pull-up interrupt

open drain

push-pull

Port C

PC7:0

floating

pull-up

open drain

push-pull

Port D

PD5:0

floating

pull-up

open drain

push-pull

Port E

PE1:0

floating

pull-up

open drain

push-pull

Port F

PF7:6, 4

floating

pull-up

open drain

push-pull

PF2

floating

floating interrupt

open drain

push-pull

PF1:0

floating

pull-up interrupt

open drain

push-pull

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10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter's contents before the T6 bit be-
comes cleared.

10.1.2 Main Features

Programmable timer

Programmable reset

Reset (if watchdog activated) when the T6 bit
reaches zero

Optional reset on HALT instruction
(configurable by option byte)

Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 f

OSC2

cycles (approx.), and the

length of the timeout period can be programmed
by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.

The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. The value to
be stored in the WDGCR register must be be-
tween FFh and C0h:

The WDGA bit is set (watchdog enabled)

The T6 bit is set to prevent generating an imme-

diate reset

The T[5:0] bits contain the number of increments

which represents the time delay before the
watchdog produces a reset (see

Figure 33. Ap-

proximate Timeout Duration

). The timing varies

between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see

Figure 34

Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction
will generate a Reset.

Figure 32. Watchdog Block Diagram

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

OSC2

WDG PRESCALER

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 4

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

MCC/RTC

TB[1:0] bits
(MCCSR
Register)

ST72324J/K

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WATCHDOG TIMER (Cont'd)

Figure 34. Exact Timeout Duration (t

min

and t

max

)

WHERE:
t

min0

= (LSB + 128) x 64 x t

OSC2

max0

= 16384 x t

OSC2

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register

To calculate the minimum Watchdog Timeout (t

min

THEN

ELSE

To calculate the maximum Watchdog Timeout (t

max

THEN

ELSE

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

TB1 Bit

(MCCSR Reg.)

TB0 Bit

(MCCSR Reg.)

Selected MCCSR

Timebase

MSB

LSB

2ms

4ms

10ms

25ms

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. Watchdog

Timeout (ms)

min

Max. Watchdog

Timeout (ms)

max

1.496

2.048

128

128.552

CNT

MSB

-------------

m in

min0

16384

CNT

osc2

min

min0

16384

CN T

4 CNT

MSB

-----------------

192

LS B

(

)

4CNT

MSB

-----------------

osc2

CNT

MSB

-------------

ma x

max0

16384

C NT

osc2

max

max0

16384

C NT

4CNT

MSB

-----------------

192

LSB

(

)

4CNT

MSB

-----------------

osc2

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WATCHDOG TIMER (Cont'd)

10.1.5 Low Power Modes

10.1.6 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.

10.1.7 Using Halt Mode with the WDG
(WDGHALT option)

The following recommendation applies if Halt
mode is used when the watchdog is enabled.

Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.

10.1.8 Interrupts

None.

10.1.9 Register Description

CONTROL REGISTER (WDGCR)

Read /Write

Reset Value: 0111 1111 (7F h)

Bit 7 = WDGA

Activation bit

This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled

Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.

Bit 6:0 = T[6:0]

7-bit counter (MSB to LSB).

These bits contain the value of the watchdog
counter. It is decremented every 16384 f

OSC2

cy-

cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).

Mode Description

SLOW

No effect on Watchdog.

WAIT

No effect on Watchdog.

HALT

OIE bit in

MCCSR
register

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.

If an external interrupt is received, the Watchdog restarts counting after 256
or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see

Section 10.1.7

below.

A reset is generated.

No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.

WDGA

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10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three differ-
ent functions:

a programmable CPU clock prescaler

a clock-out signal to supply external devices

a real time clock timer with interrupt capability

Each function can be used independently and si-
multaneously.

10.2.1 Programmable CPU Clock Prescaler

The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See

Section 8.2 SLOW MODE

for more details).

The prescaler selects the f

CPU

main clock frequen-

cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.

10.2.2 Clock-out Capability

The clock-out capability is an alternate function of
an I/O port pin that outputs a f

OSC2

clock to drive

external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.

10.2.3 Real Time Clock Timer (RTC)

The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
ing directly on f

OSC2

are available. The whole

functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See

Section 8.4 AC-

TIVE-HALT AND HALT MODES

for more details.

10.2.4 Beeper

The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).

Figure 35. Main Clock Controller (MCC/RTC) Block Diagram

DIV 2, 4, 8, 16

MCC/RTC INTERRUPT

SMS

CP1 CP0

TB1

TB0

OIE

OIF

CPU CLOCK

MCCSR

12-BIT MCC RTC

COUNTER

TO CPU AND

PERIPHERALS

OSC2

CPU

MCO

BC1 BC0

MCCBCR

BEEP

GENERATOR

BEEP SIGNAL

WATCHDOG

TIMER

DIV 64

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd)

10.2.5 Low Power Modes

10.2.6 Interrupts

The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).

Note:

The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.

10.2.7 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)

Read /Write

Reset Value: 0000 0000 (00h

)

Bit 7 = MCO

Main clock out selection

This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

CPU

on I/O

port)

Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.

Bit 6:5 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software

Bit 4 = SMS

Slow mode select

This bit is set and cleared by software.
0: Normal mode. f

CPU

OSC2

1: Slow mode. f

CPU

is given by CP1, CP0

See

Section 8.2 SLOW MODE

and

Section 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC)

for more de-

tails.

Bit 3:2 = TB[1:0]

Time base control

These bits select the programmable divider time
base. They are set and cleared by software.

A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.

Bit 1 = OIE

Oscillator interrupt enable

This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode

Mode Description

WAIT

No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.

ACTIVE-
HALT

No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.

HALT

MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with "exit
from HALT" capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Time base overflow
event

OIF

OIE

Yes

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

CPU

in SLOW mode

CP1

CP0

OSC2

/ 2

OSC2

/ 4

OSC2

/ 8

OSC2

/ 16

Counter

Prescaler

Time Base

TB1

TB0

OSC2

=4MHz f

OSC2

=8MHz

16000

4ms

2ms

32000

8ms

4ms

80000

20ms

10ms

200000

50ms

25ms

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd)

Bit 0 = OIF

Oscillator interrupt flag

This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached

CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.

Table 15. Main Clock Controller Register Map and Reset Values

BC1

BC0

BC1

BC0

Beep mode with f

OSC2

=8MHz

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

Address

(Hex.)

Register

Label

002Bh

SICSR
Reset Value

VDS

VDIE

VDF

LVDRF

CFIE

CSSD

WDGRF

002Ch

MCCSR
Reset Value

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

002Dh

MCCBCR
Reset Value

BC1

BC0

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10.3 16-BIT TIMER

10.3.1 Introduction

The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.

It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (

input capture

) or generation of up to two out-

put waveforms (

output compare

and

PWM

Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.

Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.

This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).

10.3.2 Main Features

Programmable prescaler: f

CPU

divided by 2, 4 or 8.

Overflow status flag and maskable interrupt

External clock input (must be at least 4 times
slower than the CPU

clock speed) with the choice

of active edge

1 or 2 Output Compare functions each with:

2 dedicated 16-bit registers

2 dedicated programmable signals

2 dedicated status flags

1 dedicated maskable interrupt

1 or 2 Input Capture functions each with:

2 dedicated 16-bit registers

2 dedicated active edge selection signals

2 dedicated status flags

1 dedicated maskable interrupt

Pulse width modulation mode (PWM)

One pulse mode

Reduced Power Mode

5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in

Figure 36

*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.

When reading an input signal on a non-bonded
pin, the value will always be `1'.

10.3.3 Functional Description

10.3.3.1 Counter

The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.

Counter Register (CR):

Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).

Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits
of the CR2 register, as illustrated in

Table 16 Clock

Control Bits

. The value in the counter register re-

peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
The timer frequency can be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

ST72324J/K

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16-BIT TIMER (Cont'd)

16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).

The user must read the MS Byte first, then the LS
Byte value is buffered automatically.

This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.

After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.

Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:

The TOF bit of the SR register is set.

A timer interrupt is generated if:

TOIE bit of the CR1 register is set and

I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

Clearing the overflow interrupt request is done in
two steps:

1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).

10.3.3.2 External Clock

The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.

The counter is synchronized with the falling edge
of the internal CPU clock.

A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.

is buffered

Read

At t0

Read

Returns the buffered
LS Byte value at t0

At t0 +

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

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16-BIT TIMER (Cont'd)

10.3.3.3 Input Capture

In this section, the index,

, may be 1 or 2 because

there are 2 input capture functions in the 16-bit
timer.

The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAP

pin (see figure 5).

R register is a read-only register.

The active transition is software programmable
through the IEDG

bit of Control Registers (CR

Timing resolution is one count of the free running
counter: (

CPU

CC[1:0]).

Procedure:

To use the input capture function select the follow-
ing in the CR2 register:

Select the timer clock (CC[1:0]) (see

Table 16

Clock Control Bits

Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).

And select the following in the CR1 register:

Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin
or the ICAP2 pin

Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).

When an input capture occurs:

ICF

bit is set.

The IC

R register contains the value of the free

running counter on the active transition on the
ICAP

pin (see

Figure 41

A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.

Clearing the Input Capture interrupt request (i.e.
clearing the ICF

bit) is done in two steps:

1. Reading the SR register while the ICF

bit is set.

2. An access (read or write) to the IC

Notes:

1. After reading the IC

HR register, transfer of

input capture data is inhibited and ICF

will

never be set until the IC

LR register is also

read.

2. The IC

R register contains the free running

counter value which corresponds to the most
recent input capture.

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output
compare functions.

4. In One pulse Mode and PWM mode only Input

Capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAP

pins is configured

as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion

is disabled by reading the IC

HR (see note

1).

6. The TOF bit can be used with interrupt genera-

tion in order to measure events that go beyond
the timer range (FFFFh).

MS Byte

LS Byte

ICiR

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16-BIT TIMER (Cont'd)

10.3.3.4 Output Compare

In this section, the index,

, may be 1 or 2 because

there are 2 output compare functions in the 16-bit
timer.

This function can be used to control an output
waveform or indicate when a period of time has
elapsed.

When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:

Assigns pins with a programmable value if the

E bit is set

Sets a flag in the status register

Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.

These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC

R value to 8000h.

Timing resolution is one count of the free running
counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the fol-
lowing in the CR2 register:

Set the OC

E bit if an output is needed then the

OCMP

pin is dedicated to the output compare

signal.

Select the timer clock (CC[1:0]) (see

Table 16

Clock Control Bits

And select the following in the CR1 register:

Select the OLVL

bit to applied to the OCMP

pins

after the match occurs.

Set the OCIE bit to generate an interrupt if it is

needed.

When a match is found between OCRi register
and CR register:

OCF

bit is set.

The OCMP

pin takes OLVL

bit value (OCMP

pin latch is forced low during reset).

A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in
the CC register (CC).

The OC

R register value required for a specific tim-

ing application can be calculated using the follow-
ing formula:

Where:

= Output compare period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see

Table 16

Clock Control Bits

)

If the timer clock is an external clock, the formula
is:

Where:

= Output compare period (in seconds)

EXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e.
clearing the OCF

bit) is done by:

1. Reading the SR register while the OCF

bit is

set.

2. An access (read or write) to the OC

LR register.

The following procedure is recommended to pre-
vent the OCF

bit from being set between the time

it is read and the write to the OC

Write to the OC

HR register (further compares

are inhibited).

Read the SR register (first step of the clearance

of the OCF

bit, which may be already set).

Write to the OC

LR register (enables the output

compare function and clears the OCF

bit).

MS Byte

LS Byte

R =

CPU

PRESC

R =

EXT

ST72324J/K

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16-BIT TIMER (Cont'd)

Notes:

1. After a processor write cycle to the OC

reg-

ister, the output compare function is inhibited
until the OC

2. If the OC

E bit is not set, the OCMP

pin is a

general I/O port and the OLVL

bit will not

appear when a match is found but an interrupt
could be generated if the OCIE bit is set.

3. When the timer clock is f

CPU

/2, OCF

and

OCMP

are set while the counter value equals

the OC

R register value (see

Figure 43 on page

). This behaviour is the same in OPM or

PWM mode.
When the timer clock is f

CPU

/4, f

CPU

/8 or in

external clock mode, OCF

and OCMP

are set

while the counter value equals the OC

R regis-

ter value plus 1 (see

Figure 44 on page 67

4. The output compare functions can be used both

for generating external events on the OCMP

pins even if the input capture mode is also
used.

5. The value in the 16-bit OC

OLV

bit should be changed after each suc-

cessful comparison in order to control an output
waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLV

bit is set by software, the OLVL

bit is copied to the OCMP

pin. The OLV

bit has to

be toggled in order to toggle the OCMP

pin when

it is enabled (OC

E bit=1). The OCF

bit is then not

set by hardware, and thus no interrupt request is
generated.

The FOLVL

bits have no effect in both one pulse

mode and PWM mode.

Figure 42. Output Compare Block Diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E

CC0

CC1

OC2E

OLVL1

OLVL2

OCIE

(Control Register 1) CR1

(Control Register 2) CR2

OCF2

OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

ST72324J/K

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16-BIT TIMER (Cont'd)

10.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1
function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-
mula in the opposite column).

2. Select the following in the CR1 register:

Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit

(the ICAP1 pin

must be configured as floating input).

3. Select the following in the CR2 register:

Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

Set the OPM bit.

Select the timer clock CC[1:0] (see

Table 16

Clock Control Bits

Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.

Clearing the Input Capture interrupt request (i.e.
clearing the ICF

bit) is done in two steps:

1. Reading the SR register while the ICF

bit is set.

2. An access (read or write) to the IC

The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:

Where:
t

= Pulse period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see

Table 16

Clock Control Bits

)

If the timer clock is an external clock the formula is:

Where:

= Pulse period (in seconds)

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See

Figure 45

Notes:

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an
Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.

event occurs

Counter
= OC1R

OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

R Value =

CPU

PRESC

- 5

R =

EXT

-5

ST72324J/K

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16-BIT TIMER (Cont'd)

10.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.

Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.

In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the
formula in the opposite column.

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.

3. Select the following in the CR1 register:

Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful
comparison with the OC1R register.

Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful
comparison with the OC2R register.

4. Select the following in the CR2 register:

Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

Set the PWM bit.

Select the timer clock (CC[1:0]) (see

Table 16

Clock Control Bits

If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.

The OC

R register value required for a specific tim-

ing application can be calculated using the follow-
ing formula:

Where:
t

= Signal or pulse period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see

Table 16 Clock

Control Bits

)

If the timer clock is an external clock the formula is:

Where:

= Signal or pulse period (in seconds)

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter
to be initialized to FFFCh (See

Figure 46

)

Notes:

1. After a write instruction to the OC

HR register,

the output compare function is inhibited until the
OC

LR register is also written.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output
Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.

Counter

OCMP1 = OLVL2

Counter
= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

R Value =

CPU

PRESC

- 5

R =

EXT

-5

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16-BIT TIMER (Cont'd)

10.3.4 Low Power Modes

10.3.5 Interrupts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

10.3.6 Summary of Timer modes

1) See note 4 in

Section 10.3.3.5 One Pulse Mode

2) See note 5 in

Section 10.3.3.5 One Pulse Mode

3) See note 4 in

Section 10.3.3.6 Pulse Width Modulation Mode

Mode Description

WAIT

No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter
reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP

pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICF

bit is set, and

the counter value present when exiting from HALT mode is captured into the IC

R register.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode

ICF1

ICIE

Yes

Input Capture 2 event

ICF2

Yes

Output Compare 1 event (not available in PWM mode)

OCF1

OCIE

Yes

Output Compare 2 event (not available in PWM mode)

OCF2

Yes

Timer Overflow event

TOF

TOIE

Yes

MODES

TIMER RESOURCES

Input Capture 1

Input Capture 2

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Yes

Output Compare (1 and/or 2)

Yes

One Pulse Mode

Not Recommended

Partially

PWM Mode

Not Recommended

ST72324J/K

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16-BIT TIMER (Cont'd)

10.3.7 Register Description

Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = ICIE

Input Capture Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE

Output Compare Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE

Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.

Bit 3 = FOLV1

Forced Output Compare 1.

This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-
cessful comparison.

Bit 2 = OLVL2

Output Level 2.

This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.

Bit 1 = IEDG1

Input Edge 1.

This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Bit 0 = OLVL1

Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

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16-BIT TIMER (Cont'd)

CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM

One Pulse Mode.

0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.

Bit 4 = PWM

Pulse Width Modulation.

0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.

Bit 3, 2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.

Bit 1 = IEDG2

Input Edge 2.

This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Timer Clock

CC1

CC0

CPU

/ 4

CPU

/ 2

CPU

/ 8

External Clock (where

available)

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16-BIT TIMER (Cont'd)

CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W)

Reset Value: xxxx x0xx (xxh)

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value).
1: The content of the free running counter has

matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.

Note: Reading or writing the ACLR register does
not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value).
1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value).
1: The content of the free running counter has

matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.

Bit 2 = TIMD

Timer disable.

This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

ICF1

OCF1

TOF

ICF2

OCF2 TIMD

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16-BIT TIMER (Cont'd)

OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)

Read/Write
Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.

OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)

Read/Write
Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.

COUNTER HIGH REGISTER (CHR)

Read Only
Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part
of the counter value.

COUNTER LOW REGISTER (CLR)

Read Only
Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.

ALTERNATE COUNTER HIGH REGISTER
(ACHR)

Read Only
Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part
of the counter value.

ALTERNATE COUNTER LOW REGISTER
(ACLR)

Read Only
Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

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16-BIT TIMER (Cont'd)

Table 17. 16-Bit Timer Register Map and Reset Values

These bits are not used in Timer A and must be

kept cleared.

Address

(Hex.)

Register

Label

Timer A: 32
Timer B: 42

CR1
Reset Value

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Timer A: 31
Timer B: 41

CR2
Reset Value

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

Timer A: 33
Timer B: 43

CSR
Reset Value

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Timer A: 34
Timer B: 44

IC1HR
Reset Value

MSB

LSB

Timer A: 35
Timer B: 45

IC1LR
Reset Value

MSB

LSB

Timer A: 36
Timer B: 46

OC1HR
Reset Value

MSB

LSB

Timer A: 37
Timer B: 47

OC1LR
Reset Value

MSB

LSB

Timer B: 4E

OC2HR
Reset Value

MSB

LSB

Timer B: 4F

OC2LR
Reset Value

MSB

LSB

Timer A: 38
Timer B: 48

CHR
Reset Value

MSB

LSB

Timer A: 39
Timer B: 49

CLR
Reset Value

MSB

LSB

Timer A: 3A
Timer B: 4A

ACHR
Reset Value

MSB

LSB

Timer A: 3B
Timer B: 4B

ACLR
Reset Value

MSB

LSB

Timer B: 4C

IC2HR
Reset Value

MSB

LSB

Timer B: 4D

IC2LR
Reset Value

MSB

LSB

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10.4 SERIAL PERIPHERAL INTERFACE (SPI)

10.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.

10.4.2 Main Features

Full duplex synchronous transfers (on 3 lines)

Simplex synchronous transfers (on 2 lines)

Master or slave operation

Six master mode frequencies (f

CPU

/4 max.)

CPU

/2 max. slave mode frequency

SS Management by software or hardware

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision, Master Mode Fault and Overrun
flags

10.4.3 General Description

Figure 47

shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

SPI Control Register (SPICR)

SPI Control/Status Register (SPICSR)

SPI Data Register (SPIDR)

The SPI is connected to external devices through
3 pins:

MISO: Master In / Slave Out data

MOSI: Master Out / Slave In data

SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

SS: Slave select:

This input signal acts as a `chip select' to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.

Figure 47. Serial Peripheral Interface Block Diagram

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE

SPE

MSTR

CPHA

SPR0

SPR1

CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK

CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL

MODF

OVR

SSI

SSM

SOD

bit

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.3.1 Functional Description

A basic example of interconnections between a
single master and a single slave is illustrated in

Figure 48

The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).

The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-

sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).

Four possible data/clock timing relationships may
be chosen (see

Figure 51

) but master and slave

must be programmed with the same timing mode.

Figure 48. Single Master/ Single Slave Application

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit

LSBit

MSBit

LSBit

Not used if SS is managed
by software

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.3.2 Slave Select Management

As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see

Figure 50

)

In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.

In Master mode:

SS internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock
timing relationship (see

Figure 49

If CPHA=1 (data latched on 2nd clock edge):

SS internal must be held low during the entire

transmission. This implies that in single slave

applications the SS pin either can be tied to

, or made free for standard I/O by manag-

ing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

SS internal must be held low during byte

transmission and pulled high between each

byte to allow the slave to write to the shift reg-

ister. If SS is not pulled high, a Write Collision

error will occur when the slave writes to the

shift register (see

Section 10.4.5.3

Figure 49. Generic SS Timing Diagram

Figure 50. Hardware/Software Slave Select Management

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1

Byte 2

Byte 3

SS internal

SSM bit

SSI bit

SS external pin

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).

Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).

To operate the SPI in master mode, perform the
following two steps in order (if the SPICSR register
is not written first, the SPICR register setting may
be not taken into account):

1. Write to the SPICSR register:

Select the clock frequency by configuring the

SPR[2:0]

bits.

Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits.

Figure

shows the four possible configurations.

Note: The slave must have the same CPOL

and CPHA settings as the master.

Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

2. Write to the SPICR register:

Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when software
writes a byte in the SPIDR register.

10.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.

When data transfer is complete:

The SPIF bit is set by hardware

An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR
register is cleared.

Clearing the SPIF bit is performed by the following
software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.

10.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the
SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 51

Note: The slave must have the same CPOL

and CPHA settings as the master.

Manage the SS pin as described in

Section

10.4.3.2

and

Figure 49

. If CPHA=1 SS must

be held low continuously. If CPHA=0 SS must

be held low during byte transmission and

pulled up between each byte to let the slave

write in the shift register.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O
functions.

10.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.

The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.

When data transfer is complete:

The SPIF bit is set by hardware

An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is
cleared.

Clearing the SPIF bit is performed by the following
software sequence:

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.

The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see

Section 10.4.5.2

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See

Figure 51

Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).

The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge

Figure 51

, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.

Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.

Figure 51. Data Clock Timing Diagram

SCK

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPHA =1

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(to slave)

CAPTURE STROBE

CPHA =0

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.

(from slave)

(CPOL = 1)

SCK
(CPOL = 0)

SCK
(CPOL = 1)

SCK
(CPOL = 0)

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.5 Error Flags

10.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device
has its SS pin pulled low.

When a Master mode fault occurs:

The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-
eral.

The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software
sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.

Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.

10.4.5.2 Overrun Condition (OVR)

An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has

not cleared the SPIF bit issued from the previously
transmitted byte.

When an Overrun occurs:

The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.

The OVR bit is cleared by reading the SPICSR
register.

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.

Write collisions can occur both in master and slave
mode. See also

Section 10.4.3.2 Slave Select

Management

Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.

The WCOL bit in the SPICSR register is set if a
write collision occurs.

No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software
sequence (see

Figure 52

Figure 52. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SPICSR

Read SPIDR

2nd Step

SPIF =0
WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

Read SPICSR

Read SPIDR

Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit

RESULT

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.5.4 Single Master Systems

A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see

Figure 53

The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.

The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.

For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.

Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.

Figure 53. Single Master / Multiple Slave Configuration

MISO

MOSI

MISO

SCK

r
t
s

Slave

MCU

Slave

MCU

Slave
MCU

Master
MCU

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.6 Low Power Modes

10.4.6.1 Using the SPI to wakeup the MCU from
Halt mode

In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.

Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see

Section

10.4.3.2

), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

10.4.7 Interrupts

Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in

Mode Description

WAIT

No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.

HALT

SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with "exit from HALT mode" ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of Transfer
Event

SPIF

SPIE

Yes

Master Mode Fault
Event

MODF

Yes

Overrun Error

OVR

Yes

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SERIAL PERIPHERAL INTERFACE (Cont'd)

10.4.8 Register Description

CONTROL REGISTER (SPICR)

Read/Write

Reset Value: 0000 xxxx (0xh)

Bit 7 = SPIE

Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR
register

Bit 6 = SPE

Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see

Section 10.4.5.1 Master Mode Fault

(MODF)

). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the ex-
ternal pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2

Divider Enable

This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to

Table 18 SPI Master

mode SCK Frequency

0: Divider by 2 enabled
1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR

Master Mode.

This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see

Section 10.4.5.1 Master Mode Fault

(MODF)

0: Slave mode
1: Master mode. The function of the SCK pin

changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL

Clock Polarity.

This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.

Bit 2 = CPHA

Clock Phase.

This bit is set and cleared by software.
0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and
CPHA settings as the master.

Bits 1:0 = SPR[1:0]

Serial Clock Frequency.

These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.

Note: These 2 bits have no effect in slave mode.

Table 18. SPI Master mode SCK Frequency

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Serial Clock

SPR2

SPR1

SPR0

CPU

/16

CPU

/32

CPU

/64

CPU

/128

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SERIAL PERIPHERAL INTERFACE (Cont'd)

CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.

Bit 6 = WCOL

Write Collision status (Read only).

This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see

Figure 52

0: No write collision occurred
1: A write collision has been detected

Bit 5 = OVR S

PI Overrun error (Read only).

This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See

Section 10.4.5.2

). An interrupt is generated if

SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected

Bit 4 = MODF

Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is
pulled low in master mode (see

Section 10.4.5.1

Master Mode Fault (MODF)

). An SPI interrupt can

be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF=1 fol-
lowed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD

SPI Output Disable.

This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled

Bit 1 = SSM

SS Management.

This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See

Section

10.4.3.2 Slave Select Management

0: Hardware management (SS managed by exter-

nal pin)

1: Software management (internal SS signal con-

trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)

Bit 0 = SSI

SS Internal Mode.

This bit is set and cleared by software. It acts as a
`chip select' by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
1 : Slave deselected

DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined

The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.

Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.

While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.

Warning: A write to the SPIDR register places
data directly into the shift register for transmission.

A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see

Figure 47

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

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10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.5.1 Introduction

The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.

10.5.2 Main Features

Full duplex, asynchronous communications

NRZ standard format (Mark/Space)

Dual baud rate generator systems

Independently programmable transmit and
receive baud rates up to 500K baud.

Programmable data word length (8 or 9 bits)

Receive buffer full, Transmit buffer empty and
End of Transmission flags

Two receiver wake-up modes:

Address bit (MSB)

Idle line

Muting function for multiprocessor configurations

Separate enable bits for Transmitter and
Receiver

Four error detection flags:

Overrun error

Noise error

Frame error

Parity error

Five interrupt sources with flags:

Transmit data register empty

Transmission complete

Receive data register full

Idle line received

Overrun error detected

Parity control:

Transmits parity bit

Checks parity of received data byte

Reduced power consumption mode

10.5.3 General Description

The interface is externally connected to another
device by two pins (see

Figure 55

TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.

RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.

Through these pins, serial data is transmitted and
received as frames comprising:

An Idle Line prior to transmission or reception

A start bit

A data word (8 or 9 bits) least significant bit first

A Stop bit indicating that the frame is complete.

This interface uses two types of baud rate generator:

A conventional type for commonly-used baud

rates,

An extended type with a prescaler offering a very

wide range of baud rates even with non-standard
oscillator frequencies.

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

10.5.4 Functional Description

The block diagram of the Serial Control Interface,
is shown in

Figure 54

. It contains 6 dedicated reg-

isters:

Two control registers (SCICR1 & SCICR2)

A status register (SCISR)

A baud rate register (SCIBRR)

An extended prescaler receiver register (SCIER-

PR)

An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in

Section

10.5.7

for the definitions of each bit.

10.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see

Figure 54

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame
of "1"s followed by the start bit of the next frame
which contains data.

A Break character is interpreted on receiving "0"s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra "1" bit to acknowledge the start bit.

Transmission and reception are driven by their
own baud rate generator.

Figure 55. Word Length Programming

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Start

Bit

Stop

Bit

Start

Bit

Idle Frame

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Start

Bit

Stop

Bit

Next
Start

Bit

Start

Bit

Idle Frame

Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Frame

Start

Bit

Extra

'1'

Data Frame

Break Frame

Start

Bit

Extra

'1'

Data Frame

Next Data Frame

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

10.5.4.2 Transmitter

The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.

Character Transmission

During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see

Figure 54

Procedure

Select the M bit to define the word length.

Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first
transmission.

Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.

Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

The TDR register is empty.

The data transfer is beginning.

The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.

When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.

When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the
same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see

Figure 55

As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle
frame before the first data frame.

Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.

Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

10.5.4.3 Receiver

The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.

Character reception

During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see

Figure 54

Procedure

Select the M bit to define the word length.

Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The error flags can be set if a frame error, noise

or an overrun error has been detected during re-
ception.

Clearing the RDRF bit is performed by the following
software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.

Break Character

When a break character is received, the SPI han-
dles it as a framing error.

Idle Character

When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.

Overrun Error

An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
RDR register as long as the RDRF bit is not
cleared.

When a overrun error occurs:

The OR bit is set.

The RDR content will not be lost.

The shift register will be overwritten.

An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.

When noise is detected in a frame:

The NF is set at the rising edge of the RDRF bit.

Data is transferred from the Shift register to the

SCIDR register.

No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself
generates an interrupt.

The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.

Framing Error

A framing error is detected when:

The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-
zation or excessive noise.

A break is received.

When the framing error is detected:

the FE bit is set by hardware

Data is transferred from the Shift register to the

SCIDR register.

No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself
generates an interrupt.

The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

10.5.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:

with:

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT[2:0] bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If f

CPU

is 8 MHz (normal mode) and if

PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.

Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.

10.5.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.

The extended baud rate generator block diagram
is described in the

Figure 56

The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.

Note: the extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:

with:

ETPR = 1,..,255 (see SCIETPR register)

ERPR = 1,.. 255 (see SCIERPR register)

10.5.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.

The non addressed devices may be placed in
sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in
sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

A muted receiver may be awakened by one of the
following two ways:

by Idle Line detection if the WAKE bit is reset,

by Address Mark detection if the WAKE bit is set.

Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.

Receiver wakes-up by Address Mark detection
when it received a "1" as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.

Caution: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU=1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit will be set again by
this write operation. Consequently the address
byte is lost and the SCI is not woken up from Mute
mode.

Tx =

(16

PR)

CPU

Rx =

(16

PR)

CPU

Tx =

ETPR*(PR*TR)

CPU

Rx =

ERPR*(PR*RR)

CPU

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

10.5.4.7 Parity Control

Parity control (generation of parity bit in trasmis-
sion and and parity chencking in reception) can be
enabled by setting the PCE bit in the SCICR1 reg-
ister. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in

Table 20

Table 20. Frame Formats

Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit

Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit

Even parity: the parity bit is calculated to obtain
an even number of "1s" inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an
odd number of "1s" inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of "1s" if even parity is selected

(PS=0) or an odd number of "1s" if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.

10.5.5 Low Power Modes

10.5.6 Interrupts

The SCI interrupt events are connected to the
same interrupt vector.

These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).

M bit

PCE bit

SCI frame

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

Mode Description

WAIT

No effect on SCI.

SCI interrupts cause the device to exit
from Wait mode.

HALT

SCI registers are frozen.

In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Transmit Data Register
Empty

TDRE

TIE

Yes

Transmission Com-
plete

TCIE

Yes

Received Data Ready
to be Read

RDRF

RIE

Yes

Overrun Error Detected

Yes

Idle Line Detected

IDLE

ILIE

Yes

Parity Error

PIE

Yes

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

10.5.7 Register Description

STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE

Transmit data register empty.

This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register

Note: Data will not be transferred to the shift reg-
ister unless the TDRE bit is cleared.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete

Note: TC is not set after the transmission of a Pre-
amble or a Break.

Bit 5 = RDRF

Received data ready flag.

This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected

Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs).

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Overrun error
1: Overrun error is detected

Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
1: Noise is detected

Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected

Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.

Bit 0 = PE

Parity error.

This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error

TDRE

RDRF

IDLE

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

Bit 7 = R8

Receive data bit 8.

This bit is used to store the 9th bit of the received
word when M=1.

Bit 6 = T8

Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-
ted word when M=1.

Bit 5 = SCID

Disabled for low power consumption

When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled

Bit 4 = M

Word length.

This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data
transfer (both transmission and reception).

Bit 3 = WAKE

Wake-Up method.

This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark

Bit 2 = PCE

Parity control enable.

This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
0: Parity control disabled
1: Parity control enabled

Bit 1 = PS

Parity selection.

This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity

Bit 0 = PIE

Parity interrupt enable.

This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled.

SCID

WAKE

PCE

PIE

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

CONTROL REGISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00 h)

Bit 7 = TIE

Transmitter interrupt enable

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE

Transmission complete interrupt ena-

ble

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 5 = RIE

Receiver interrupt enable

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Bit 4 = ILIE

Idle line interrupt enable.

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 3 = TE

Transmitter enable.

This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled

Notes:

During transmission, a "0" pulse on the TE bit

("0" followed by "1") sends a preamble (idle line)
after the current word.

When TE is set there is a 1 bit-time delay before

the transmission starts.

Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).

Bit 2 = RE

Receiver enable.

This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a

start bit

Bit 1 = RWU

Receiver wake-up.

This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
wakeup by idle line detection.

Bit 0 = SBK

Send break.

This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted

Note: If the SBK bit is set to "1" and then to "0", the
transmitter will send a BREAK word at the end of
the current word.

TIE

TCIE

RIE

ILIE

RWU

SBK

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

DATA REGISTER (SCIDR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.

The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see

Figure 54

The RDR register provides the parallel interface
between the input shift register and the internal
bus (see

Figure 54

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 00 xx xxxx (xxh)

Bits 7:6= SCP[1:0]

First SCI Prescaler

These 2 prescaling bits allow several standard
clock division ranges:

Bits 5:3 = SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.

Bits 2:0 = SCR[2:0]

SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

SCP1

SCP0

SCT2

SCT1

SCT0

SCR2

SCR1

SCR0

PR Prescaling factor

SCP1

SCP0

TR dividing factor

SCT2

SCT1

SCT0

128

RR Dividing factor

SCR2

SCR1

SCR0

128

ST72324J/K

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)

Read/Write

Reset Value: 0000 0000 (00 h)

Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.

Bits 7:0 = ERPR[7:0]

8-bit Extended Receive

Prescaler Register.

The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see

Figure 56

) is divided by

the binary factor set in the SCIERPR register (in
the range 1 to 255).

The extended baud rate generator is not used af-
ter a reset.

EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)

Read/Write

Reset Value:0000 0000 (00h)

Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.

Bits 7:0 = ETPR[7:0]

8-bit Extended Transmit

Prescaler Register.

The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see

Figure 56

) is divided by

the binary factor set in the SCIETPR register (in
the range 1 to 255).

The extended baud rate generator is not used af-
ter a reset.

ERPR

ETPR

ST72324J/K

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10-BIT A/D CONVERTER (ADC) (Cont'd)

10.6.3 Functional Description

The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than V

AREF

(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).

If the input voltage (V

AIN

) is lower than V

SSA

(low-

level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.

The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.

AIN

is the maximum recommended impedance

for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.

10.6.3.1 A/D Converter Configuration

The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.

In the ADCCSR register:

Select the CS[3:0] bits to assign the analog

channel to convert.

10.6.3.2 Starting the Conversion

In the ADCCSR register:

Set the ADON bit to enable the A/D converter

and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.

When a conversion is complete:

The EOC bit is set by hardware.
The result is in the ADCDR registers.

A read to the ADCDRH resets the EOC bit.

To read the 10 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRL register

3. Read the ADCDRH register. This clears EOC

automatically.

Note: The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion re-
sult.

To read only 8 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRH register. This clears EOC

automatically.

10.6.3.3 Changing the conversion channel

The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.

10.6.4 Low Power Modes

Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.

10.6.5 Interrupts

None.

Mode Description

WAIT

No effect on A/D Converter

HALT

A/D Converter disabled.

After wakeup from Halt mode, the A/D
Converter requires a stabilization time
t

STAB

(see Electrical Characteristics)

before accurate conversions can be
performed.

ST72324J/K

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10-BIT A/D CONVERTER (ADC) (Cont'd)

10.6.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read /Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

Bit 7 = EOC

End of

Conversion

This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete

Bit 6 = SPEED

ADC clock selection

This bit is set and cleared by software.
0: f

ADC

= f

CPU

1: f

ADC

= f

CPU

Bit 5 = ADON

A/D Converter on

This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion

Bit 4 = Reserved. Must be kept cleared.

Bit 3:0 = CH[3:0]

Channel Selection

These bits are set and cleared by software. They
select the analog input to convert.

*The number of channels is device dependent. Refer to
the device pinout description.

DATA REGISTER (ADCDRH)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[9:2]

MSB of

Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0]

LSB of

Converted Analog Value

EOC

SPEED ADON

CH3

CH2

CH1

CH0

Channel Pin*

CH3

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

ST72324J/K

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11 INSTRUCTION SET

11.1 ST7 ADDRESSING MODES

The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:

The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do

so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:

Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.

Short addressing mode is less powerful because

it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and
short addressing modes.

Table 23. ST7 Addressing Mode Overview

Addressing Mode

Example

Inherent

nop

Immediate

ld A,#$55

Direct

ld A,$55

Indexed

ld A,($55,X)

Indirect

ld A,([$55],X)

Relative

jrne loop

Bit operation

bset byte,#5

Mode

Syntax

Destination

Pointer

Address

(Hex.)

Pointer Size

(Hex.)

Length
(Bytes)

Inherent

nop

+ 0

Immediate

ld A,#$55

+ 1

Short

Direct

ld A,$10

00..FF

+ 1

Long

Direct

ld A,$1000

0000..FFFF

+ 2

No Offset

Direct

Indexed

ld A,(X)

00..FF

+ 0

Short

Direct

Indexed

ld A,($10,X)

00..1FE

+ 1

Long

Direct

Indexed

ld A,($1000,X)

0000..FFFF

+ 2

Short

Indirect

ld A,[$10]

00..FF

byte

+ 2

Long

Indirect

ld A,[$10.w]

0000..FFFF

00..FF

word

+ 2

Short

Indirect

Indexed

ld A,([$10],X)

00..1FE

00..FF

byte

+ 2

Long

Indirect

Indexed

ld A,([$10.w],X)

0000..FFFF

00..FF

word

+ 2

Relative

Direct

jrne loop

PC+/-127

+ 1

Relative

Indirect

jrne [$10]

PC+/-127

00..FF

byte

+ 2

Bit

Direct

bset $10,#7

00..FF

+ 1

Bit

Indirect

bset [$10],#7

00..FF

byte

+ 2

Bit

Direct

Relative

btjt $10,#7,skip

00..FF

+ 2

Bit

Indirect

Relative

btjt [$10],#7,skip

00..FF

byte

+ 3

ST72324J/K

107/156

INSTRUCTION SET OVERVIEW (Cont'd)

11.1.1 Inherent

All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.

11.1.2 Immediate

Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.

11.1.3 Direct

In Direct instructions, the operands are referenced
by their memory address.

The direct addressing mode consists of two sub-
modes:

Direct (short)

The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.

Direct (long)

The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three
sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.

11.1.5 Indirect (Short, Long)

The required data byte to do the operation is found
by its memory address, located in memory (point-
er).

The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

Inherent Instruction

Function

NOP

No operation

TRAP

S/W Interrupt

WFI

Wait For Interrupt (Low Pow-
er Mode)

HALT

Halt Oscillator (Lowest Power
Mode)

RET

Sub-routine Return

IRET

Interrupt Sub-routine Return

SIM

Set Interrupt Mask (level 3)

RIM

Reset Interrupt Mask (level 0)

SCF

Set Carry Flag

RCF

Reset Carry Flag

RSP

Reset Stack Pointer

Load

CLR

Clear

PUSH/POP

Push/Pop to/from the stack

INC/DEC

Increment/Decrement

TNZ

Test Negative or Zero

CPL, NEG

1 or 2 Complement

MUL

Byte Multiplication

SLL, SRL, SRA, RLC,
RRC

Shift and Rotate Operations

SWAP

Swap Nibbles

Immediate Instruction

Function

Load

Compare

BCP

Bit Compare

AND, OR, XOR

Logical Operations

ADC, ADD, SUB, SBC

Arithmetic Operations

ST72324J/K

108/156

INSTRUCTION SET OVERVIEW (Cont'd)

11.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.

The indirect indexed addressing mode consists of
two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

Table 24. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes

11.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.

The relative addressing mode consists of two sub-
modes:

Relative (Direct)

The offset is following the opcode.

Relative (Indirect)

The offset is defined in memory, which address
follows the opcode.

Long and Short

Instructions

Function

Load

Compare

AND, OR, XOR

Logical Operations

ADC, ADD, SUB, SBC

Arithmetic Additions/Sub-
stractions operations

BCP

Bit Compare

Short Instructions

Only

Function

CLR

Clear

INC, DEC

Increment/Decrement

TNZ

Test Negative or Zero

CPL, NEG

1 or 2 Complement

BSET, BRES

Bit Operations

BTJT, BTJF

Bit Test and Jump Opera-
tions

SLL, SRL, SRA, RLC,
RRC

Shift and Rotate Opera-
tions

SWAP

Swap Nibbles

CALL, JP

Call or Jump subroutine

Available Relative

Direct/Indirect

Instructions

Function

JRxx

Conditional Jump

CALLR

Call Relative

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109/156

INSTRUCTION SET OVERVIEW (Cont'd)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in
the following table:

Using a pre-byte

The instructions are described with one to four op-
codes.

In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.

The whole instruction becomes:

PC-2

End of previous instruction

PC-1

Prebyte

opcode

PC+1

Additional word (0 to 2) according

to the number of bytes required to compute the ef-
fective address

These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:

PDY 90

Replace an X based instruction

using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.

PIX 92

Replace an instruction using di-

rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.

PIY 91

Replace an instruction using X in-

direct indexed addressing mode by a Y one.

Load and Transfer

CLR

Stack operation

PUSH

POP

RSP

Increment/Decrement

INC

DEC

Compare and Tests

TNZ

BCP

Logical operations

AND

XOR

CPL

NEG

Bit Operation

BSET

BRES

Conditional Bit Test and Branch

BTJT

BTJF

Arithmetic operations

ADC

ADD

SUB

SBC

MUL

Shift and Rotates

SLL

SRL

SRA

RLC

RRC

SWAP

SLA

Unconditional Jump or Call

JRA

JRT

JRF

CALL

CALLR

NOP

RET

Conditional Branch

JRxx

Interruption management

TRAP

WFI

HALT

IRET

Condition Code Flag modification

SIM

RIM

SCF

RCF

ST72324J/K

110/156

INSTRUCTION SET OVERVIEW (Cont'd)

Mnemo

Description

Function/Example

Dst

Src

ADC

Add with Carry

A = A + M + C

ADD

Addition

A = A + M

AND

Logical And

A = A . M

BCP

Bit compare A, Memory

tst (A . M)

BRES

Bit Reset

bres Byte, #3

BSET

Bit Set

bset Byte, #3

BTJF

Jump if bit is false (0)

btjf Byte, #3, Jmp1

BTJT

Jump if bit is true (1)

btjt Byte, #3, Jmp1

CALL

Call subroutine

CALLR

Call subroutine relative

CLR

Clear

reg, M

Arithmetic Compare

tst(Reg - M)

reg

CPL

One Complement

A = FFH-A

reg, M

DEC

Decrement

dec Y

reg, M

HALT

Halt

IRET

Interrupt routine return

Pop CC, A, X, PC

INC

Increment

inc X

reg, M

Absolute Jump

jp [TBL.w]

JRA

Jump relative always

JRT

Jump relative

JRF

Never jump

jrf *

JRIH

Jump if Port B INT pin = 1

(no Port B Interrupts)

JRIL

Jump if Port B INT pin = 0

(Port B interrupt)

JRH

Jump if H = 1

H = 1 ?

JRNH

Jump if H = 0

H = 0 ?

JRM

Jump if I1:0 = 11

I1:0 = 11 ?

JRNM

Jump if I1:0 <> 11

I1:0 <> 11 ?

JRMI

Jump if N = 1 (minus)

N = 1 ?

JRPL

Jump if N = 0 (plus)

N = 0 ?

JREQ

Jump if Z = 1 (equal)

Z = 1 ?

JRNE

Jump if Z = 0 (not equal)

Z = 0 ?

JRC

Jump if C = 1

C = 1 ?

JRNC

Jump if C = 0

C = 0 ?

JRULT

Jump if C = 1

Unsigned <

JRUGE

Jump if C = 0

Jmp if unsigned >=

JRUGT

Jump if (C + Z = 0)

Unsigned >

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INSTRUCTION SET OVERVIEW (Cont'd)

Mnemo

Description

Function/Example

Dst

Src

JRULE

Jump if (C + Z = 1)

Unsigned <=

Load

dst <= src

reg, M

M, reg

MUL

Multiply

X,A = X * A

A, X, Y

X, Y, A

NEG

Negate (2's compl)

neg $10

reg, M

NOP

No Operation

OR operation

A = A + M

POP

Pop from the Stack

pop reg

reg

pop CC

PUSH

Push onto the Stack

push Y

reg, CC

RCF

Reset carry flag

C = 0

RET

Subroutine Return

RIM

Enable Interrupts

I1:0 = 10 (level 0)

RLC

Rotate left true C

C <= A <= C

reg, M

RRC

Rotate right true C

C => A => C

reg, M

RSP

Reset Stack Pointer

S = Max allowed

SBC

Substract with Carry

A = A - M - C

SCF

Set carry flag

C = 1

SIM

Disable Interrupts

I1:0 = 11 (level 3)

SLA

Shift left Arithmetic

C <= A <= 0

reg, M

SLL

Shift left Logic

C <= A <= 0

reg, M

SRL

Shift right Logic

0 => A => C

reg, M

SRA

Shift right Arithmetic

A7 => A => C

reg, M

SUB

Substraction

A = A - M

SWAP

SWAP nibbles

A7-A4 <=> A3-A0

reg, M

TNZ

Test for Neg & Zero

tnz lbl1

TRAP

S/W trap

S/W interrupt

WFI

Wait for Interrupt

XOR

Exclusive OR

A = A XOR M

ST72324J/K

112/156

12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re-
ferred to V

12.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at T

=25°C

and T

max (given by the selected temperature

range).

Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3

12.1.2 Typical values

Unless otherwise specified, typical data are based
on T

=25°C, V

=5V. They are given only as de-

sign guidelines and are not tested.

Typical ADC accuracy values are determined by
characterization of a batch of samples from a
standard diffusion lot over the full temperature
range, where 95% of the devices have an error
less than or equal to the value indicated
(mean±2

)

12.1.3 Typical curves

Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.

12.1.4 Loading capacitor

The loading conditions used for pin parameter
measurement are shown in

Figure 58

Figure 58. Pin loading conditions

12.1.5 Pin input voltage

The input voltage measurement on a pin of the de-
vice is described in

Figure 59

Figure 59. Pin input voltage

ST7 PIN

ST72324J/K

113/156

12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as "absolute maxi-
mum ratings" may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-

tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.

12.2.1 Voltage Characteristics

12.2.2 Current Characteristics

Notes:
1. Directly connecting the RESET and I/O pins to V

or V

could damage the device if an unintentional internal reset

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k

for

RESET, 10k

for I/Os). For the same reason, unused I/O pins must not be directly tied to V

or V

2. When the current limitation is not possible, the V

absolute maximum rating must be respected, otherwise refer to

INJ(PIN)

specification. A positive injection is induced by V

while a negative injection is induced by V

3. All power (V

) and ground (V

) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. See note in

"ADC Accuracy" on page 143

For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum

INJ(PIN)

is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with

INJ(PIN)

maxi-

mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.

Symbol

Ratings

Maximum value

Unit

- V

Supply voltage

6.5

- V

Programming Voltage

1) & 2)

Input Voltage on true open drain pin

-0.3 to 6.5

Input voltage on any other pin

-0.3 to V

+0.3

DDx

| and |

SSx

Variations between different digital power pins

SSA

- V

SSx

Variations between digital and analog ground pins

ESD(HBM)

Electro-static discharge voltage (Human Body Model)

see

Section 12.7.3 on page 130

ESD(MM)

Electro-static discharge voltage (Machine Model)

Symbol

Ratings

Maximum value

Unit

VDD

Total current into V

power lines

(source)

32-pin devices

44-pin devices

150

VSS

Total current out of V

ground lines

(sink) for

32-pin devices

44-pin devices

150

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

- 25

INJ(PIN)

2) & 4)

Injected current on V

± 5

Injected current on RESET pin

± 5

Injected current on OSC1 and OSC2 pins

± 5

Injected current on any other pin

5) & 6)

± 5

INJ(PIN)

Total injected current (sum of all I/O and control pins)

± 25

ST72324J/K

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12.2.3 Thermal Characteristics

12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions (standard voltage ROM and Flash devices)

Figure 60. f

CPU

Max Versus V

for Standard Voltage Devices

Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-
dering Information .

Symbol

Ratings

Value

Unit

STG

Storage temperature range

-65 to +150

°C

Maximum junction temperature (see

Section 13.2 THERMAL CHARACTERISTICS

)

Symbol

Parameter

Conditions

Min

Max

Unit

CPU

Internal clock frequency

MHz

Standard voltage devices (except Flash
Write/Erase)

3.8

5.5

Operating Voltage for Flash Write/Erase

= 11.4 to 12.6V

4.5

5.5

Ambient temperature range

1 Suffix Version

°C

5 Suffix Version

-10

6 or A Suffix Versions

-40

7 or B Suffix Versions

-40

105

C Suffix Version

-40

125

CPU

[MHz]

SUPPLY VOLTAGE [V]

1
0

3.5

4.0

4.5

5.5

FUNCTIONALITY

FUNCTIONALITY
GUARANTEED
IN THIS AREA

NOT GUARANTEED

IN THIS AREA

3.8

IN STANDARD

DEVICES (UNLESS

VOLTAGE

OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA)

ST72324J/K

116/156

OPERATING CONDITIONS (Cont'd)

12.3.3 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for V

, f

CPU

, and T

Notes:
1. Data based on characterization results, not tested in production.
2. When Vt

POR

is faster than 100

s/V, the Reset signal is released after a delay of max. 42µs after V

crosses the

IT+(LVD)

threshold.

3. Applicable only in low voltage devices (planned).

Figure 62. LVD Startup Behaviour

Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.
However, in some devices, the reset state is released when V

is approximately between 0.8V and 1.5V.

As a consequence, depending on the ramp-up speed, the I/Os may toggle when V

is within this win-

dow.

This may be an issue especially for applications where the MCU drives power components.

Because Flash write access is impossible within this window, the Flash memory contents will not be cor-
rupted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

IT+(LVD)

Reset release threshold
(V

rise)

VD level = High in option byte

4.0

4.2

4.5

VD level = Med. in option byte

VD level = Low in option byte

3.55

2.95

3.75
3.15

4.0

3.35

IT-(LVD)

Reset generation threshold
(V

fall)

VD level = High in option byte

3.8

4.0

4.25

VD level = Med. in option byte

VD level = Low in option byte

3.35

2.8

3.55

3.0

3.75

3.15

hys(LVD)

LVD voltage threshold hysteresis

IT+(LVD)

-V

IT-(LVD)

150

200

250

POR

rise time

1)2)

s/V

g(VDD)

Filtered glitch delay on V

Not detected by the LVD

1.5V

IT+

0.8V

LVD RESET

Window

ST72324J/K

118/156

12.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).

12.4.1 RUN and SLOW Modes (Flash devices)

Figure 63. Typical I

in RUN vs. f

CPU

Figure 64. Typical I

in SLOW vs. f

CPU

Notes:
1. Data based on characterization results, tested in production at V

max. and f

CPU

max.

2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at V

or V

(no load)

- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, f

CPU

is based on f

OSC

divided by 32.

To obtain the total current consumption of the device, add the clock source (

Section 12.5.3

and

Section 12.5.4

) and the

peripheral power consumption (

Section 12.4.7

Symbol

Parameter

Conditions

Typ Max

Unit

Supply current in RUN mode

(see

Figure 63

)

3.8

5.5

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

1.3
2.0
3.6
7.1

3.0
5.0
8.0

15.0

Supply current in SLOW mode

(see

Figure 64

)

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.6
0.7
0.8
1.1

2.7
3.0
3.6
4.0

Supply current in RUN mode

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

0.8
1.2
2.0

TBD
TBD
TBD

Supply current in SLOW mode

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

0.33
0.37
0.44

TBD
TBD
TBD

3.2

3.6

4.4

4.8

5.2

5.5

Vdd (V)

I
dd (

)

8MHz
4MHz
2MHz
1MHz

0.00

0.20

0.40

0.60

0.80

1.00

1.20

3.2

3.6

4.4

4.8

5.2

5.5

Vdd (V)

I
dd (

)

500kHz

250kHz

125kHz

62.5kHz

ST72324J/K

119/156

SUPPLY CURRENT CHARACTERISTICS (Cont'd)

12.4.2 WAIT and SLOW WAIT Modes (Flash devices)

Figure 65. Typical I

in WAIT vs. f

CPU

Figure 66. Typical I

in SLOW-WAIT vs. f

CPU

Notes:
1. Data based on characterization results, tested in production at V

max. and f

CPU

max.

or V

(no load)

- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, f

CPU

is based on f

OSC

divided by 32.

To obtain the total current consumption of the device, add the clock source (

Section 12.5.3

and

Section 12.5.4

) and the

peripheral power consumption (

Section 12.4.7

Symbol

Parameter

Conditions

Typ Max

Unit

Supply current in WAIT mode

(see

Figure 65

)

3.8V

5.5V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

1.0
1.5
2.5
4.5

3.0
4.0
5.0
7.0

Supply current in SLOW WAIT mode

(see

Figure 66

)

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.58
0.65
0.77
1.05

1.2
1.3
1.8
2.0

Supply current in WAIT mode

3.6V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

0.6
0.8
1.6

TBD
TBD
TBD

Supply current in SLOW WAIT mode

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

0.33
0.37
0.44

TBD
TBD
TBD

3.2

3.6

4.4

4.8

5.2

5.5

Vdd (V)

I
dd (

)

8MHz
4MHz
2MHz
1MHz

0.00

0.20

0.40

0.60

0.80

1.00

1.20

3.2

3.6

4.4

4.8

5.2

5.5

Vdd (V)

()

500kHz

250kHz

125kHz

62.5kHz

ST72324J/K

120/156

SUPPLY CURRENT CHARACTERISTICS (Cont'd)

12.4.3 RUN and SLOW Modes (ROM devices)

12.4.4 WAIT and SLOW WAIT Modes (ROM devices)

Notes:
1. Data based on characterization results, tested in production at V

max. and f

CPU

max.

2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. There is no increase in consumption for if programs are

executed in ROM

- All I/O pins in input mode with a static value at V

or V

(no load)

- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, f

CPU

is based on f

OSC

divided by 32.

To obtain the total current consumption of the device, add the clock source (

Section 12.5.3

and

Section 12.5.4

) and the

peripheral power consumption (

Section 12.4.7

Symbol

Parameter

Conditions

Typ Max

Unit

Supply current in RUN mode

3.8V

5.5V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

1.3
2.0
3.6
7.1

2.0
3.0
5.0

10.0

Supply current in SLOW mode

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.6
0.7
0.8
1.1

1.8
2.1
2.4
3.0

Supply current in RUN mode

3.6V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

0.8
1.2
2.0

TBD
TBD
TBD

Supply current in SLOW mode

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

0.35

0.4
0.5

TBD
TBD
TBD

Symbol

Parameter

Conditions

Typ Max

Unit

Supply current in WAIT mode

3.8

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

1.0
1.5
2.5
4.5

1.3
2.0
3.3
6.0

Supply current in SLOW WAIT mode

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.07

0.1
0.2

0.35

0.2
0.3
0.6
1.2

Supply current in WAIT mode

.6V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

0.6
0.8
1.6

TBD
TBD
TBD

Supply current in SLOW WAIT mode

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

0.33
0.37
0.44

TBD
TBD
TBD

ST72324J/K

121/156

SUPPLY CURRENT CHARACTERISTICS (Cont'd)

12.4.5 HALT and ACTIVE-HALT Modes

Notes:
1. All I/O pins in push-pull 0 mode (when applicable) with a static value at V

or V

(no load), CSS and LVD disabled.

Data based on characterization results, tested in production at V

max. and f

CPU

max.

2. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at V

or V

(no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the

total current consumption of the device, add the clock source consumption (

Section 12.5.3

and

Section 12.5.4

12.4.6 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode).

Notes:
1. Data based on characterisation results, not tested in production.
2. Data based on characterization results done with the external components specified in

Section 12.5.3

and

Section

12.5.4

, not tested in production.

3. As the oscillator is based on a current source, the consumption does not depend on the voltage.

Symbol

Parameter

Conditions

Typ

Max

Unit

Supply current in HALT mode

=5.5V

-40°C

+85°C

-40°C

+125°C

Supply current in ACTIVE-HALT mode

OSC

= 16 MHz, V

= 5V

650

No max.

guaran-

teed

Symbol

Parameter

Conditions

Typ

Max

Unit

DD(RCINT)

Supply current of internal RC oscillator

625

DD(RCEXT)

Supply current of external RC oscillator

see

Section

12.5.4 on page

126

DD(RES)

Supply current of resonator oscillator

2) & 3)

see

Section

12.5.3 on page

124

DD(PLL)

PLL supply current

= 5V

360

DD(CSS)

Clock security system supply current

= 5V

250

DD(LVD)

LVD supply current

HALT mode, V

= 5V

150

300

ST72324J/K

123/156

12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V

, f

CPU

, and T

12.5.1 General Timings

12.5.2 External Clock Source

Figure 67. Typical Application with an External Clock Source

Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch.

c(INST)

is the number of t

CPU

cycles needed to finish

the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

c(INST)

Instruction cycle time

CPU

=8MHz

250

375

1500

v(IT)

Interrupt reaction time

v(IT)

c(INST)

+ 10

CPU

=8MHz

1.25

2.75

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

OSC1H

OSC1 input pin high level voltage

see

Figure 67

-1

OSC1L

OSC1 input pin low level voltage

w(OSC1H)

w(OSC1L)

OSC1 high or low time

r(OSC1)

f(OSC1)

OSC1 rise or fall time

OSCx Input leakage current

±1

OSC1

OSC2

OSC

EXTERNAL

ST72XXX

CLOCK SOURCE

Not connected internally

OSC1L

OSC1H

r(OSC1)

f(OSC1)

w(OSC1H)

w(OSC1L)

90%

10%

ST72324J/K

124/156

CLOCK AND TIMING CHARACTERISTICS (Cont'd)

12.5.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as

close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).

Figure 68. Typical Application with a Crystal or Ceramic Resonator

Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value.

Refer to crystal/ceramic resonator manufacturer for more details.

Symbol

Parameter

Conditions

Min

Max

Unit

OSC

Oscillator Frequency

LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator

>2
>4
>8

2
4
8

MHz

Feedback resistor

Recommended load capacitance ver-
sus equivalent serial resistance of the
crystal or ceramic resonator (R

)

=200

LP oscillator

=200

MP oscillator

=200

MS oscillator

=100

HS oscillator

22
22
18
15

56
46
33
33

Symbol

Parameter

Conditions

Typ

Max

Unit

OSC2 driving current

=5V

LP oscillator

MP oscillator
MS oscillator
HS oscillator

160
310
610

150
250
460
910

OSC2

OSC1

OSC

ST72XXX

RESONATOR

WHEN RESONATOR WITH
INTEGRATED CAPACITORS

ST72324J/K

126/156

CLOCK CHARACTERISTICS (Cont'd)

12.5.4 RC Oscillators

The ST7 internal clock can be supplied with an RC
oscillator. This oscillator can be used with internal

or external components (selectable by option
byte).

Figure 69. Typical Application with RC oscillator

Notes:
1. Data based on design simulation.
2. R

must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.

3. i

CEX

is the current needed to load the C

capacitor while OSC1 is forced to V

or 1.5V (RC oscillation voltage range).

Figure 70. Typical f

OSC(RCINT)

vs V

Figure 71. Typical f

OSC(RCINT)

vs T

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

OSC (RCINT)

Internal RC oscillator frequency

See

Figure 70

and

Figure 71

=25°C, V

=5V

3.5

5.6

MHz

OSC(RCEXT)

External RC oscillator frequency

5 / (R

)

Oscillator external resistor

100

Oscillator external capacitor

470

CEX

Capacitor load current

OSC1 = V

or 1.5V

290

350

OSC2

OSC1

OSC

EXTERNAL RC

INTERNAL RC

REF

Current copy

Voltage generator

discharge

ST72XXX

CEX

0.5

1.5

2.5

3.5

4.5

2.35

5.5

(V)

RCI

)

TA=-45C

TA=25C

TA=130C

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

-45

130

(°C)

RCI

)

Vdd = 2.4V

Vdd = 5V

ST72324J/K

127/156

CLOCK CHARACTERISTICS (Cont'd)

12.5.5 Clock Security System (CSS)

Note:
1. Data based on characterization results.

12.5.6 PLL Characteristics

Operating conditions: V

3.8 to 5.5V @ T

0 to 70°C

or V

4.5 to 5.5V @ T

-40 to 125°C

Note:
1. Data characterized but not tested.

Figure 72. PLL Jitter vs. Signal frequency

The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore the longer the
period of the application signal, the less it will be
impacted by the PLL jitter.

Figure 72

shows the PLL jitter integrated on appli-

cation signals in the range 125kHz to 2MHz. At fre-
quencies of less than 125KHz, the jitter is negligi-
ble.

Note 1: Measurement conditions: f

CPU

= 4MHz, T

= 25°C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SFOSC

Safe Oscillator Frequency

MHz

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DD(PLL)

PLL Operating Range

0 to 70

°C

3.8

5.5

-40 to +125

°C

4.5

5.5

OSC

PLL input frequency range

MHz

CPU

Instantaneous PLL jitter

OSC

= 4 MHz.

1.0

2.5

OSC

= 2 MHz.

2.5

4.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

2000

1000

500

250

125

Application Signal Frequency (KHz)

/
-Ji

t
t
e

r (%

)

PLL ON

PLL OFF

ST72324J/K

128/156

12.6 MEMORY CHARACTERISTICS

12.6.1 RAM and Hardware Registers

12.6.2 FLASH Memory

Notes:
1. Minimum V

supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-

isters (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. V

must be applied only during the programming or erasing operation and not permanently for reliability reasons.

4. Data based on simulation results, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Data retention mode

HALT mode (or RESET)

1.6

DUAL VOLTAGE HDFLASH MEMORY

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CPU

Operating frequency

Read mode

MHz

Write / Erase mode

Programming voltage

4.5V

5.5V

11.4

12.6

Supply current

RUN mode (f

CPU

= 4MHz)

Write / Erase

Power down mode / HALT

µA

current

Read (V

=12V)

200

Write / Erase

VPP

Internal

stabilization time

µs

RET

Data retention

=55°C

years

Write erase cycles

=25°C

100

cycles

PROG

ERASE

Programming or erasing tempera-
ture range

-40

°C

ST72324J/K

129/156

12.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba-
sis during product characterization.

12.7.1 Functional EMS

(Electro Magnetic Susceptibility)

Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).

ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.

FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V

and V

through

a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.

A device reset allows normal operations to be re-
sumed.

12.7.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.

Notes:
1. Data based on characterization results, not tested in production.

Symbol

Parameter

Conditions

Neg

Pos

Unit

FESD

Voltage limits to be applied on any I/O pin
to induce a functional disturbance

5V, T

+25°C, f

OSC

8MHz

conforms to IEC 1000-4-2

-1

1.5

FFTB

Fast transient voltage burst limits to be ap-
plied through 100pF on V

and V

pins

to induce a functional disturbance

5V, T

+25°C, f

OSC

8MHz

conforms to IEC 1000-4-4

-1.5

1.5

Symbol

Parameter

Conditions

Monitored

Frequency Band

Max vs. [f

OSC

CPU

]

Unit

8/4MHz

16/8MHz

EMI

Peak level

5V, T

+25°C,

TQFP44 package
conforming to SAE J 1752/3

0.1MHz to 30MHz

30MHz to 130MHz

130MHz to 1GHz

SAE EMI Level

3.0

3.5

ST72324J/K

130/156

EMC CHARACTERISTICS (Cont'd)

12.7.3 Absolute Electrical Sensitivity

Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.

12.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See

Figure 73

and the following test sequences.

Human Body Model Test Sequence

is loaded through S1 by the HV pulse gener-

ator.

S1 switches position from generator to R.

A discharge from C

through R (body resistance)

to the ST7 occurs.

S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.

Machine Model Test Sequence

is loaded through S1 by the HV pulse gener-

ator.

S1 switches position from generator to ST7.

A discharge from C

to the ST7 occurs.

S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.

R (machine resistance), in series with S2, en-

sures a slow discharge of the ST7.

Absolute Maximum Ratings

Figure 73. Typical Equivalent ESD Circuits

Notes:
1. Data based on characterization results, not tested in production.

Symbol

Ratings

Conditions

Maximum value

Unit

ESD(HBM)

Electro-static discharge voltage
(Human Body Model)

+25°C

2000

ESD(MM)

Electro-static discharge voltage
(Machine Model)

+25°C

200

ST7

R=1500

HIGH VOLTAGE

100pF

PULSE

GENERATOR

ST7

HIGH VOLTAGE

200pF

PULSE

GENERATOR

10
k

10M

HUMAN BODY MODEL

MACHINE MODEL

ST72324J/K

131/156

EMC CHARACTERISTICS (Cont'd)

12.7.3.2 Static and Dynamic Latch-Up

LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the AN1181 ST7
application note.

DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in

Figure 74

. For

more details, refer to the AN1181 ST7
application note.

12.7.3.3 Designing hardened software to avoid
noise problems

EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It

should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.

Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.

Software recommendations:

The software flowchart must include the manage-
ment of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).

Electrical Sensitivities

Figure 74. Simplified Diagram of the ESD Generator for DLU

Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.

Symbol

Parameter

Conditions

Class

Static latch-up class

+25°C

+85°C

+125°C

A
A
A

DLU

Dynamic latch-up class

5.5V, f

OSC

4MHz, T

+25°C

=50M

=330

150pF

ESD

HV RELAY

DISCHARGE TIP

DISCHARGE
RETURN CONNECTION

GENERATOR

ST7

ST72324J/K

132/156

EMC CHARACTERISTICS (Cont'd)

12.7.4 ESD Pin Protection Strategy

To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.

An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in

Figure 75

and

Figure 76

for standard

pins and in

Figure 77

and

Figure 78

for true open

drain pins.

Standard Pin Protection

To protect the output structure the following ele-
ments are added:

A diode to V

(3a) and a diode from V

(3b)

A protection device between V

and V

(4)

To protect the input structure the following ele-
ments are added:

A resistor in series with the pad (1)
A diode to V

(2a) and a diode from V

(2b)

A protection device between V

and V

(4)

Figure 75. Positive Stress on a Standard Pad vs. V

Figure 76. Negative Stress on a Standard Pad vs. V

(1)

(2a)

(2b)

(4)

OUT

(3a)

(3b)

Main path

Path to avoid

(1)

(2a)

(2b)

(4)

OUT

(3a)

(3b)

Main path

ST72324J/K

134/156

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Figure 80. Connecting Unused I/O Pins

Figure 81. Typical I

vs. V

with V

Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V

maximum must be respected, otherwise refer to I

INJ(PIN)

specifica-

tion. A positive injection is induced by V

while a negative injection is induced by V

. Refer to

Section 12.2.2

on page 113

for more details.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see

Figure 80

). Data based on design simulation and/or technology

characteristics, not tested in production.
5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

current characteristics de-

scribed in

Figure 81

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input low level voltage

CMOS ports

0.3xV

Input high level voltage

0.7xV

hys

Schmitt trigger voltage hysteresis

0.7

Input low level voltage

TTL ports

0.8

Input high level voltage

hys

Schmitt trigger voltage hysteresis

INJ(PIN)

Injected Current on an I/O pin

=5V

± 4

INJ(PIN)

Total injected current (sum of all I/O
and control pins)

± 25

Input leakage current

±1

Static current consumption

Floating input mode

200

Weak pull-up equivalent resistor

=5V

120

250

I/O pin capacitance

f(IO)out

Output high to low level fall time

=50pF

Between 10% and 90%

r(IO)out

Output low to high level rise time

w(IT)in

External interrupt pulse time

CPU

10k

UNUSED I/O PORT

ST72XXX

10k

UNUSED I/O PORT

ST72XXX

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

2.5

3 .5

4.5

5.5

Vdd (V)

I
p

)

Ta=1 40°C

Ta=9 5°C

Ta=2 5°C

Ta=-45 °C

ST72324J/K

135/156

I/O PORT PIN CHARACTERISTICS (Cont'd)

12.8.2 Output Driving Current

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Figure 82. Typical V

at V

=5V (standard)

Figure 83. Typical V

at V

=5V (high-sink)

Figure 84. Typical V

at V

=5V

Notes:
1. The I

current sunk must always respect the absolute maximum rating specified in

Section 12.2.2

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. The I

current sourced must always respect the absolute maximum rating specified in

Section 12.2.2

and the sum of

(I/O ports and control pins) must not exceed I

VDD

. True open drain I/O pins do not have V

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see

Figure 82

)

=+5mA

1.2

=+2mA

0.5

Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see

Figure 83

and

Figure 85

)

=+20mA,T

85°C

1.3
1.5

=+8mA

0.6

Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see

Figure 84

and

Figure 87

)

=-5mA, T

85°C

-1.4

-1.6

=-2mA

-0.7

0.2

0.4

0.6

0.8

1.2

1.4

0 .005

0.01

0.015

Iio(A )

l (V

) at

Ta =14 0°C "

Ta =95 °C

Ta =25 °C

Ta =-45 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.01

0.02

0.03

Iio(A)

l
(
V)

t
Vd

Ta= 140 °C

Ta= 95 °C

Ta= 25 °C

Ta= -45°C

2.5

3.5

4.5

5.5

-0.01

-0.008

-0.006

-0.004

-0.002

Iio (A)

(

)
a

t
Vd

V dd= 5V 1 40°C m in

V dd= 5v 95°C m in

V dd= 5v 25°C m in

V dd= 5v -4 5°C m i n

ST72324J/K

136/156

I/O PORT PIN CHARACTERISTICS (Cont'd)

Figure 85. Typical V

vs. V

(standard)

Figure 86. Typical V

vs. V

(high-sink)

Figure 87. Typical V

-V

vs. V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

2.5

3.5

4.5

5.5

Vd d(V )

l
(
V

)
a

t
I

i
o

Ta= -4 5°C

Ta= 25°C

Ta= 95°C

Ta= 140 °C

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

2 .5

3.5

4.5

5.5

Vd d(V )

l
(
V

)
at

I
i
o

Ta=-4 5°C

Ta=2 5°C

Ta=9 5°C

Ta=1 40°C

0 .1

0 .2

0 .3

0 .4

0 .5

0 .6

2.5

3.5

4.5

5.5

Vdd (V )

l
(
V

)
at

I
i
o=

Ta= 14 0°C

Ta= 9 5°C

Ta= 2 5°C

Ta= -45 °C

0 .2

0 .4

0 .6

0 .8

1 .2

1 .4

1 .6

2.5

3.5

4.5

5.5

V dd(V )

l
(
V

)
at

I
i
o=

Ta= 140 °C

Ta= 95 °C

Ta= 25 °C

Ta= -45°C

2.5

3.5

4.5

5.5

Vdd(V)

-
V

(
V)

t

I
i
o

-
5

Ta= -4 5°C

Ta= 25°C

Ta= 95°C

Ta= 140°C

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

Vdd(V)

Voh

(
V

)
a

t
I

i
o

-
2

Ta= -4 5°C

Ta= 25°C

Ta= 95°C

Ta= 140°C

ST72324J/K

137/156

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Figure 88. Typical Application with RESET pin

6)7)8)

Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I

current sunk must always respect the absolute maximum rating specified in

Section 12.2.2

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t

h(RSTL)in

can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V

max. level specified in

Section 12.9.1

. Otherwise the reset will not be taken into account internally.

8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I

INJ(RESET)

Section 12.2.2 on page 113

9. Data guaranteed by design, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input low level voltage

0.16xV

Input high level voltage

0.85xV

hys

Schmitt trigger voltage hysteresis

2.5

Output low level voltage

=5V

=+5mA

0.5

1.2

=+2mA

0.2

0.5

Input current on RESET pin

TBD

Weak pull-up equivalent resistor

120

w(RSTL)out

Generated reset pulse duration

External pin

Internal reset sources

h(RSTL)in

External reset pulse hold time

2.5

g(RSTL)in

Filtered glitch duration

200

0.01

EXTERNAL

RESET

CIRCUIT

USER

4.7k

Required if LVD is disabled

Recommended

if LVD is disabled

ST72XXX

PULSE

GENERATOR

Filter

WATCHDOG

LVD RESET

INTERNAL

RESET

ST72324J/K

138/156

CONTROL PIN CHARACTERISTICS (Cont'd)

12.9.2 ICCSEL/V

Pin

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Figure 89. Two typical Applications with ICCSEL/V

Pin

Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/V

pin must be tied to V

12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).

12.10.1 16-Bit Timer

Symbol

Parameter

Conditions

Min

Max

Unit

Input low level voltage

FLASH versions

0.2

ROM versions

0.3xV

Input high level voltage

FLASH versions

-0.1

12.6

ROM versions

0.7xV

Input leakage current

±1

ICCSEL/V

ST72XXX

10k

PROGRAMMING

TOOL

ST72XXX

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

w(ICAP)in

Input capture pulse time

CPU

res(PWM)

PWM resolution time

CPU

=8MHz

250

EXT

Timer external clock frequency

CPU

MHz

PWM

PWM repetition rate

CPU

MHz

Res

PWM

PWM resolution

bit

ST72324J/K

139/156

12.11 COMMUNICATION INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for V

CPU

, and T

unless otherwise specified.

Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).

Figure 90. SPI Slave Timing Diagram with CPHA=0

Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV

and 0.7xV

Symbol

Parameter

Conditions

Min

Max

Unit

SCK

1/t

c(SCK)

SPI clock frequency

Master

CPU

=8MHz

CPU

/128

0.0625

CPU

MHz

Slave

CPU

=8MHz

CPU

r(SCK)

f(SCK)

SPI clock rise and fall time

see I/O port pin description

su(SS)

SS setup time

Slave

120

h(SS)

SS hold time

Slave

120

w(SCKH)

w(SCKL)

SCK high and low time

Master
Slave

100

su(MI)

su(SI)

Data input setup time

Master
Slave

100
100

h(MI)

h(SI)

Data input hold time

Master
Slave

100
100

a(SO)

Data output access time

Slave

120

dis(SO)

Data output disable time

Slave

240

v(SO)

Data output valid time

Slave (after enable edge)

h(SO)

Data output hold time

v(MO)

Data output valid time

Master (before capture edge)

0.25

CPU

h(MO)

Data output hold time

0.25

INPUT

INP

CPHA=0

MOSI

INPUT

MISO

OUTPUT

CPHA=0

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

v(SO)

a(SO)

su(SI)

h(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

see note 2

CPOL=0

CPOL=1

su(SS)

h(SS)

dis(SO)

h(SO)

see

note 2

BIT1 IN

ST72324J/K

141/156

12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Figure 93. R

AIN

max. vs f

ADC

with C

AIN

=0pF

Figure 94. Recommended C

AIN

& R

AIN values.

Figure 95. Typical A/D Converter Application

Notes:
1. Unless otherwise specified, typical data are based on T

=25°C and V

-V

=5V. They are given only as design guide-

lines and are not tested.
2. When V

DDA

and V

SSA

pins are not available on the pinout, the ADC refers to V

and V

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

). Data

based on characterization results, not tested in production.
4. C

PARASITIC

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high C

PARASITIC

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

5. This graph shows that depending on the input signal variation (f

AIN

), C

AIN

can be increased for stabilization and to allow

the use of a larger serial resistor (R

AIN)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ADC

ADC clock frequency

0.4

MHz

AREF

Analog reference voltage

0.7*V

5.5

AIN

Conversion voltage range

SSA

AREF

Input leakage current
for analog input

-40°C

85°C range

±250

Other T

ranges

±1

AIN

External input impedance

see

Figure 93

and

Figure

3)4)5)

AIN

External capacitor on analog input

AIN

Variation freq. of analog input signal

ADC

Internal sample and hold capacitor

STAB

Stabilization time after ADC enable

CPU

=8MHz, SPEED=0

ADC

=2MHz

ADC

Conversion time (Sample+Hold)

7.5

- No of sample capacitor loading cycles
- No. of Hold conversion cycles

1/f

ADC

PARASITIC

(pF)

Max

.
R

(

ohm)

2 MHz

1 MHz

0.1

100

1000

0.01

0.1

AIN

(KHz)

Max

.
R

(

ohm)

Cain 10 nF

Cain 22 nF

Cain 47 nF

AINx

ST72XXX

±1

0.6V

ADC

6pF

AIN

10-Bit A/D
Conversion

(

max

)

AIN

ST72324J/K

142/156

ADC CHARACTERISTICS (Cont'd)

12.12.0.1 Analog Power Supply and Reference
Pins

Depending on the MCU pin count, the package
may feature separate V

AREF

and V

SSA

analog

power supply pins. These pins supply power to the
A/D converter cell and function as the high and low
reference voltages for the conversion. In smaller
packages V

AREF

and V

SSA

pins are not available

and the analog supply and reference pads are

in-

ternally

bonded to the V

and V

pins.

Separation of the digital and analog power pins al-
low board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see

Section

12.12.0.2 General PCB Design Guidelines

12.12.0.2 General PCB Design Guidelines

To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.

Use separate digital and analog planes. The an-

alog ground plane should be connected to the

digital ground plane via a single point on the
PCB.

Filter power to the analog power planes. It is rec-

ommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines,

placing 0.1µF and optionally, if

needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF ca-
pacitor close to the power source (see

Figure

The analog and digital power supplies should be

connected in a star nework. Do not use a resis-
tor, as V

AREF

used as a reference voltage by

the A/D converter and

any resistance would

cause a voltage drop and a loss of accuracy.

Properly place components and route the signal

traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.

Figure 96. Power Supply Filtering

0.1

10pF

ST72XXX

AREF

SSA

POWER
SUPPLY
SOURCE

ST7
DIGITAL NOISE
FILTERING

EXTERNAL
NOISE
FILTERING

1 to 10

0.1

10pF

(if needed)

ST72324J/K

143/156

10-BIT ADC CHARACTERISTICS (Cont'd)

12.12.1 ADC Accuracy

Conditions: V

=5V

Notes:
1. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for I

INJ(PIN)

and

INJ(PIN)

Section 12.8

does not affect the ADC

accuracy.
2. Data based on characterization results, monitored in production.

Figure 97. ADC Accuracy Characteristics

Symbol

Parameter

Conditions

Typ

Max

Unit

Total unadjusted error

LSB

Offset error

3.5

Gain Error

-0.5

-2

Differential linearity error

CPU in run mode @ f

ADC

2 MHz.

1.5

4.5

Integral linearity error

CPU in run mode @ f

ADC

2 MHz.

1.5

4.5

1 LSB

IDEAL

1LSB

IDEAL

A REF

SS A

1024

--------------------------------------------

(LSB

IDEAL

)

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.
E

=Offset Error: deviation between the first actual

transition and the first ideal one.
E

=Gain Error: deviation between the last ideal

transition and the last actual one.
E

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.
E

=Integral Linearity Error: maximum deviation

between any actual transition and the end point
correlation line.

Digital Result ADCDR

1023

1022

1021

1021 1022 1023 1024

(1)

(2)

(3)

AREF

SSA

ST72324J/K

145/156

PACKAGE MECHANICAL DATA (Cont'd)

Figure 100. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width

Figure 101. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width

Dim.

inches

Min

Typ

Max

Min

Typ

Max

5.08

0.200

0.51

0.020

3.05

3.81

4.57 0.120 0.150 0.180

0.38

0.46

0.56 0.015 0.018 0.022

0.89

1.02

1.14 0.035 0.040 0.045

0.23

0.25

0.38 0.009 0.010 0.015

36.58 36.83 37.08 1.440 1.450 1.460

15.24

16.00 0.600

0.630

12.70 13.72 14.48 0.500 0.540 0.570

1.78

0.070

15.24

0.600

18.54

0.730

1.52 0.000

0.060

2.54

3.30

3.56 0.100 0.130 0.140

Number of Pins

0.015

GAGE PLANE

Dim.

inches

Min

Typ

Max

Min

Typ

Max

3.56

3.76

5.08 0.140 0.148 0.200

0.51

0.020

3.05

3.56

4.57 0.120 0.140 0.180

0.36

0.46

0.58 0.014 0.018 0.023

0.76

1.02

1.40 0.030 0.040 0.055

0.20

0.25

0.36 0.008 0.010 0.014

27.43

28.45 1.080 1.100 1.120

9.91 10.41 11.05 0.390 0.410 0.435

7.62

8.89

9.40 0.300 0.350 0.370

1.78

0.070

10.16

0.400

12.70

0.500

1.40

0.055

2.54

3.05

3.81 0.100 0.120 0.150

Number of Pins

eA
eB

ST72324J/K

148/156

14 ST72324J/K DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). FLASH devices are
shipped to customers with a default content (FFh),
while ROM factory coded parts contain the code

supplied by the customer. This implies that FLASH
devices have to be configured by the customer us-
ing the Option Bytes while the ROM devices are
factory-configured.

14.1 FLASH OPTION BYTES

The option bytes allows the hardware configura-
tion of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The de-
fault content of the FLASH is fixed to FFh. To pro-
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the
internal RC clock source. In masked ROM devic-
es, the option bytes are fixed in hardware by the
ROM code (see option list).

OPTION BYTE 0

OPT7= WDG HALT

Watchdog and HALT mode

This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode

OPT6= WDG SW

Hardware or software watchdog

This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)

OPT5 = CSS

Clock security system on/off

This option bit enables or disables the clock secu-
rity system function (CSS) which include the clock

filter and the backup safe oscillator.
0: CSS enabled
1: CSS disabled

OPT4:3= VD[1:0]

Voltage detection

These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+IVD).

OPT0= FMP_R

Flash memory read-out protection

This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
induce the whole user memory erasing first.
0: read-out protection enabled
1: read-out protection disabled

STATIC OPTION BYTE 0

STATIC OPTION BYTE 1

WDG

P_R

KG1

STC

OSCTYPE

OSCRANGE

LOFF

HAL

Default

Selected Low Voltage Detector

VD1

VD0

LVD and AVD Off

Lowest Voltage Threshold (V

~3V)

Medium Voltage Threshold (V

~3.5V)

Highest Voltage Threshold (V

~4V)

ST72324J/K

149/156

ST72324J/K DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd)

OPTION BYTE 1

OPT7= PKG1

Pin package selection bit

This option bit selects the package.

Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.

OPT6 = RSTC

RESET clock cycle selection

This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
Note: when the CSS is enabled, the device starts
to count immediately thanks to the backup oscilla-
tor.

OPT5:4 = OSCTYPE[1:0]

Oscillator Type

These option bits select the ST7 main clock
source type.

OPT3:1 = OSCRANGE[2:0]

Oscillator range

When the resonator oscillator type is selected,
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits

are used to select the normal operating frequency
range.

OPT0 = PLL OFF

PLL activation

This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL must not be used with the internal RC os-
cillator. The PLL is guaranteed only with an input
frequency between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
"OSC RANGE" (OPT3:1) bits are configured to
"MP - 2~4MHz". Otherwise, the device functionali-
ty is not guaranteed.

Version

Selected Package

PKG1

TQFP44 / SDIP42

TQFP32 / SDIP32

Clock Source

OSCTYPE

Resonator Oscillator

External RC Oscillator

Internal RC Oscillator

External Source

Typ. Freq. Range

OSCRANGE

1~2MHz

2~4MHz

4~8MHz

8~16MHz

ST72324J/K

150/156

ST72324J/K DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd)

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.

The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.

The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.

Figure 104. ROM Factory Coded Device Types

Table 25. Orderable Flash Device Types

Part Number

Program

Memory

(Bytes)

Temp. Range

Package

ST72F324J6T6

32KB FLASH

-40°C +85°C

TQFP44

ST72F324J4T6

16KB FLASH

ST72F324J2T6

8KB FLASH

ST72F324J6B6

32KB FLASH

SDIP42

ST72F324J4B6

16KB FLASH

ST72F324J2B6

8KB FLASH

ST72F324J6TC

32KB FLASH

-40°C +125°C

TQFP44

ST72F324K6T6

32KB FLASH

-40°C +85°C

TQFP32

ST72F324K4T6

16KB FLASH

ST72F324K2T6

8KB FLASH

ST72F324K6B6

32KB FLASH

SDIP32

ST72F324K4B6

16KB FLASH

ST72F324K2B6

8KB FLASH

ST72F324K6TC

32KB FLASH

-40°C +125°C

TQFP32

DEVICE PACKAGE

TEMP.

RANGE

XXX

Code name (defined by STMicroelectronics)

1= 0 to +70 °C
5= -10 to +85 °C
6= -40 to +85 °C
C = -40 to +125 °C

T= Plastic Thin Quad Flat Pack
B= Plastic Dual in Line

ST72324J6, ST72324J4, ST72324J2
ST72324K6, ST72324K4, ST72324K2

ST72324J/K

151/156

ST72324J/K DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd)

ST72324 MICROCONTROLLER OPTION LIST

Customer:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . .
*The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.

Device Type/Memory Size/Package (check only one option):

Conditioning (check only one option):

Temp. Range (do not check for die product:

Special Marking:

[ ] No

[ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Clock Source Selection:

[ ] Resonator:

[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)

[ ] RC Network:

[ ] Internal
[ ] External

[ ] External Clock

PLL

[ ] Disabled

[ ] Enabled

Clock Security System:

[ ] Disabled

[ ] Enabled

LVD Reset

[ ] Disabled

[ ] Enabled:

[ ] Highest threshold

Reset Delay

[ ] 256 Cycles

[ ] 4096 Cycles

Watchdog Selection:

[ ] Software Activation

[ ] Hardware Activation

Halt when Watchdog on:

[ ] Reset

[ ] No reset

Readout Protection:

[ ] Disabled

[ ] Enabled

Date

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL must not be enabled if internal RC Network is selected

---------------------------------

ROM DEVICE:

---------------------------------

|
|

--------------------------------------

32K

--------------------------------------

|
|

--------------------------------------

16K

--------------------------------------

-----------------------------------

TQFP32:

[ ] ST72324K6T

[ ] ST72324K4T

[ ] ST72324K2T

DIP32:

[ ] ST72324K6B

[ ] ST72324K4B

[ ] ST72324K2B

TQFP44 :

[ ] ST72324J6T

[ ] ST72324J4T

[ ] ST72324J2T

DIP42:

[ ] ST72324J6B

[ ] ST72324J4B

[ ] ST72324J2B

---------------------------------

DIE FORM:

---------------------------------

|
|

---------------------------------------

32K

---------------------------------------

|
|

---------------------------------------

16K

---------------------------------------

-----------------------------------

------------------------------------

32-pin:

[ ]

44-pin:

[ ]

------------------------------------------------------------------------

Packaged Product

------------------------------------------------------------------------

-----------------------------------------------------

Die Product (dice tested at 25°C only)

-----------------------------------------------------

[ ] Tape & Reel

[ ] Tray

[ ] Tape & Reel

[ ] Inked wafer

[ ] Sawn wafer on sticky foil

[ ] 0°C to +70°C

[ ] -10°C to +85°C

[ ] -40°C to +105°C

[ ] -40°C to +85°C

[ ] -40°C to +125°C

ST72324J/K

152/156

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd)

14.3 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:

http//mcu.st.com.

Tools from these manufacturers include C compli-
ers, emulators and gang programmers.

ST Emulators

The emulator is delivered with everything (probes,
TEB, adapters etc.) needed to start emulating the
devices. To configure the emulator to emulate dif-
ferent ST7 subfamily devices, the active probe for
the ST7 EMU3 can be changed and the ST7EMU3
probe is designed for easy interchange of TEBs

(Target Emulation Board). See

Table 26

for more

details.

14.3.1 Socket and Emulator Adapter
Information

For information on the type of socket that is sup-
plied with the emulator, refer to the suggested list
of sockets in

Table 27

Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.

For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer's datasheet (www.yamaichi.de for
TQFP44 10 x 10 and www.ironwoodelectron-
ics.com for TQFP32 7 x 7).

Table 26. STMicroelectronics Development Tools

Note:
1. Flash Programming interface for FLASH devices.

Table 27. Suggested List of Socket Types

Supported Products

ST7 Evaluation

Board

ST7 HDS2

Emulator

Active Probe &

T.E.B.

ST7 Programming Board

ST72324J, ST72F324J

ST72324K, ST72F324K

N/A

ST7MDT20J-

EMU3

ST7MDT20J-TEB

ST7MDT20J-EPB/EU

ST7MDT20J-EPB/US

ST7MDT20J-EPB/UK

Device

Socket (supplied with

ST7MDT20J-EMU3)

Emulator Adapter (supplied with

ST7MDT20J-EMU3)

TQFP32 7 X 7

IRONWOOD SF-QFE32SA-L-01

IRONWOOD SK-UGA06/32A-01

TQFP44 10 X10

YAMAICHI IC149-044-*52-*5

YAMAICHI ICP-044-5

ST72324J/K

153/156

14.4 ST7 APPLICATION NOTES

IDENTIFICATION

DESCRIPTION

EXAMPLE DRIVERS

AN 969

SCI COMMUNICATION BETWEEN ST7 AND PC

AN 970

SPI COMMUNICATION BETWEEN ST7 AND EEPROM

AN 971

I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM

AN 972

ST7 SOFTWARE SPI MASTER COMMUNICATION

AN 973

SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

AN 974

REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE

AN 976

DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION

AN 979

DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

AN 980

ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

AN1017

USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER

AN1041

USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSO

AN1042

ST7 ROUTINE FOR IÝC SLAVE MODE MANAGEMENT

AN1044

MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

AN1045

ST7 S/W IMPLEMENTATION OF IÝC BUS MASTER

AN1046

UART EMULATION SOFTWARE

AN1047

MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS

AN1048

ST7 SOFTWARE LCD DRIVER

AN1078

PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE

AN1082

DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS

AN1083

ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE

AN1105

ST7 PCAN PERIPHERAL DRIVER

AN1129

PERMANENT MAGNET DC MOTOR DRIVE.

AN1130

AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141

AN1148

USING THE ST7263 FOR DESIGNING A USB MOUSE

AN1149

HANDLING SUSPEND MODE ON A USB MOUSE

AN1180

USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD

AN1276

BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER

AN1321

USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE

AN1325

USING THE ST7 USB LOW-SPEED FIRMWARE V4.X

AN1445

USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE

AN1475

DEVELOPING AN ST7265X MASS STORAGE APPLICATION

AN1504

STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER

PRODUCT EVALUATION

AN 910

PERFORMANCE BENCHMARKING

AN 990

ST7 BENEFITS VERSUS INDUSTRY STANDARD

AN1077

OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS

AN1086

U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING

AN1150

BENCHMARK ST72 VS PC16

AN1151

PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876

AN1278

LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS

PRODUCT MIGRATION

AN1131

MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324

AN1322

MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B

AN1365

GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264

PRODUCT OPTIMIZATION

ST72324J/K

154/156

14.5 TO GET MORE INFORMATION

To get the latest information on this product please use the ST web server: http://mcu.st.com/

AN 982

USING ST7 WITH CERAMIC RENATOR

AN1014

HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

AN1015

SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE

AN1040

MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES

AN1070

ST7 CHECKSUM SELF-CHECKING CAPABILITY

AN1324

CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS

AN1477

EMULATED DATA EEPROM WITH XFLASH MEMORY

AN1502

EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY

AN1530

ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR

PROGRAMMING AND TOOLS

AN 978

KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE

AN 983

KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE

AN 985

EXECUTING CODE IN ST7 RAM

AN 986

USING THE INDIRECT ADDRESSING MODE WITH ST7

AN 987

ST7 SERIAL TEST CONTROLLER PROGRAMMING

AN 988

STARTING WITH ST7 ASSEMBLY TOOL CHAIN

AN 989

GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN

AN1039

ST7 MATH UTILITY ROUTINES

AN1064

WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7

AN1071

HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER

AN1106

TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

AN1179

PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)

AN1446

USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION

AN1478

PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE

AN1527

DEVELOPING A USB SMARTCARD READER WITH ST7SCR

AN1575

ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS

IDENTIFICATION

DESCRIPTION

ST72324J/K

156/156

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I

C Components by STMicroelectronics conveys a license under the Philips I

C Patent. Rights to use these components in an

C system is granted provided that the system conforms to the I

C Standard Specification as defined by Philips.

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