Электронный компонент: ST72521BR6

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Rev. 1.1

October 2003

1/198

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

ST72521B

80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM,

FIVE TIMERS, SPI, SCI, I

2

C, CAN INTERFACE

PRELIMINARY DATA

s

Memories

� 32K to 60K ROM with read-out protection ca-

pability

� 1K to 2K RAM

s

Clock, Reset And Supply Management

� Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

� Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator, clock security

system and bypass for external clock

� PLL for 2x frequency multiplication
� Four power saving modes: Halt, Active-Halt,

Wait and Slow

s

Interrupt Management

� Nested interrupt controller
� 14 interrupt vectors plus TRAP and RESET
� Top Level Interrupt (TLI) pin
� 15 external interrupt lines (on 4 vectors)

s

Up to 64 I/O Ports

� 48 multifunctional bidirectional I/O lines
� 34 alternate function lines
� 16 high sink outputs

s

5 Timers

� Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

� Configurable watchdog timer
� Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and pulse generator modes

� 8-bit PWM Auto-Reload timer with: 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

event detector

s

4 Communications Interfaces

� SPI synchronous serial interface
� SCI asynchronous serial interface (LIN com-

patible)

� I

2

C multimaster interface

� CAN interface (2.0B Passive)

s

Analog peripheral (low current coupling)

� 10-bit ADC with 16 robust input ports

s

Instruction Set

� 8-bit Data Manipulation
� 63 Basic Instructions
� 17 main Addressing Modes
� 8 x 8 Unsigned Multiply Instruction

s

Development Tools

� Full hardware/software development package
� In-Circuit Testing capability

Device Summary

TQFP80

14 x 14

TQFP64

10 x 10

TQFP64

14 x 14

Features

ST72521B(M/R/AR)9

ST72521B(R/AR)6

ROM - bytes

60K

32K

RAM (stack) - bytes

2048 (256)

1024 (256)

Operating Voltage

3.8V to 5.5V

Temp. Range

up to -40�C to +125�C

Package

TQFP80 14x14 (M),

TQFP64 14x14 (R), TQFP64

10x10 (AR)

TQFP64 14x14 (R), TQFP64 10x10 (AR)

1

Table of Contents

198

2/198

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

4.3

CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1

PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2

MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3

RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.2

Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.3

External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3.4

Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3.5

Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4

SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.1

Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.2

Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4.3

Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4.4

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4.5

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2

MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3

INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.4

CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.5

INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.6

EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.6.1

I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.7

EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 37

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2

SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3

WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4

ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.1

ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.2

HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.1

Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.2

Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.3

Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2

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8.3

I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.4

LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.5

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.5.1

I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1

WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1.4

How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1.5

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.1.6

Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.1.7

Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 53

9.1.8

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.1.9

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 55

9.2.1

Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2.2

Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2.3

Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2.4

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2.5

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2.6

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2.7

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3

PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.3.2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.3.3

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.4

16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.4.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.4.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.4.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.4.4

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.4.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.4.6

Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.4.7

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.5

SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.5.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.5.3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.5.4

Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

9.5.5

Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.5.6

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.5.7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.5.8

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

9.6

SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.6.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.6.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

1

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9.6.3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.6.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.6.5

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.6.6

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.6.7

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

9.7

I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.7.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.7.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.7.3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.7.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

9.7.5

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.7.6

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.7.7

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.8

CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.8.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.8.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.8.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.8.4

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.8.5

List of CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.9

10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.9.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.9.2

Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.9.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.9.4

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.9.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.9.6

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

11.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

11.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
11.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
11.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

1

Table of Contents

198

5/198

11.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

11.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

11.4 LVD/AVD CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.4.1 Low Voltage Detector (LVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.4.2 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.4.3 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.5 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.5.1 CURRENTCONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.5.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.5.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.6 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

11.6.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.6.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.6.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.6.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11.6.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.6.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.7.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

11.8.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.8.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.8.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.8.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

11.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

11.9.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.9.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.10 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

11.10.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

11.11 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.11.18-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11.11.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.12 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 177

11.12.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.12.2CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
11.12.3I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

11.13 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.13.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.13.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.13.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

13 ST72521B CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . 188

13.1 DEVICE OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

13.1.1 WDG HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

1

Document Outline

• 1 INTRODUCTION 7
• 2 PIN DESCRIPTION 8
• 3 REGISTER & MEMORY MAP 14
• 4 CENTRAL PROCESSING UNIT 18
  • 4.1 INTRODUCTION 18
  • 4.2 MAIN FEATURES 18
  • 4.3 CPU REGISTERS 18
• 5 SUPPLY, RESET AND CLOCK MANAGEMENT 21
  • 5.1 PHASE LOCKED LOOP 21
  • 5.2 MULTI-OSCILLATOR (MO) 22
  • 5.3 RESET SEQUENCE MANAGER (RSM) 23
  • 5.3.1 Introduction 23
  • 5.3.2 Asynchronous External RESET pin 23
  • 5.3.3 External Power-On RESET 24
  • 5.3.4 Internal Low Voltage Detector (LVD) RESET 24
  • 5.3.5 Internal Watchdog RESET 24
    • 5.4 SYSTEM INTEGRITY MANAGEMENT (SI) 25
  • 5.4.1 Low Voltage Detector (LVD) 25
  • 5.4.2 Auxiliary Voltage Detector (AVD) 26
  • 5.4.3 Clock Security System (CSS) 28
  • 5.4.4 Low Power Modes 28
  • 5.4.5 Register Description 29
• 6 INTERRUPTS 30
  • 6.1 INTRODUCTION 30
  • 6.2 Masking and Processing Flow 30
  • 6.3 Interrupts and Low Power Modes 32
  • 6.4 Concurrent & Nested Management 32
  • 6.5 Interrupt Register Description 33
  • 6.6 EXTERNAL INTERRUPTS 35
  • 6.6.1 I/O Port Interrupt Sensitivity 35
    • 6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) 37
• 7 POWER SAVING MODES 39
  • 7.1 INTRODUCTION 39
  • 7.2 SLOW MODE 39
  • 7.3 WAIT MODE 40
  • 7.4 ACTIVE-HALT AND HALT MODES 41
  • 7.4.1 ACTIVE-HALT MODE 41
  • 7.4.2 HALT MODE 42
• 8 I/O PORTS 44
  • 8.1 INTRODUCTION 44
  • 8.2 FUNCTIONAL DESCRIPTION 44
  • 8.2.1 Input Modes 44
  • 8.2.2 Output Modes 44
  • 8.2.3 Alternate Functions 44
    • 8.3 I/O PORT IMPLEMENTATION 47
    • 8.4 LOW POWER MODES 47
    • 8.5 INTERRUPTS 47
  • 8.5.1 I/O Port Implementation 48
• 9 ON-CHIP PERIPHERALS 50
  • 9.1 WATCHDOG TIMER (WDG) 50
  • 9.1.1 Introduction 50
  • 9.1.2 Main Features 50
  • 9.1.3 Functional Description 50
  • 9.1.4 How to Program the Watchdog Timeout 51
  • 9.1.5 Low Power Modes 53
  • 9.1.6 Hardware Watchdog Option 53
  • 9.1.7 Using Halt Mode with the WDG (WDGHALT option) 53
  • 9.1.8 Interrupts 53
  • 9.1.9 Register Description 53
    • 9.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) 55
  • 9.2.1 Programmable CPU Clock Prescaler 55
  • 9.2.2 Clock-out Capability 55
  • 9.2.3 Real Time Clock Timer (RTC) 55
  • 9.2.4 Beeper 55
  • 9.2.5 Low Power Modes 56
  • 9.2.6 Interrupts 56
  • 9.2.7 Register Description 56
    • 9.3 PWM AUTO-RELOAD TIMER (ART) 58
  • 9.3.1 Introduction 58
  • 9.3.2 Functional Description 59
  • 9.3.3 Register Description 63
    • 9.4 16-BIT TIMER 67
  • 9.4.1 Introduction 67
  • 9.4.2 Main Features 67
  • 9.4.3 Functional Description 67
  • 9.4.4 Low Power Modes 79
  • 9.4.5 Interrupts 79
  • 9.4.6 Summary of Timer modes 79
  • 9.4.7 Register Description 80
    • 9.5 SERIAL PERIPHERAL INTERFACE (SPI) 86
  • 9.5.1 Introduction 86
  • 9.5.2 Main Features 86
  • 9.5.3 General Description 86
  • 9.5.4 Clock Phase and Clock Polarity 90
  • 9.5.5 Error Flags 91
  • 9.5.6 Low Power Modes 93
  • 9.5.7 Interrupts 93
  • 9.5.8 Register Description 94
    • 9.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 97
  • 9.6.1 Introduction 97
  • 9.6.2 Main Features 97
  • 9.6.3 General Description 97
  • 9.6.4 Functional Description 99
  • 9.6.5 Low Power Modes 105
  • 9.6.6 Interrupts 105
  • 9.6.7 Register Description 106
    • 9.7 I2C BUS INTERFACE (I2C) 112
  • 9.7.1 Introduction 112
  • 9.7.2 Main Features 112
  • 9.7.3 General Description 112
  • 9.7.4 Functional Description 114
  • 9.7.5 Low Power Modes 118
  • 9.7.6 Interrupts 118
  • 9.7.7 Register Description 119
    • 9.8 CONTROLLER AREA NETWORK (CAN) 125
  • 9.8.1 Introduction 125
  • 9.8.2 Main Features 126
  • 9.8.3 Functional Description 126
  • 9.8.4 Register Description 132
  • 9.8.5 List of CAN Cell Limitations 142
    • 9.9 10-BIT A/D CONVERTER (ADC) 143
  • 9.9.1 Introduction 143
  • 9.9.2 Main Features 143
  • 9.9.3 Functional Description 144
  • 9.9.4 Low Power Modes 144
  • 9.9.5 Interrupts 144
  • 9.9.6 Register Description 145
• 10 INSTRUCTION SET 147
  • 10.1 CPU ADDRESSING MODES 147
  • 10.1.1 Inherent 148
  • 10.1.2 Immediate 148
  • 10.1.3 Direct 148
  • 10.1.4 Indexed (No Offset, Short, Long) 148
  • 10.1.5 Indirect (Short, Long) 148
  • 10.1.6 Indirect Indexed (Short, Long) 149
  • 10.1.7 Relative mode (Direct, Indirect) 149
    • 10.2 INSTRUCTION GROUPS 150
• 11 ELECTRICAL CHARACTERISTICS 153
  • 11.1 PARAMETER CONDITIONS 153
  • 11.1.1 Minimum and Maximum values 153
  • 11.1.2 Typical values 153
  • 11.1.3 Typical curves 153
  • 11.1.4 Loading capacitor 153
  • 11.1.5 Pin input voltage 153
    • 11.2 ABSOLUTE MAXIMUM RATINGS 154
  • 11.2.1 Voltage Characteristics 154
  • 11.2.2 Current Characteristics 154
  • 11.2.3 Thermal Characteristics 155
    • 11.3 OPERATING CONDITIONS 155
  • 11.3.1 Operating Conditions 155
    • 11.4 LVD/AVD CHARACTERISTICS 156
  • 11.4.1 Low Voltage Detector (LVD) thresholds 156
  • 11.4.2 Auxiliary Voltage Detector (AVD) Thresholds 156
  • 11.4.3 External Voltage Detector (EVD) Thresholds 156
    • 11.5 SUPPLY CURRENT CHARACTERISTICS 157
  • 11.5.1 CURRENTCONSUMPTION 157
  • 11.5.2 Supply and Clock Managers 159
  • 11.5.3 On-Chip Peripherals 160
    • 11.6 CLOCK AND TIMING CHARACTERISTICS 161
  • 11.6.1 General Timings 161
  • 11.6.2 External Clock Source 161
  • 11.6.3 Crystal and Ceramic Resonator Oscillators 162
  • 11.6.4 RC Oscillators 164
  • 11.6.5 Clock Security System (CSS) 165
  • 11.6.6 PLL Characteristics 165
    • 11.7 MEMORY CHARACTERISTICS 166
  • 11.7.1 RAM and Hardware Registers 166
    • 11.8 EMC CHARACTERISTICS 167
  • 11.8.1 Functional EMS 167
  • 11.8.2 Electro Magnetic Interference (EMI) 167
  • 11.8.3 Absolute Electrical Sensitivity 168
  • 11.8.4 ESD Pin Protection Strategy 170
    • 11.9 I/O PORT PIN CHARACTERISTICS 172
  • 11.9.1 General Characteristics 172
  • 11.9.2 Output Driving Current 173
    • 11.10 CONTROL PIN CHARACTERISTICS 175
  • 11.10.1 Asynchronous RESET Pin 175
    • 11.11 TIMER PERIPHERAL CHARACTERISTICS 176
  • 11.11.1 8-Bit PWM-ART Auto-Reload Timer 176
  • 11.11.2 16-Bit Timer 176
    • 11.12 COMMUNICATION INTERFACE CHARACTERISTICS 177
  • 11.12.1 SPI - Serial Peripheral Interface 177
  • 11.12.2 CAN - Controller Area Network Interface 179
  • 11.12.3 I2C - Inter IC Control Interface 180
    • 11.13 10-BIT ADC CHARACTERISTICS 181
  • 11.13.1 Analog Power Supply and Reference Pins 183
  • 11.13.2 General PCB Design Guidelines 183
  • 11.13.3 ADC Accuracy 184
• 12 PACKAGE CHARACTERISTICS 185
  • 12.1 PACKAGE MECHANICAL DATA 185
  • 12.2 THERMAL CHARACTERISTICS 186
  • 12.3 SOLDERING AND GLUEABILITY INFORMATION 187
• 13 ST72521B CONFIGURATION AND ORDERING INFORMATION 188
  • 13.1 DEVICE OPTION BYTES 188
  • 13.1.1 WDG HALT 188
  • 13.1.2 WDG SW 188
  • 13.1.3 CSS 188
  • 13.1.4 LVD 188
  • 13.1.5 RMP_R 188
  • 13.1.6 PKG 188
  • 13.1.7 RSTC 188
  • 13.1.8 OSCTYPE 188
  • 13.1.9 OSCRANGE 189
  • 13.1.10 PLL OFF 189
    • 13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 189
  • 13.2.1 Version-Specific Sales Conditions 191
    • 13.3 DEVELOPMENT TOOLS 191
  • 13.3.1 Socket and Emulator Adapter Information 191
    • 13.4 ST7 APPLICATION NOTES 192
• 14 KNOWN LIMITATIONS 196
  • 14.1 External RC option 196
  • 14.2 CSS Function 196
  • 14.3 Safe Connection of OSC1/OSC2 Pins 196
  • 14.4 Unexpected Reset Fetch 196
  • 14.5 16-bit Timer PWM Mode 196
  • 14.6 CAN Cell Limitations 196
• 15 SUMMARY OF CHANGES 197
  • ST72521B
• 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• 1 INTRODUCTION
  • Figure 1. Device Block Diagram
• 2 PIN DESCRIPTION
  • Figure 2. 80-Pin TQFP 14x14 Package Pinout
  • PIN DESCRIPTION (Cont�d)
    • Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout
  • PIN DESCRIPTION (Cont�d)
    • Table 1. Device Pin Description
• 3 REGISTER & MEMORY MAP
  • Figure 4. Memory Map
    • Table 2. Hardware Register Map
• 4 CENTRAL PROCESSING UNIT
  • 4.1 INTRODUCTION
  • 4.2 MAIN FEATURES
  • 4.3 CPU REGISTERS
    • Figure 5 . CPU Registers
  • CENTRAL PROCESSING UNIT (Cont�d)
  • CENTRAL PROCESSING UNIT (Cont�d)
    • Figure 6 . Stack Manipulation Example
• 5 SUPPLY, RESET AND CLOCK MANAGEMENT
  • 5.1 PHASE LOCKED LOOP
    • Figure 7. PLL Block Diagram
    • Figure 8. Clock, Reset and Supply Block Diagram
  • 5.2 MULTI-OSCILLATOR (MO)
    • Table 3. ST7 Clock Sources
  • 5.3 RESET SEQUENCE MANAGER (RSM)
    • 5.3.1 Introduction
    • Figure 9. RESET Sequence Phases
      • 5.3.2 Asynchronous External RESET pin
    • Figure 10. Reset Block Diagram
  • RESET SEQUENCE MANAGER (Cont�d)
    • 5.3.3 External Power-On RESET
    • 5.3.4 Internal Low Voltage Detector (LVD) RESET
    • 5.3.5 Internal Watchdog RESET
    • Figure 11. RESET Sequences
    • 5.4 SYSTEM INTEGRITY MANAGEMENT (SI)
      • 5.4.1 Low Voltage Detector (LVD)
      • Figure 12. Low Voltage Detector vs Reset
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 5.4.2 Auxiliary Voltage Detector (AVD)
      • 5.4.2.1 Monitoring the VDD Main Supply
    • Figure 13. Using the AVD to Monitor VDD (AVDS bit=0)
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 5.4.2.2 Monitoring a Voltage on the EVD pin
    • Figure 14. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 5.4.3 Clock Security System (CSS)
      • 5.4.3.1 Clock Filter Control
      • 5.4.3.2 Clock detection Control
    • 5.4.4 Low Power Modes
      • 5.4.4.1 Interrupts
    • Figure 15. Clock Filter Function
  • SYSTEM INTEGRITY MANAGEMENT (Cont�d)
    • 5.4.5 Register Description
• 6 INTERRUPTS
  • 6.1 INTRODUCTION
  • 6.2 Masking and Processing Flow
    • Table 4. Interrupt Software Priority Levels
    • Figure 16 . Interrupt Processing Flowchart
  • INTERRUPTS (Cont�d)
    • Figure 17 . Priority Decision Process
  • INTERRUPTS (Cont�d)
    • 6.3 Interrupts and Low Power Modes
    • 6.4 Concurrent & Nested Management
      • Figure 18 . Concurrent Interrupt Management
      • Figure 19 . Nested Interrupt Management
  • INTERRUPTS (Cont�d)
    • 6.5 Interrupt Register Description
  • INTERRUPTS (Cont�d)
    • Table 5. Dedicated Interrupt Instruction Set
  • INTERRUPTS (Cont�d)
    • Table 6. Interrupt Mapping
    • 6.6 EXTERNAL INTERRUPTS
      • 6.6.1 I/O Port Interrupt Sensitivity
      • Figure 20. External Interrupt Control bits
  • INTERRUPTS (Cont�d)
    • 6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
  • INTERRUPTS (Cont�d)
    • Table 7. Nested Interrupts Register Map and Reset Values
• 7 POWER SAVING MODES
  • 7.1 INTRODUCTION
    • Figure 21. Power Saving Mode Transitions
  • 7.2 SLOW MODE
    • Figure 22. SLOW Mode Clock Transitions
  • POWER SAVING MODES (Cont�d)
    • 7.3 WAIT MODE
      • Figure 23. WAIT Mode Flow-chart
  • POWER SAVING MODES (Cont�d)
    • 7.4 ACTIVE-HALT AND HALT MODES
      • 7.4.1 ACTIVE-HALT MODE
      • Figure 24. ACTIVE-HALT Timing Overview
      • Figure 25. ACTIVE-HALT Mode Flow-chart
  • POWER SAVING MODES (Cont�d)
    • 7.4.2 HALT MODE
    • Figure 26. HALT Timing Overview
    • Figure 27. HALT Mode Flow-chart
  • POWER SAVING MODES (Cont�d)
    • 7.4.2.1 Halt Mode Recommendations
• 8 I/O PORTS
  • 8.1 INTRODUCTION
  • 8.2 FUNCTIONAL DESCRIPTION
    • 8.2.1 Input Modes
    • 8.2.2 Output Modes
    • 8.2.3 Alternate Functions
  • I/O PORTS (Cont�d)
    • Figure 28. I/O Port General Block Diagram
      • Table 8. I/O Port Mode Options
  • I/O PORTS (Cont�d)
    • Table 9. I/O Port Configurations
  • I/O PORTS (Cont�d)
    • 8.3 I/O PORT IMPLEMENTATION
      • Figure 29. Interrupt I/O Port State Transitions
    • 8.4 LOW POWER MODES
    • 8.5 INTERRUPTS
  • I/O PORTS (Cont�d)
    • 8.5.1 I/O Port Implementation
      • Table 10. Port Configuration
  • I/O PORTS (Cont�d)
    • Table 11. I/O Port Register Map and Reset Values
• 9 ON-CHIP PERIPHERALS
  • 9.1 WATCHDOG TIMER (WDG)
    • 9.1.1 Introduction
    • 9.1.2 Main Features
    • 9.1.3 Functional Description
    • Figure 30 . Watchdog Block Diagram
  • WATCHDOG TIMER (Cont�d)
    • 9.1.4 How to Program the Watchdog Timeout
    • Figure 31 . Approximate Timeout Duration
  • WATCHDOG TIMER (Cont�d)
    • Figure 32 . Exact Timeout Duration (tmin and tmax)
  • WATCHDOG TIMER (Cont�d)
    • 9.1.5 Low Power Modes
    • 9.1.6 Hardware Watchdog Option
    • 9.1.7 Using Halt Mode with the WDG (WDGHALT option)
    • 9.1.8 Interrupts
    • 9.1.9 Register Description
      • Table 12. Watchdog Timer Register Map and Reset Values
    • 9.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
      • 9.2.1 Programmable CPU Clock Prescaler
      • 9.2.2 Clock-out Capability
      • 9.2.3 Real Time Clock Timer (RTC)
      • 9.2.4 Beeper
      • Figure 33. Main Clock Controller (MCC/RTC) Block Diagram
  • MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont�d)
    • 9.2.5 Low Power Modes
    • 9.2.6 Interrupts
    • 9.2.7 Register Description
  • MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont�d)
    • Table 13. Main Clock Controller Register Map and Reset Values
    • 9.3 PWM AUTO-RELOAD TIMER (ART)
      • 9.3.1 Introduction
      • Figure 34. PWM Auto-Reload Timer Block Diagram
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • 9.3.2 Functional Description
    • Figure 35. Output compare control
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Figure 36. PWM Auto-reload Timer Function
    • Figure 37. PWM Signal from 0% to 100% Duty Cycle
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Figure 38. External Event Detector Example (3 counts)
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Figure 39. Input Capture Timing Diagram
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • 9.3.3 Register Description
  • PWM AUTO-RELOAD TIMER (Cont�d)
  • PWM AUTO-RELOAD TIMER (Cont�d)
  • PWM AUTO-RELOAD TIMER (Cont�d)
    • Table 14. PWM Auto-Reload Timer Register Map and Reset Values
    • 9.4 16-BIT TIMER
      • 9.4.1 Introduction
      • 9.4.2 Main Features
      • 9.4.3 Functional Description
        • 9.4.3.1 Counter
  • 16-BIT TIMER (Cont�d)
    • Figure 40. Timer Block Diagram
  • 16-BIT TIMER (Cont�d)
    • 9.4.3.2 External Clock
  • 16-BIT TIMER (Cont�d)
    • Figure 41. Counter Timing Diagram, internal clock divided by 2
    • Figure 42. Counter Timing Diagram, internal clock divided by 4
    • Figure 43. Counter Timing Diagram, internal clock divided by 8
  • 16-BIT TIMER (Cont�d)
    • 9.4.3.3 Input Capture
  • 16-BIT TIMER (Cont�d)
    • Figure 44. Input Capture Block Diagram
    • Figure 45. Input Capture Timing Diagram
  • 16-BIT TIMER (Cont�d)
    • 9.4.3.4 Output Compare
  • 16-BIT TIMER (Cont�d)
    • Figure 46. Output Compare Block Diagram
  • 16-BIT TIMER (Cont�d)
    • Figure 47. Output Compare Timing Diagram, fTIMER =fCPU/2
    • Figure 48. Output Compare Timing Diagram, fTIMER =fCPU/4
  • 16-BIT TIMER (Cont�d)
    • 9.4.3.5 One Pulse Mode
  • 16-BIT TIMER (Cont�d)
    • Figure 49. One Pulse Mode Timing Example
    • Figure 50. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
  • 16-BIT TIMER (Cont�d)
    • 9.4.3.6 Pulse Width Modulation Mode
  • 16-BIT TIMER (Cont�d)
    • 9.4.4 Low Power Modes
    • 9.4.5 Interrupts
    • 9.4.6 Summary of Timer modes
  • 16-BIT TIMER (Cont�d)
    • 9.4.7 Register Description
  • 16-BIT TIMER (Cont�d)
    • Table 15. Clock Control Bits
  • 16-BIT TIMER (Cont�d)
  • CONTROL/STATUS REGISTER (CSR)
  • 16-BIT TIMER (Cont�d)
  • 16-BIT TIMER (Cont�d)
  • 16-BIT TIMER (Cont�d)
    • Table 16. 16-Bit Timer Register Map and Reset Values
    • 9.5 SERIAL PERIPHERAL INTERFACE (SPI)
      • 9.5.1 Introduction
      • 9.5.2 Main Features
      • 9.5.3 General Description
      • Figure 51. Serial Peripheral Interface Block Diagram
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.3.1 Functional Description
    • Figure 52. Single Master/ Single Slave Application
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.3.2 Slave Select Management
    • Figure 53. Generic SS Timing Diagram
    • Figure 54. Hardware/Software Slave Select Management
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.3.3 Master Mode Operation
    • 9.5.3.4 Master Mode Transmit Sequence
    • 9.5.3.5 Slave Mode Operation
    • 9.5.3.6 Slave Mode Transmit Sequence
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.4 Clock Phase and Clock Polarity
    • Figure 55. Data Clock Timing Diagram
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.5 Error Flags
      • 9.5.5.1 Master Mode Fault (MODF)
      • 9.5.5.2 Overrun Condition (OVR)
      • 9.5.5.3 Write Collision Error (WCOL)
    • Figure 56. Clearing the WCOL bit (Write Collision Flag) Software Sequence
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.5.4 Single Master Systems
    • Figure 57. Single Master / Multiple Slave Configuration
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.6 Low Power Modes
      • 9.5.6.1 Using the SPI to wakeup the MCU from Halt mode
    • 9.5.7 Interrupts
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • 9.5.8 Register Description
      • Table 17. SPI Master mode SCK Frequency
  • SERIAL PERIPHERAL INTERFACE (Cont�d)
    • Table 18. SPI Register Map and Reset Values
    • 9.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
      • 9.6.1 Introduction
      • 9.6.2 Main Features
      • 9.6.3 General Description
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • Figure 58. SCI Block Diagram
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.4 Functional Description
      • 9.6.4.1 Serial Data Format
    • Figure 59. Word Length Programming
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.4.2 Transmitter
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.4.3 Receiver
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • Figure 60. SCI Baud Rate and Extended Prescaler Block Diagram
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.4.4 Conventional Baud Rate Generation
    • 9.6.4.5 Extended Baud Rate Generation
    • 9.6.4.6 Receiver Muting and Wake-up Feature
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.4.7 Parity Control
      • Table 19. Frame Formats
    • 9.6.4.8 SCI Clock Tolerance
    • 9.6.4.9 Clock Deviation Causes
    • Figure 61 . Bit Sampling in Reception Mode
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.5 Low Power Modes
    • 9.6.6 Interrupts
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • 9.6.7 Register Description
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
  • SERIAL COMMUNICATIONS INTERFACE (Cont�d)
    • Table 20. Baudrate Selection
  • SERIAL COMMUNICATION INTERFACE (Cont�d)
    • Table 21. SCI Register Map and Reset Values
    • 9.7 I2C BUS INTERFACE (I2C)
      • 9.7.1 Introduction
      • 9.7.2 Main Features
      • 9.7.3 General Description
      • Figure 62. I2C BUS Protocol
  • I2C BUS INTERFACE (Cont�d)
    • Figure 63. I2C Interface Block Diagram
  • I2C BUS INTERFACE (Cont�d)
    • 9.7.4 Functional Description
      • 9.7.4.1 Slave Mode
  • I2C BUS INTERFACE (Cont�d)
    • 9.7.4.2 Master Mode
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
    • Figure 64. Transfer Sequencing
  • I2C BUS INTERFACE (Cont�d)
    • 9.7.5 Low Power Modes
    • 9.7.6 Interrupts
    • Figure 65. Event Flags and Interrupt Generation
  • I2C BUS INTERFACE (Cont�d)
    • 9.7.7 Register Description
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
  • I2C BUS INTERFACE (Cont�d)
  • I�C BUS INTERFACE (Cont�d)
    • Table 22. I2C Register Map and Reset Values
    • 9.8 CONTROLLER AREA NETWORK (CAN)
      • 9.8.1 Introduction
      • Figure 66. CAN Block Diagram
  • CONTROLLER AREA NETWORK (Cont�d)
    • 9.8.2 Main Features
    • 9.8.3 Functional Description
      • 9.8.3.1 Frame Formats
      • 9.8.3.2 Hardware Blocks
  • CONTROLLER AREA NETWORK (Cont�d)
    • Figure 67. CAN Frames
  • CONTROLLER AREA NETWORK (Cont�d)
    • 9.8.3.3 Modes of Operation
    • Figure 68 . CAN Controller State Diagram
      • n
  • CONTROLLER AREA NETWORK (Cont�d)
  • CONTROLLER AREA NETWORK (Cont�d)
    • Figure 69 . CAN Error State Diagram
  • CONTROLLER AREA NETWORK (Cont�d)
    • 9.8.3.4 Bit Timing Logic
    • Figure 70 . Bit Timing
  • CONTROLLER AREA NETWORK (Cont�d)
    • 9.8.4 Register Description
      • 9.8.4.1 General Purpose Registers
  • CONTROLLER AREA NETWORK (Cont�d)
  • CONTROLLER AREA NETWORK (Cont�d)
  • CONTROLLER AREA NETWORK (Cont�d)
  • CONTROLLER AREA NETWORK (Cont�d)
    • 9.8.4.2 Paged Registers
  • CONTROLLER AREA NETWORK (Cont�d)
  • CONTROLLER AREA NETWORK (Cont�d)
  • CONTROLLER AREA NETWORK (Cont�d)
    • Figure 71. CAN Register Map
  • CONTROLLER AREA NETWORK (Cont�d)
    • Figure 72. Page Maps
  • CONTROLLER AREA NETWORK (Cont�d)
    • Table 23. CAN Register Map and Reset Values
  • CONTROLLER AREA NETWORK (Cont�d)
    • 9.8.5 List of CAN Cell Limitations
      • 9.8.5.1 Omitted SOF bit
      • 9.8.5.2 CAN: CPU Write Access (More Than One Cycle) Corrupts CAN Frame
      • 9.8.5.3 WKPS Functionality
    • 9.9 10-BIT A/D CONVERTER (ADC)
      • 9.9.1 Introduction
      • 9.9.2 Main Features
      • Figure 73. ADC Block Diagram
  • 10-BIT A/D CONVERTER (ADC) (Cont�d)
    • 9.9.3 Functional Description
      • 9.9.3.1 A/D Converter Configuration
      • 9.9.3.2 Starting the Conversion
      • 9.9.3.3 Changing the conversion channel
    • 9.9.4 Low Power Modes
    • 9.9.5 Interrupts
  • 10-BIT A/D CONVERTER (ADC) (Cont�d)
    • 9.9.6 Register Description
  • 10-BIT A/D CONVERTER (Cont�d)
    • Table 24. ADC Register Map and Reset Values
• 10 INSTRUCTION SET
  • 10.1 CPU ADDRESSING MODES
    • Table 25. CPU Addressing Mode Overview
  • INSTRUCTION SET OVERVIEW (Cont�d)
    • 10.1.1 Inherent
    • 10.1.2 Immediate
    • 10.1.3 Direct
    • 10.1.4 Indexed (No Offset, Short, Long)
    • 10.1.5 Indirect (Short, Long)
  • INSTRUCTION SET OVERVIEW (Cont�d)
    • 10.1.6 Indirect Indexed (Short, Long)
      • Table 26. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
    • 10.1.7 Relative mode (Direct, Indirect)
  • INSTRUCTION SET OVERVIEW (Cont�d)
    • 10.2 INSTRUCTION GROUPS
  • INSTRUCTION SET OVERVIEW (Cont�d)
  • INSTRUCTION SET OVERVIEW (Cont�d)
• 11 ELECTRICAL CHARACTERISTICS
  • 11.1 PARAMETER CONDITIONS
    • 11.1.1 Minimum and Maximum values
    • 11.1.2 Typical values
    • 11.1.3 Typical curves
    • 11.1.4 Loading capacitor
    • Figure 74. Pin loading conditions
      • 11.1.5 Pin input voltage
    • Figure 75. Pin input voltage
  • 11.2 ABSOLUTE MAXIMUM RATINGS
    • 11.2.1 Voltage Characteristics
    • 11.2.2 Current Characteristics
    • 11.2.3 Thermal Characteristics
  • 11.3 OPERATING CONDITIONS
    • 11.3.1 Operating Conditions
    • Figure 76. fCPU Max Versus VDD
  • OPERATING CONDITIONS (Cont�d)
    • 11.4 LVD/AVD CHARACTERISTICS
      • 11.4.1 Low Voltage Detector (LVD) thresholds
      • 11.4.2 Auxiliary Voltage Detector (AVD) Thresholds
      • 11.4.3 External Voltage Detector (EVD) Thresholds
    • 11.5 SUPPLY CURRENT CHARACTERISTICS
      • 11.5.1 CURRENTCONSUMPTION
  • SUPPLY CURRENT CHARACTERISTICS (Cont�d)
    • Figure 77. Typical IDD in RUN vs. fCPU
    • Figure 78. Typical IDD in WAIT vs. fCPU
    • Figure 79. Typical IDD in SLOW vs. fCPU
    • Figure 80. Typical IDD in SLOW-WAIT vs. fCPU
  • SUPPLY CURRENT CHARACTERISTICS (Cont�d)
    • 11.5.2 Supply and Clock Managers
  • SUPPLY CURRENT CHARACTERISTICS (Cont�d)
    • 11.5.3 On-Chip Peripherals
    • 11.6 CLOCK AND TIMING CHARACTERISTICS
      • 11.6.1 General Timings
      • 11.6.2 External Clock Source
      • Figure 81. Typical Application with an External Clock Source
  • CLOCK AND TIMING CHARACTERISTICS (Cont�d)
    • 11.6.3 Crystal and Ceramic Resonator Oscillators
    • Figure 82. Typical Application with a Crystal or Ceramic Resonator
  • CLOCK AND TIMING CHARACTERISTICS (Cont�d)
  • CLOCK CHARACTERISTICS (Cont�d)
    • 11.6.4 RC Oscillators
    • Figure 83. Typical fOSC(RCINT) vs TA
      • Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitor...
  • CLOCK CHARACTERISTICS (Cont�d)
    • 11.6.5 Clock Security System (CSS)
    • 11.6.6 PLL Characteristics
    • Figure 84. PLL Jitter vs. Signal frequency1
    • 11.7 MEMORY CHARACTERISTICS
      • 11.7.1 RAM and Hardware Registers
    • 11.8 EMC CHARACTERISTICS
      • 11.8.1 Functional EMS
      • 11.8.2 Electro Magnetic Interference (EMI)
  • EMC CHARACTERISTICS (Cont�d)
    • 11.8.3 Absolute Electrical Sensitivity
      • 11.8.3.1 Electro-Static Discharge (ESD)
    • Figure 85. Typical Equivalent ESD Circuits
  • EMC CHARACTERISTICS (Cont�d)
    • 11.8.3.2 Static and Dynamic Latch-Up
    • 11.8.3.3 Designing hardened software to avoid noise problems
    • Figure 86. Simplified Diagram of the ESD Generator for DLU
  • EMC CHARACTERISTICS (Cont�d)
    • 11.8.4 ESD Pin Protection Strategy
    • Figure 87. Positive Stress on a Standard Pad vs. VSS
    • Figure 88. Negative Stress on a Standard Pad vs. VDD
  • EMC CHARACTERISTICS (Cont�d)
    • Figure 89. Positive Stress on a True Open Drain Pad vs. VSS
    • Figure 90. Negative Stress on a True Open Drain Pad vs. VDD
    • Figure 91. Multisupply Configuration
    • 11.9 I/O PORT PIN CHARACTERISTICS
      • 11.9.1 General Characteristics
      • Figure 92. Connecting Unused I/O Pins
      • Figure 93. Typical IPU vs. VDD with VIN=VSS
  • I/O PORT PIN CHARACTERISTICS (Cont�d)
    • 11.9.2 Output Driving Current
    • Figure 94. Typical VOL at VDD=5V (std. ports)
    • Figure 95. Typ. VOL at VDD=5V (high-sink ports)
    • Figure 96. Typical VOH at VDD=5V
  • I/O PORT PIN CHARACTERISTICS (Cont�d)
    • Figure 97. Typical VOL vs. VDD (std. ports)
    • Figure 98. Typical VOL vs. VDD (high-sink ports)
    • Figure 99. Typical VOH vs. VDD
    • 11.10 CONTROL PIN CHARACTERISTICS
      • 11.10.1 Asynchronous RESET Pin
      • Figure 100. Typical Application with RESET pin 6)7)8)
    • 11.11 TIMER PERIPHERAL CHARACTERISTICS
      • 11.11.1 8-Bit PWM-ART Auto-Reload Timer
      • 11.11.2 16-Bit Timer
    • 11.12 COMMUNICATION INTERFACE CHARACTERISTICS
      • 11.12.1 SPI - Serial Peripheral Interface
      • Figure 101. SPI Slave Timing Diagram with CPHA=0 3)
  • COMMUNICATION INTERFACE CHARACTERISTICS (Cont�d)
    • Figure 102. SPI Slave Timing Diagram with CPHA=11)
    • Figure 103. SPI Master Timing Diagram 1)
  • COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont�d)
    • 11.12.2 CAN - Controller Area Network Interface
  • COMMUNICATION INTERFACE CHARACTERISTICS (Cont�d)
    • 11.12.3 I2C - Inter IC Control Interface
    • Figure 104. Typical Application with I2C Bus and Timing Diagram 4)
    • 11.13 10-BIT ADC CHARACTERISTICS
      • Figure 105. RAIN max. vs fADC with CAIN=0pF3)
      • Figure 106. Recommended CAIN & RAIN values.4)
  • ADC CHARACTERISTICS (Cont�d)
    • Figure 107. Typical A/D Converter Application
  • ADC CHARACTERISTICS (Cont�d)
    • 11.13.1 Analog Power Supply and Reference Pins
    • 11.13.2 General PCB Design Guidelines
    • Figure 108. Power Supply Filtering
  • 10-BIT ADC CHARACTERISTICS (Cont�d)
    • 11.13.3 ADC Accuracy
    • Figure 109. ADC Accuracy Characteristics
• 12 PACKAGE CHARACTERISTICS
  • 12.1 PACKAGE MECHANICAL DATA
    • Figure 110. 80-Pin Thin Quad Flat Package
    • Figure 111. 64-Pin 14 x 14 Thin Quad Flat Package
  • PACKAGE MECHANICAL DATA (Cont�d)
    • Figure 112. 64-Pin 10 x 10 Thin Quad Flat Package
    • 12.2 THERMAL CHARACTERISTICS
    • 12.3 SOLDERING AND GLUEABILITY INFORMATION
      • Figure 113. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
      • Figure 114. Recommended Reflow Soldering Oven Profile (MID JEDEC)
• 13 ST72521B CONFIGURATION AND ORDERING INFORMATION
  • 13.1 DEVICE OPTION BYTES
    • 13.1.1 WDG HALT
    • 13.1.2 WDG SW
    • 13.1.3 CSS
    • 13.1.4 LVD
    • 13.1.5 RMP_R
    • 13.1.6 PKG
    • 13.1.7 RSTC
    • 13.1.8 OSCTYPE
  • ST72521B DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont�d)
    • 13.1.9 OSCRANGE
    • 13.1.10 PLL OFF
    • 13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
      • Figure 115. ROM Factory Coded Device Types
  • ST72521B DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont�d)
  • DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont�d)
    • 13.2.1 Version-Specific Sales Conditions
    • 13.3 DEVELOPMENT TOOLS
      • 13.3.1 Socket and Emulator Adapter Information
        • Table 27. STMicroelectronics Development Tools
        • Table 28. Suggested List of Socket Types
    • 13.4 ST7 APPLICATION NOTES
• 14 KNOWN LIMITATIONS
  • 14.1 External RC option
  • 14.2 CSS Function
  • 14.3 Safe Connection of OSC1/OSC2 Pins
  • 14.4 Unexpected Reset Fetch
  • 14.5 16-bit Timer PWM Mode
  • 14.6 CAN Cell Limitations
• 15 SUMMARY OF CHANGES
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