Rev. 1.5
April 2002
1/11
This is preliminary information on a new product now in development. Details are subject to change without notice.
ST72521M/R/AR
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
FIVE TIMERS, SPI, SCI, I
2
C, CAN INTERFACE
DATA BRIEFING
s
Memories
32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
1K to 2K RAM
s
Cloc anced reset system
Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
Clock sources: crystal/ceramic resonator os-
cillators, internal or external RC oscillator,
clock security system and bypass for external
clock
PLL for 2x frequency multiplication
Four power saving modes: Halt, Active-Halt,
Wait and Slow
s
Interrupt Management
Nested interrupt controller
14 interrupt vectors plus TRAP and RESET
TLI dedicated top level interrupt pin
15 external interrupt lines (on 4 vectors)
s
Up to 64 I/O Ports
48 multifunctional bidirectional I/O lines
34 alternate function lines
16 high sink outputs
s
5 Timers
Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
Configurable watchdog timer
Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
8-bit PWM Auto-Reload timer with: 2 input
captures, 4 PWM outputs, output compare
and time base interrupt, external clock with
event detector
s
4 Communications Interfaces
SPI synchronous serial interface
SCI asynchronous serial interface (LIN com-
patible)
I
2
C multimaster interface
CAN interface (2.0B Passive)
s
Analog peripheral
10-bit ADC with 16 input pins
s
Instruction Set
8-bit Data Manipulation
63 Basic Instructions
17 main Addressing Modes
8 x 8 Unsigned Multiply Instruction
True Bit Manipulation
s
Development Tools
Full hardware/software development package
In-Circuit Testing capability
Device Summary
TQFP80
14 x 14
TQFP64
10 x 10
TQFP64
14 x 14
Features
ST72(F)521(M/R/AR)9
ST72521(M/R/AR)7
ST72(F)521(R/AR)6
Program memory - bytes
60K
48K
32K
RAM (stack) - bytes
2048 (256)
1536 (256)
1024 (256)
Operating Voltage
3.8V to 5.5V
Temp. Range (ROM)
0
C to 70
C / -10
C to +85
C / -40
C to +85
C / -40
C to +105
C / -40
C to +125
C
Temp. Range (Flash)
-40
C to +85
C / -40
C to +125
C
N/A
-40
C to +125
C
Package
TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR)
TQFP64 14x14 (R), TQFP64 10x10 (AR)
1
ST72521M/R/AR
2/11
1 INTRODUCTION
The ST72521(A)R and ST72521M devices are
members of the ST7 microcontroller family de-
signed for mid-range applications with a CAN bus
interface (Controller Area Network).
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
ADDRESS
AND
DATA
BUS
OSC1
V
PP
CONTROL
PROGRAM
(32K - 60K Bytes)
V
DD
RESE T
PORT F
PF7:0
(8-bits)
TIMER A
BEEP
PORT A
RAM
(1024-2048 Bytes)
PORT C
10-BIT ADC
V
AREF
V
SSA
PORT B
PB7:0
(8-bits)
PWM ART
PORT E
CAN
PE7:0
(8-bits)
SCI
TIMER B
PA7:0
(8-bits)
PORT D
PD7:0
(8-bits)
SPI
PC7:0
(8-bits)
V
SS
WATCHDOG
TLI
OSC
LVD
OSC2
MEMORY
MCC/RTC/BEEP
EVD
AVD
I2C
1
On some devices only, see Device Summary on page 1
PORT G
1
PG7:0
(8-bits)
PORT H
1
PH7:0
(8-bits)
ST72521M/R/AR
5/11
PIN DESCRIPTION (Cont'd)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3V
DD
/0.7V
DD
C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
T
T
= TTL 0.8V / 2V with Schmitt trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
Input:
float = floating, wpu = weak pull-up, int = interrupt
1)
, ana = analog
Output:
OD = open drain
2)
, PP = push-pull
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n
Pin Name
Type
Level
Port
Main
function
(after
reset)
Alternate function
TQFP80
TQFP64
Input
Output
Input
Outpu t
float
wpu
int
ana
OD
PP
1
1
PE4 (HS)
I/O C
T
HS
X
X
X
X
Port E4
2
2
PE5 (HS)
I/O C
T
HS
X
X
X
X
Port E5
3
3
PE6 (HS)
I/O C
T
HS
X
X
X
X
Port E6
4
4
PE7 (HS)
I/O C
T
HS
X
X
X
X
Port E7
5
5
PB0/PWM3
I/O C
T
X
ei
2
X
X
Port B0
PWM Output 3
6
6
PB1/PWM2
I/O C
T
X
ei
2
X
X
Port B1
PWM Output 2
7
7
PB2/PWM1
I/O C
T
X
ei
2
X
X
Port B2
PWM Output 1
8
8
PB3/PWM0
I/O C
T
X
ei2
X
X
Port B3
PWM Output 0
9
-
PG0
I/O T
T
X
X
X
X
Port G0
10
-
PG1
I/O T
T
X
X
X
X
Port G1
11
-
PG2
I/O T
T
X
X
X
X
Port G2
12
-
PG3
I/O T
T
X
X
X
X
Port G3
13
9
PB4 (HS)/ARTCLK
I/O C
T
HS
X
ei3
X
X
Port B4
PWM-ART External Clock
14
10
PB5/ARTIC1
I/O C
T
X
ei3
X
X
Port B5
PWM-ART Input Capture 1
15
11
PB6/ARTIC2
I/O C
T
X
ei3
X
X
Port B6
PWM-ART Input Capture 2
16
12
PB7
I/O C
T
X
ei3
X
X
Port B7
17
13
PD0 /AIN0
I/O C
T
X
X
X
X
X
Port D0
ADC Analog Input 0
18
14
PD1/AIN1
I/O C
T
X
X
X
X
X
Port D1
ADC Analog Input 1
19
15
PD2/AIN2
I/O C
T
X
X
X
X
X
Port D2
ADC Analog Input 2
20
16
PD3/AIN3
I/O C
T
X
X
X
X
X
Port D3
ADC Analog Input 3
21
-
PG6
I/O T
T
X
X
X
X
Port G6
22
-
PG7
I/O T
T
X
X
X
X
Port G7
23
17
PD4/AIN4
I/O C
T
X
X
X
X
X
Port D4
ADC Analog Input 4
24
18
PD5/AIN5
I/O C
T
X
X
X
X
X
Port D5
ADC Analog Input 5
25
19
PD6/AIN6
I/O C
T
X
X
X
X
X
Port D6
ADC Analog Input 6
26
20
PD7/AIN7
I/O C
T
X
X
X
X
X
Port D7
ADC Analog Input 7
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