Электронный компонент: ST72F561R9TC

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Rev. 1.9

May 2004

1/262

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

ST72561

8-BIT MCU WITH FLASH OR ROM,

10-BIT ADC, 5 TIMERS, SPI,

LIN

SCI , ACTIVE CAN

PRELIMINARY DATA

Memories

� 32K to 60K High Density Flash (HDFlash) or

ROM with read-out protection capability. In-

Application Programming and In-Circuit Pro-

gramming for HDFlash devices

� 1 to 2K RAM
� HDFlash endurance: 100 cycles, data reten-

tion: 20 years at 55�C

Clock, Reset and Supply Management

� Low power crystal/ceramic resonator oscilla-

tors and bypass for external clock

� PLL for 2x frequency multiplication
� Five Power Saving Modes: Halt, Auto Wake

Up From Halt, Active-Halt, Wait and Slow

Interrupt Management

� Nested interrupt controller
� 14 interrupt vectors plus TRAP and RESET
� TLI top level interrupt (on 64-pin devices)
� Up to 21 external interrupt lines (on 4 vectors)

Up to 48 I/O Ports

� Up to 48 multifunctional bidirectional I/O lines
� Up to 36 alternate function lines
� Up to 6 high sink outputs

5 Timers

� 16-bit Timer with: 2 input captures, 2 output

compares, external clock input, PWM and

pulse generator modes

� 8-bit Timer with: 1 or 2 input captures, 1 or 2

output compares, PWM and pulse generator

modes

� 8-bit PWM Auto-Reload Timer with: 1 or 2 in-

put captures, 2 or 4 independent PWM output

channels, output compare and time base in-

terrupt, external clock with event detector

� Main Clock Controller with: Real time base

and Clock output

� Window watchdog timer

Up to 4 Communications Interfaces

� SPI synchronous serial interface
� Master/slave

LIN

SCI asynchronous serial

interface

� Master-only

LIN

SCI asynchronous serial in-

terface

� CAN 2.0B active

Analog peripheral (low current coupling)

� 10-bit A/D Converter with up to 16 inputs
� Up to 9 robust ports (low current coupling)

Instruction Set

� 8-bit data manipulation
� 63 basic instructions
� 17 main addressing modes
� 8 x 8 unsigned multiply instruction

Development Tools

� Full hardware/software development package

Device Summary

TQFP32

7x7mm

TQFP44

10x10mm

TQFP64

14 x 14

TQFP64

10 x 10

Features

ST72(F)561(AR/R/J/K)9

ST72(F)561(AR/R/J/K)6

Program memory - bytes

60K

32K

RAM (stack) - bytes

2K (256)

1K (256)

Operating Supply

4.5V to 5.5V

CPU Frequency

External Resonator Osc. w/ PLLx2/8MHz

Max. Temp. Range

-40�C to +125�C

Packages

TQFP64 10x10mm (AR), TQFP64 14x14mm (R), TQFP44 10x10mm (J), TQFP32 7x7mm (K)

1

Table of Contents

262

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2

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10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC . . . . . . . . . . . . . . . 60

10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.5 8-BIT TIMER (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . . 123

10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER ONLY) . . . . . . . . . . . . 154

10.9 BECAN CONTROLLER (BECAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

10.1010-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

12.6 AUTO WAKEUP FROM HALT OSCILLATOR (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

12.10CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

12.11TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

12.12COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 243

12.1310-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 253

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 255

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

15.1 CLEARING ACTIVE INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

15.2 CAN FIFO CORRUPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

15.3 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

15.4 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

ST72561

4/262

16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

ST72561

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1 INTRODUCTION

The ST72561/ST72563 devices are members of
the ST7 microcontroller family designed for mid-
range applications with CAN (Controller Area Net-
work) and LIN (Local Interconnect Network) inter-
face.

All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

A

D

DRE

S

S

A

N

D DA

T

A

B

U

S

OSC1

OSC2

RESET

PORT A

CONTROL

RAM

(512 - 2048 Bytes)

PA7:0

(8 bits)

1

PROGRAM

(16 - 60 K Bytes)

MEMORY

PLL x 2

PWM

8-bit

PORT B

PORT C

SPI

LIN

SCI2

PB7:0

(8 bits)

1

PC7:0

(8 bits)

1

CAN

(2.0B ACTIVE)

OSC

PORT D

PD7:0

(8 bits)

1

/2

option

LIN

SCI1

16-Bit

TIMER

(LIN master)

(LIN master/slave)

V

SS

V

DD

POWER

SUPPLY

PORT E

PE7:0

(8 bits)

1

PORT F

PF7:0

(8 bits)

1

TIMER

ART

MCC

(Clock Control)

1

On some devices only, see Device Summary on page 1

TLI

1

WATCHDOG

WINDOW

3

Document Outline

• ST72561
• 1 INTRODUCTION
• 2 PIN DESCRIPTION
• 3 REGISTER & MEMORY MAP
• 4 FLASH PROGRAM MEMORY
  • 4.1 Introduction
  • 4.2 Main Features
  • 4.3 Structure
    • 4.3.1 Read-out Protection
  • 4.4 ICC Interface
  • 4.5 ICP (In-Circuit Programming)
  • 4.6 IAP (In-Application Programming)
  • 4.7 Related Documentation
  • 4.8 Register Description
• 5 CENTRAL PROCESSING UNIT
  • 5.1 INTRODUCTION
  • 5.2 MAIN FEATURES
  • 5.3 CPU REGISTERS
• 6 SUPPLY, RESET AND CLOCK MANAGEMENT
  • 6.1 PHASE LOCKED LOOP
  • 6.2 MULTI-OSCILLATOR (MO)
  • 6.3 RESET SEQUENCE MANAGER (RSM)
    • 6.3.1 Introduction
    • 6.3.2 Asynchronous External RESET pin
    • 6.3.3 External Power-On RESET
    • 6.3.4 Internal Low Voltage Detector (LVD) RESET
    • 6.3.5 Internal Watchdog RESET
  • 6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
    • 6.4.1 Low Voltage Detector (LVD)
    • 6.4.2 Auxiliary Voltage Detector (AVD)
      • 6.4.2.1 Monitoring the VDD Main Supply
    • 6.4.3 Low Power Modes
      • 6.4.3.1 Interrupts
    • 6.4.4 Register Description
• 7 INTERRUPTS
  • 7.1 INTRODUCTION
  • 7.2 Masking and Processing Flow
  • 7.3 Interrupts and Low Power Modes
  • 7.4 Concurrent & Nested Management
  • 7.5 Interrupt Register Description
  • 7.6 EXTERNAL INTERRUPTS
    • 7.6.1 I/O PORT INTERRUPT SENSITIVITY
    • 7.6.2 Register Description
• 8 POWER SAVING MODES
  • 8.1 INTRODUCTION
  • 8.2 SLOW MODE
  • 8.3 WAIT MODE
  • 8.4 HALT MODE
  • 8.5 ACTIVE-HALT MODE
  • 8.6 AUTO WAKE UP FROM HALT MODE
    • 8.6.0.1 Register Description
• 9 I/O PORTS
  • 9.1 INTRODUCTION
  • 9.2 FUNCTIONAL DESCRIPTION
    • 9.2.1 Input Modes
    • 9.2.2 Output Modes
    • 9.2.3 Alternate Functions
  • 9.3 I/O PORT IMPLEMENTATION
  • 9.4 LOW POWER MODES
  • 9.5 INTERRUPTS
  • 9.6 I/O Port Implementation
    • 9.6.1 Standard Ports
    • 9.6.2 Interrupt Ports
    • 9.6.3 Pull-up Input Port (CANTX requirement)
• 10 ON-CHIP PERIPHERALS
  • 10.1 WINDOW WATCHDOG (WWDG)
    • 10.1.1 Introduction
    • 10.1.2 Main Features
    • 10.1.3 Functional Description
    • 10.1.4 Using Halt Mode with the WDG
    • 10.1.5 How to Program the Watchdog Timeout
    • 10.1.6 Low Power Modes
    • 10.1.7 Hardware Watchdog Option
    • 10.1.8 Using Halt Mode with the WDG (WDGHALT option)
    • 10.1.9 Interrupts
    • 10.1.10 Register Description
  • 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC
    • 10.2.1 Programmable CPU Clock Prescaler
    • 10.2.2 Clock-out Capability
    • 10.2.3 Real Time Clock Timer (RTC)
    • 10.2.4 Low Power Modes
    • 10.2.5 Interrupts
    • 10.2.6 Register Description
  • 10.3 PWM AUTO-RELOAD TIMER (ART)
    • 10.3.1 Introduction
    • 10.3.2 Functional Description
    • 10.3.3 Register Description
  • 10.4 16-BIT TIMER
    • 10.4.1 Introduction
    • 10.4.2 Main Features
    • 10.4.3 Functional Description
      • 10.4.3.1 Counter
      • 10.4.3.2 External Clock
      • 10.4.3.3 Input Capture
      • 10.4.3.4 Output Compare
      • 10.4.3.5 One Pulse Mode
      • 10.4.3.6 Pulse Width Modulation Mode
    • 10.4.4 Low Power Modes
    • 10.4.5 Interrupts
    • 10.4.6 Summary of Timer modes
    • 10.4.7 Register Description
  • 10.5 8-BIT TIMER (TIM8)
    • 10.5.1 Introduction
    • 10.5.2 Main Features
    • 10.5.3 Functional Description
      • 10.5.3.1 Counter
      • 10.5.3.2 Input Capture
      • 10.5.3.3 Output Compare
      • 10.5.3.4 One Pulse Mode
      • 10.5.3.5 Pulse Width Modulation Mode
    • 10.5.4 Low Power Modes
    • 10.5.5 Interrupts
    • 10.5.6 Summary of Timer modes
    • 10.5.7 Register Description
    • 10.5.8 8-bit Timer Register Map
  • 10.6 SERIAL PERIPHERAL INTERFACE (SPI)
    • 10.6.1 Introduction
    • 10.6.2 Main Features
    • 10.6.3 General Description
      • 10.6.3.1 Functional Description
      • 10.6.3.2 Slave Select Management
      • 10.6.3.3 Master Mode Operation
      • 10.6.3.4 Master Mode Transmit Sequence
      • 10.6.3.5 Slave Mode Operation
      • 10.6.3.6 Slave Mode Transmit Sequence
    • 10.6.4 Clock Phase and Clock Polarity
    • 10.6.5 Error Flags
      • 10.6.5.1 Master Mode Fault (MODF)
      • 10.6.5.2 Overrun Condition (OVR)
      • 10.6.5.3 Write Collision Error (WCOL)
      • 10.6.5.4 Single Master and Multimaster Configurations
    • 10.6.6 Low Power Modes
      • 10.6.6.1 Using the SPI to wake-up the Device from Halt mode
    • 10.6.7 Interrupts
    • 10.6.8 Register Description
  • 10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
    • 10.7.1 Introduction
    • 10.7.2 SCI Features
    • 10.7.3 LIN Features
    • 10.7.4 General Description
    • 10.7.5 SCI Mode - Functional Description
      • 10.7.5.1 Serial Data Format
      • 10.7.5.2 Transmitter
      • 10.7.5.3 Receiver
      • 10.7.5.4 Conventional Baud Rate Generation
      • 10.7.5.5 Extended Baud Rate Generation
      • 10.7.5.6 Receiver Muting and Wake-up Feature
      • 10.7.5.7 Parity Control
    • 10.7.6 Low Power Modes
    • 10.7.7 Interrupts
    • 10.7.8 SCI Mode Register Description
    • 10.7.9 LIN Mode - Functional Description.
      • 10.7.9.1 Entering LIN Mode
      • 10.7.9.2 LIN Transmission
      • 10.7.9.3 LIN Reception
      • 10.7.9.4 LIN Error Detection
      • 10.7.9.5 LIN Baudrate
      • 10.7.9.6 LIN Slave Baud Rate Generation
      • 10.7.9.7 LINSCI Clock Tolerance
      • 10.7.9.8 Clock Deviation Causes
      • 10.7.9.9 Error due to LIN Synch measurement
      • 10.7.9.10 Error due to Baud Rate Quantisation
      • 10.7.9.11 Impact of Clock Deviation on Maximum Baud Rate
    • 10.7.10 LIN Mode Register Description
  • 10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN Master Only)
    • 10.8.1 Introduction
    • 10.8.2 Main Features
    • 10.8.3 General Description
    • 10.8.4 Functional Description
      • 10.8.4.1 Serial Data Format
      • 10.8.4.2 Transmitter
      • 10.8.4.3 Receiver
      • 10.8.4.4 Conventional Baud Rate Generation
      • 10.8.4.5 Extended Baud Rate Generation
      • 10.8.4.6 Receiver Muting and Wake-up Feature
      • 10.8.4.7 Parity control
    • 10.8.5 Low Power Modes
    • 10.8.6 Interrupts
    • 10.8.7 SCI Synchronous Transmission
    • 10.8.8 Register Description
  • 10.9 beCAN CONTROLLER (beCAN)
    • 10.9.1 Main Features
    • 10.9.2 General Description
    • 10.9.3 Operating Modes
      • 10.9.3.1 Initialization Mode
      • 10.9.3.2 Normal Mode
      • 10.9.3.3 Low Power Mode (Sleep)
      • 10.9.3.4 Test Mode
      • 10.9.3.5 Silent Mode
      • 10.9.3.6 Loop Back Mode
      • 10.9.3.7 Loop Back combined with Silent Mode
    • 10.9.4 Functional Description
      • 10.9.4.1 Transmission Handling
      • 10.9.4.2 Reception Handling For the reception of CAN messages, three mailboxes organized as a FIF...
      • 10.9.4.3 Identifier Filtering
      • 10.9.4.4 Message Storage
      • 10.9.4.5 Error Management
      • 10.9.4.6 Bit Timing
    • 10.9.5 Interrupts
    • 10.9.6 Register Access Protection
    • 10.9.7 BeCAN Cell Limitations
      • 10.9.7.1 FIFO Corruption
    • 10.9.8 Register Description
      • 10.9.8.1 Control and Status Registers
      • 10.9.8.2 Mailbox Registers
      • 10.9.8.3 CAN Filter Registers
      • 10.9.8.4 Page Mapping for CAN
  • 10.10 10-BIT A/D CONVERTER (ADC)
    • 10.10.1 Introduction
    • 10.10.2 Main Features
    • 10.10.3 Functional Description
      • 10.10.3.1 Digital A/D Conversion Result
      • 10.10.3.2 A/D Conversion
      • 10.10.3.3 Changing the conversion channel
      • 10.10.3.4 ADCDR consistency
    • 10.10.4 Low Power Modes
    • 10.10.5 Interrupts
    • 10.10.6 Register Description
• 11 INSTRUCTION SET
  • 11.1 CPU ADDRESSING MODES
    • 11.1.1 Inherent
    • 11.1.2 Immediate
    • 11.1.3 Direct
    • 11.1.4 Indexed (No Offset, Short, Long)
    • 11.1.5 Indirect (Short, Long)
    • 11.1.6 Indirect Indexed (Short, Long)
    • 11.1.7 Relative mode (Direct, Indirect)
  • 11.2 INSTRUCTION GROUPS
• 12 ELECTRICAL CHARACTERISTICS
  • 12.1 PARAMETER CONDITIONS
    • 12.1.1 Minimum and Maximum values
    • 12.1.2 Typical values
    • 12.1.3 Typical curves
    • 12.1.4 Loading capacitor
    • 12.1.5 Pin input voltage
  • 12.2 ABSOLUTE MAXIMUM RATINGS
    • 12.2.1 Voltage Characteristics
    • 12.2.2 Current Characteristics
    • 12.2.3 Thermal Characteristics
  • 12.3 OPERATING CONDITIONS
    • 12.3.1 General Operating Conditions
    • 12.3.2 Operating Conditions with Low Voltage Detector (LVD)
    • 12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
  • 12.4 SUPPLY CURRENT CHARACTERISTICS
    • 12.4.1 RUN and SLOW Modes (Flash devices)
    • 12.4.2 WAIT and SLOW WAIT Modes (Flash devices)
    • 12.4.3 HALT and ACTIVE-HALT Modes
    • 12.4.4 Supply and Clock Managers
    • 12.4.5 On-Chip Peripherals
  • 12.5 CLOCK AND TIMING CHARACTERISTICS
    • 12.5.1 General Timings
    • 12.5.2 External Clock Source
    • 12.5.3 Crystal and Ceramic Resonator Oscillators
    • 12.5.4 PLL Characteristics
  • 12.6 Auto Wakeup from Halt Oscillator (AWU)
  • 12.7 MEMORY CHARACTERISTICS
    • 12.7.1 RAM and Hardware Registers
    • 12.7.2 FLASH Memory
  • 12.8 EMC CHARACTERISTICS
    • 12.8.1 Functional EMS (Electro Magnetic Susceptibility)
      • 12.8.1.1 Designing hardened software to avoid noise problems
    • 12.8.2 Electro Magnetic Interference (EMI)
    • 12.8.3 Absolute Maximum Ratings (Electrical Sensitivity)
      • 12.8.3.1 Electro-Static Discharge (ESD)
      • 12.8.3.2 Static and Dynamic Latch-Up
  • 12.9 I/O PORT PIN CHARACTERISTICS
    • 12.9.1 General Characteristics
    • 12.9.2 Output Driving Current
  • 12.10 CONTROL PIN CHARACTERISTICS
    • 12.10.1 Asynchronous RESET Pin
    • 12.10.2 ICCSEL/VPP Pin
  • 12.11 TIMER PERIPHERAL CHARACTERISTICS
    • 12.11.1 8-Bit PWM-ART Autoreload Timer
    • 12.11.2 8-Bit Timer
    • 12.11.3 16-Bit Timer
  • 12.12 COMMUNICATION INTERFACE CHARACTERISTICS
    • 12.12.1 SPI - Serial Peripheral Interface
    • 12.12.2 CAN - Controller Area Network Interface
  • 12.13 10-BIT ADC CHARACTERISTICS
    • 12.13.0.1 Analog Power Supply and Reference Pins
    • 12.13.0.2 General PCB Design Guidelines
    • 12.13.0.3 Software Filtering of Spurious Conversion Results
• 13 PACKAGE CHARACTERISTICS
  • 13.1 PACKAGE MECHANICAL DATA
  • 13.2 THERMAL CHARACTERISTICS
  • 13.3 SOLDERING AND GLUEABILITY INFORMATION
• 14 DEVICE CONFIGURATION AND ORDERING INFORMATION
  • 14.1 FLASH OPTION BYTES
  • 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
    • 14.2.1 Version-Specific Sales Conditions
  • 14.3 DEVELOPMENT TOOLS
• 15 IMPORTANT NOTES
  • 15.1 CLEARING ACTIVE INTERRUPTS
  • 15.2 CAN FIFO CORRUPTION
  • 15.3 FLASH/FASTROM DEVICES ONLY
    • 15.3.1 LINSCI wrong break duration
    • 15.3.2 16-bit and 8-bit Timer PWM Mode
  • 15.4 ROM DEVICES ONLY
    • 15.4.1 16-bit Timer PWM Mode Buffering Feature Change
• 16 REVISION HISTORY