Электронный компонент: ST7FLITE10F1B6

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December 2004

1/131

Rev. 2.0

ST7LITE1

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

DATA EEPROM, ADC, 4 TIMERS, SPI

Memories

� 4 Kbytes single voltage extended Flash

(XFlash) Program memory with read-out pro-
tection, In-Circuit Programming and In-Appli-
cation programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20
years at 55�C.

� 256 bytes RAM
� 128 bytes data E

2

PROM with read-out protec-

tion. 300K write/erase cycles guaranteed,
data retention: 20 years at 55�C.

Clock, Reset and Supply Management

� Enhanced reset system
� Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage detector

(AVD) with interrupt capability for implement-

ing safe power-down procedures

� Clock sources: Internal 1% RC oscillator (on

some devices), crystal/ceramic resonator or
external clock

� Internal 32-MHz input clock for Auto-reload

timer

� Optional x4 or x8 PLL for 4 or 8 MHz internal

clock

� Five Power Saving Modes: Halt, Active-Halt,

Auto Wake-up from Halt, Wait and Slow

I/O Ports

� Up to 15 multifunctional bidirectional I/O lines
� 7

high sink outputs

4 Timers

� Configurable watchdog timer
� Two 8-bit Lite Timers with prescaler,

1 realtime base and 1 input capture

� One 12-bit Auto-reload Timer with 4 PWM

outputs, input capture and output compare
functions

Communication Interface

� SPI synchronous serial interface

Interrupt Management

� 10 interrupt vectors plus TRAP and RESET
� 15 external interrupt lines (on 4 vectors)

A/D Converter

� 7 input channels
� Fixed gain Op-amp
� 13-bit precision for 0 to 430 mV (@ 5V V

DD

)

� 10-bit precision for 430 mV to 5V (@ 5V V

DD

)

Instruction Set

� 8-bit data manipulation
� 63 basic instructions with illegal opcode de-

tection

� 17 main addressing modes
� 8 x 8 unsigned multiply instructions

Development Tools

� Full hardware/software development package
� DM (Debug Module)

Device Summary

SO20

Features

ST7LITE10

ST7LITE15

ST7LITE19

Program memory - bytes

4K

RAM (stack) - bytes

256 (128)

Data EEPROM - bytes

-

-

128

Peripherals

Lite Timer with Watchdog,

Autoreload Timer, SPI,

10-bit ADC with Op-Amp

Lite Timer with Watchdog,

Autoreload Timer with 32-MHz input clock,

SPI, 10-bit ADC with Op-Amp

Operating Supply

2.4V to 5.5V

CPU Frequency

Up to 8Mhz

(w/ ext OSC up to 16MHz)

Up to 8Mhz (w/ ext OSC up to 16MHz

and int 1MHz RC 1% PLLx8/4MHz)

Operating Temperature

-40�C to +85�C

Packages

SO20 300"

1

Table of Contents

131

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3

PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4

ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.5

MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6

RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.7

REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3

MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4

POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5

ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.6

DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.7

REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3

CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1

INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2

PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3

REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4

MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5

RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.6

SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1

NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.2

EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.3

PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.2

SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.3

WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.4

HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.5

ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.6

AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1

Table of Contents

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10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.2 12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 113

13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

16.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . 129

16.4 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 129

ST7LITE1

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16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 129

16.6 USING PB4 AS EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section "IMPORTANT NOTES" on page 128.

ST7LITE1

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1 INTRODUCTION

The ST7LITE1 is a member of the ST7 microcon-
troller family. All ST7 devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.

The ST7LITE1 features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.

Under software control, the ST7LITE1 device can
be placed in WAIT, SLOW, or HALT mode, reduc-
ing power consumption when the application is in
idle or standby state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.

For easy reference, all parametric data are located
in

section 13 on page 91

.The devices feature an

on-chip Debug Module (DM) to support in-circuit
debugging (ICD). For a description of the DM reg-
isters, refer to the ST7 ICC Protocol Reference
Manual.

Figure 1. General Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

OSC2

RESET

PORT A

Internal
CLOCK

CONTROL

RAM

(256 Bytes)

PA7:0

(8 bits)

V

SS

V

DD

POWER

SUPPLY

PROGRAM

(4K Bytes)

LVD

MEMORY

PLL x 8

Ext.

1MHz

PLL

Int.

1MHz

8-Bit

LITE TIMER 2

PORT B

SPI

PB6:0

(7 bits)

DATA EEPROM

(128 Bytes)

1% RC

OSC

to

16MHz

ADC

+ OpAmp

12-Bit

Auto-Reload

TIMER 2

CLKIN

/ 2

or PLL X4

8MHz -> 32MHz

WATCHDOG

Debug Module

1

Document Outline

• 1 INTRODUCTION
• 2 PIN DESCRIPTION
• 3 REGISTER & MEMORY MAP
• 4 FLASH PROGRAM MEMORY
  • 4.1 Introduction
  • 4.2 Main Features
  • 4.3 PROGRAMMING MODES
    • 4.3.1 In-Circuit Programming (ICP)
    • 4.3.2 In Application Programming (IAP)
  • 4.4 ICC interface
  • 4.5 Memory Protection
    • 4.5.1 Read out Protection
    • 4.5.2 Flash Write/Erase Protection
  • 4.6 Related Documentation
  • 4.7 Register Description
• 5 DATA EEPROM
  • 5.1 INTRODUCTION
  • 5.2 MAIN FEATURES
  • 5.3 MEMORY ACCESS
  • 5.4 POWER SAVING MODES
  • 5.5 ACCESS ERROR HANDLING
  • 5.6 Data EEPROM Read-out Protection
  • 5.7 REGISTER DESCRIPTION
• 6 CENTRAL PROCESSING UNIT
  • 6.1 INTRODUCTION
  • 6.2 MAIN FEATURES
  • 6.3 CPU REGISTERS
• 7 SUPPLY, RESET AND CLOCK MANAGEMENT
  • 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
  • 7.2 PHASE LOCKED LOOP
  • 7.3 REGISTER DESCRIPTION
  • 7.4 MULTI-OSCILLATOR (MO)
  • 7.5 RESET SEQUENCE MANAGER (RSM)
    • 7.5.1 Introduction
    • 7.5.2 Asynchronous External RESET pin
    • 7.5.3 External Power-On RESET
    • 7.5.4 Internal Low Voltage Detector (LVD) RESET
    • 7.5.5 Internal Watchdog RESET
  • 7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
    • 7.6.1 Low Voltage Detector (LVD)
    • 7.6.2 Auxiliary Voltage Detector (AVD)
      • 7.6.2.1 Monitoring the VDD Main Supply
    • 7.6.3 Low Power Modes
      • 7.6.3.1 Interrupts
    • 7.6.4 Register Description
• 8 INTERRUPTS
  • 8.1 NON MASKABLE SOFTWARE INTERRUPT
  • 8.2 EXTERNAL INTERRUPTS
  • 8.3 PERIPHERAL INTERRUPTS
• 9 POWER SAVING MODES
  • 9.1 INTRODUCTION
  • 9.2 SLOW MODE
  • 9.3 WAIT MODE
  • 9.4 HALT MODE
    • 9.4.1 Halt Mode Recommendations
  • 9.5 ACTIVE-HALT MODE
  • 9.6 AUTO WAKE UP FROM HALT MODE
    • 9.6.0.1 Register Description
• 10 I/O PORTS
  • 10.1 INTRODUCTION
  • 10.2 FUNCTIONAL DESCRIPTION
    • 10.2.1 Input Modes
    • 10.2.2 Output Modes
    • 10.2.3 Alternate Functions
  • 10.3 I/O PORT IMPLEMENTATION
  • 10.4 UNUSED I/O PINS
  • 10.5 LOW POWER MODES
  • 10.6 INTERRUPTS
  • 10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
• 11 ON-CHIP PERIPHERALS
  • 11.1 WATCHDOG TIMER (WDG)
    • 11.1.1 Introduction
    • 11.1.2 Main Features
    • 11.1.3 Functional Description
    • 11.1.4 Hardware Watchdog Option
      • 11.1.4.1 Using Halt Mode with the WDG (WDGHALT option)
    • 11.1.5 Interrupts
    • 11.1.6 Register Description
  • 11.2 12-BIT AUTORELOAD TIMER 2 (AT2)
    • 11.2.1 Introduction
    • 11.2.2 Main Features
    • 11.2.3 Functional Description
      • 11.2.3.1 Input Capture
    • 11.2.4 Low Power Modes
    • 11.2.5 Interrupts
    • 11.2.6 Register Description
  • 11.3 LITE TIMER 2 (LT2)
    • 11.3.1 Introduction
    • 11.3.2 Main Features
    • 11.3.3 Functional Description
      • 11.3.3.1 Timebase Counter 1
      • 11.3.3.2 Timebase Counter 2
      • 11.3.3.3 Input Capture
    • 11.3.4 Low Power Modes
    • 11.3.5 Interrupts
    • 11.3.6 Register Description
  • 11.4 SERIAL PERIPHERAL INTERFACE (SPI)
    • 11.4.1 Introduction
    • 11.4.2 Main Features
    • 11.4.3 General Description
      • 11.4.3.1 Functional Description
      • 11.4.3.2 Slave Select Management
      • 11.4.3.3 Master Mode Operation
      • 11.4.3.4 Master Mode Transmit Sequence
      • 11.4.3.5 Slave Mode Operation
      • 11.4.3.6 Slave Mode Transmit Sequence
    • 11.4.4 Clock Phase and Clock Polarity
    • 11.4.5 Error Flags
      • 11.4.5.1 Master Mode Fault (MODF)
      • 11.4.5.2 Overrun Condition (OVR)
      • 11.4.5.3 Write Collision Error (WCOL)
      • 11.4.5.4 Single Master and Multimaster Configurations
    • 11.4.6 Low Power Modes
      • 11.4.6.1 Using the SPI to wake-up the Device from Halt mode
    • 11.4.7 Interrupts
    • 11.4.8 Register Description
  • 11.5 10-BIT A/D CONVERTER (ADC)
    • 11.5.1 Introduction
    • 11.5.2 Main Features
    • 11.5.3 Functional Description
      • 11.5.3.1 Analog Power Supply
      • 11.5.3.2 Input Voltage Amplifier
      • 11.5.3.3 Digital A/D Conversion Result
      • 11.5.3.4 A/D Conversion
    • 11.5.4 Low Power Modes
    • 11.5.5 Interrupts
    • 11.5.6 Register Description
• 12 INSTRUCTION SET
  • 12.1 ST7 ADDRESSING MODES
    • 12.1.1 Inherent
    • 12.1.2 Immediate
    • 12.1.3 Direct
    • 12.1.4 Indexed (No Offset, Short, Long)
    • 12.1.5 Indirect (Short, Long)
    • 12.1.6 Indirect Indexed (Short, Long)
    • 12.1.7 Relative Mode (Direct, Indirect)
  • 12.2 INSTRUCTION GROUPS
    • 12.2.1 Illegal Opcode Reset
• 13 ELECTRICAL CHARACTERISTICS
  • 13.1 PARAMETER CONDITIONS
    • 13.1.1 Minimum and Maximum values
    • 13.1.2 Typical values
    • 13.1.3 Typical curves
    • 13.1.4 Loading capacitor
    • 13.1.5 Pin input voltage
  • 13.2 ABSOLUTE MAXIMUM RATINGS
    • 13.2.1 Voltage Characteristics
    • 13.2.2 Current Characteristics
    • 13.2.3 Thermal Characteristics
  • 13.3 OPERATING CONDITIONS
    • 13.3.1 General Operating Conditions: Suffix 6 Devices
    • 13.3.2 Operating Conditions with Low Voltage Detector (LVD)
    • 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
    • 13.3.4 Internal RC Oscillator and PLL
      • 13.3.4.1 Devices with ��6� order code suffix (tested for TA = -40 to +85C) @ VDD = 4.5 to 5.5V
      • 13.3.4.2 Devices with ��6� order code suffix (tested for TA = -40 to +85C) @ VDD = 2.7 to 3.3V
      • 13.3.4.3 32MHz PLL
  • 13.4 SUPPLY CURRENT CHARACTERISTICS
    • 13.4.1 Supply Current
    • 13.4.2 On-chip peripherals
  • 13.5 CLOCK AND TIMING CHARACTERISTICS
    • 13.5.1 General Timings
    • 13.5.2 Auto Wakeup from Halt Oscillator (AWU)
  • 13.6 MEMORY CHARACTERISTICS
    • 13.6.1 RAM and Hardware Registers
    • 13.6.2 FLASH Program Memory
    • 13.6.3 EEPROM Data Memory
  • 13.7 EMC CHARACTERISTICS
    • 13.7.1 Functional EMS (Electro Magnetic Susceptibility)
      • 13.7.1.1 Designing hardened software to avoid noise problems
    • 13.7.2 Electro Magnetic Interference (EMI)
    • 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity)
      • 13.7.3.1 Electro-Static Discharge (ESD)
      • 13.7.3.2 Static and Dynamic Latch-Up
  • 13.8 I/O PORT PIN CHARACTERISTICS
    • 13.8.1 General Characteristics
    • 13.8.2 Output Driving Current
  • 13.9 CONTROL PIN CHARACTERISTICS
    • 13.9.1 Asynchronous RESET Pin
  • 13.10 COMMUNICATION INTERFACE CHARACTERISTICS
    • 13.10.1 SPI - Serial Peripheral Interface
  • 13.11 10-BIT ADC CHARACTERISTICS
• 14 PACKAGE CHARACTERISTICS
  • 14.1 PACKAGE MECHANICAL DATA
  • 14.2 SOLDERING AND GLUEABILITY INFORMATION
• 15 DEVICE CONFIGURATION
  • 15.1 OPTION BYTES
  • 15.2 DEVICE ORDERING INFORMATION
  • 15.3 DEVELOPMENT TOOLS
  • 15.4 ST7 APPLICATION NOTES
• 16 IMPORTANT NOTES
  • 16.1 EXECUTION OF BTJX INSTRUCTION
  • 16.2 ADC CONVERSION SPURIOUS RESULTS
  • 16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION
  • 16.4 NEGATIVE INJECTION IMPACT ON ADC ACCURACY
  • 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE
  • 16.6 USING PB4 AS EXTERNAL INTERRUPT
• 17 REVISION HISTORY