Rev. 1.3
March 2003
1/102
ST7SCR
8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K
FLASH, 768
RAM, SMARTCARD I/F, TIMER
s
Memories
Up to 16K of ROM or High Density Flash (HD-
Flash) program memory with read/write pro-
tection, HDFlash In-Circuit and In-Application
Programming. 100 write/erase cycles guaran-
teed, data retention: 20 years at 55C
Up to 768 bytes of RAM including up to 128
bytes stack and 256 bytes USB buffer
s
Clock, Reset and Supply Management
Low Voltage Reset
2 power saving modes: Halt and Wait modes
PLL for generating 48 MHz USB clock using a
4 MHz crystal
s
Interrupt Management
Nested Interrupt Controller
s
USB (Universal Serial Bus) Interface
256-byte buffer for full speed bulk, control and
interrupt transfer types compliant with USB
specification (version 2.0)
On-Chip 3.3V USB voltage regulator and
transceivers with software power-down
7 USB Endpoints:
One 8-byte Bidirectional Control Endpoint
One 64-byte In Endpoint,
One 64-byte Out Endpoint
Four 8-byte In Endpoints
s
35 or 4 I/O ports:
Up to 4 LED outputs with software program-
mable constant current (3 or 7 mA).
2 General purpose I/Os programmable as in-
terrupts
Up to 8 line inputs programmable as interrupts
Up to 20 Outputs
1 line assigned by default as static input after
reset
s
ISO7816-3 UART Interface:
4 Mhz Clock generation
Synchronous/Asynchronous protocols (T=0,
T=1)
Automatic retry on parity error
Programmable Baud rate from 372 clock puls-
es up to 11.625 clock pulses (D=32/F=372)
Card Insertion/Removal Detection
s
Smartcard Power Supply:
Selectable card V
CC
1.8V, 3V, and 5V
Internal Step-up converter for 5V supplied
Smartcards (with a current of up to 55mA) us-
ing only two external components.
Programmable Smartcard Internal Voltage
Regulator (1.8V to 3.0V) with current overload
protection and 4 KV ESD protection (Human
Body Model) for all Smartcard Interface I/Os
s
One 8-bit Timer
Time Base Unit (TBU) for generating periodic
interrupts.
s
Development Tools
Full hardware/software development package
Table 1. Device Summary
TQFP64 14x14
SO24
Features
ST7FSCR1R4
ST7SCR1R4
ST7FSCR1E4
ST7SCR1E4
Program memory
16K FLASH
16K ROM
16K FLASH
16K ROM
User RAM (stack) - bytes
768 (128)
Peripherals
USB Full-Speed (7 Ep), TBU, Watchdog timer, ISO7816-3 Interface
Operating Supply
4.0 to 5.5V
Package
TQFP64
SO24
CPU Frequency
4 or 8 Mhz
Operating temperature
0C to +70C
1
Table of Contents
102
2/102
ST7SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
4.3
STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4
ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5
IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6
PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
5.3
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
6.2
RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2
MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3
INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4
CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5
INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3
HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3
I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.2 TIME BASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.4 SMARTCARD INTERFACE (CRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1
Table of Contents
3/102
13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.3 SUPPLY AND RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.4 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.5 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
14.6 SMARTCARD SUPPLY SUPERVISOR ELECTRICAL CHARACTERISTICS . . . . . . . . 82
14.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 89
15 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 92
16.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 93
16.2 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.3 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
18 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
19 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.1 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.2 USB: TWO CONSECUTIVE SETUP TOKENS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.3 USB BUFFER SHARED MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.4 WDG (WATCHDOG) LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.5 SUPPLY CURRENT IN HALT MODE (SUSPEND) LIMITATIONS . . . . . . . . . . . . . . . . 100
20.6 START-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.7 I/O PORT INPUT HIGH LEVEL (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
21 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
22 ERRATA SHEET ReVISION History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please note that an errata sheet can be found at the end of this document on
page 99
.
ST7SCR
4/102
1 INTRODUCTION
The ST7SCR and ST7FSCR devices are mem-
bers of the ST7 microcontroller family designed for
USB applications. All devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.
The ST7SCR ROM devices are factory-pro-
grammed and are not reprogrammable.
The ST7FSCR versions feature dual-voltage
Flash memory with Flash Programming capability.
They operate at a 4MHz external oscillator fre-
quency.
Under software control, all devices can be placed
in WAIT or HALT mode, reducing power consump-
tion when the application is in idle or stand-by
state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
The devices include an ST7 Core, up to 16 Kbytes
of program memory, up to 512 bytes of user RAM,
up to 35 I/O lines and the following on-chip periph-
erals:
USB full speed interface with 7 endpoints, pro-
grammable in/out configuration and embedded
3.3V voltage regulator and transceivers (no ex-
ternal components are needed).
ISO7816-3 UART interface with Programmable
Baud rate from 372 clock pulses up to 11.625
clock pulses
Smartcard Supply Block able to provide pro-
grammable supply voltage and I/O voltage levels
to the smartcards
Low voltage reset ensuring proper power-on or
power-off of the device (selectable by option)
Watchdog Timer
8-bit Timer (TBU)
Figure 1. ST7SCR Block Diagram
8-BIT CORE
ALU
A
DDRE
S
S
A
ND DA
T
A
B
U
S
OSCIN
OSCOUT
PA6
4MHz
CONTROL
RAM
(512 Bytes)
PROGRAM
(16K Bytes)
MEMORY
8-BIT TIMER
LVD
V
PP
USBDP
USBDM
USBVCC
PORT C
PC[7:0]
PB[7:0]
PA[5:0]
SUPPLY
MANAGER
PLL
OSCILLATOR
USB
PORT B
PORT A
USB
DATA
BUFFER
(256 bytes)
DIVIDER
8 MHz
3V/1.8V Vreg
DC/DC
CRDDET
CRDIO
CRDC4
CRDC8
CRDRST
CRDCLK
PD[7:0]
ISO7816 UART
PORT D
CONVERTER
CRDVCC
SELF
WATCHDOG
LED
LED[3:0]
or 4 MHz
48 MHz
DIODE
1
ST7SCR
5/102
2 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout
WAK
UP2
/PA2
WAK
UP2
/PA3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
OS
CIN
OSC
OUT
CRD
DET
VDD
WA
KUP2
/ICCD
ATA
/PA0
W
AKUP
2/ICC
CLK
/PA1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24
29 30 31 32
25 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C4
CRDIO
C8
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
CRDCLK
NC
PA6
V
PP
PC7/WAKUP1
PC6/WAKUP1
PC5/WAKUP1
PC4/WAKUP1
PC3/WAKUP1
PC2/WAKUP1
PC1/WAKUP1
PC0/WAKUP1
GND
VDD
NC
DP
DM
LED0
SE
LF1
SE
LF2
PA
5
PA
4
NC
NC
LE
D3
LE
D2
LE
D1
VD
D
VD
DA
US
BVcc
CR
DVC
C
GN
D
GN
DA
DI
ODE
CRDRST
NC = Not Connected
1
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