January 2000
1/18
Rev. 2.2
ST92R195B
ROMLESS HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
s
Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s
0
C to +70
C Operating Temperature Range
available
s
Up to 24 MHz Operation @ 5V
10%
s
Minimum instruction cycle time: 375ns at
16 MHz internal clock
s
4 Mbytes address space
s
256 Bytes RAM of Register file (accumulators or
index registers)
s
1024 Bytes of on-chip static RAM
s
8K Bytes of TDSRAM (Teletext and Display
Storage RAM)
s
80-lead QFP package
s
23 fully programmable I/O pins
s
Serial Peripheral Interface
s
Flexible Clock controller for OSD, Data Slicer
and Core clocks running from one single low
frequency external crystal.
s
Enhanced Display Controller with 26 rows of
40/80 characters
Serial and Parallel attributes
10x10 dot Matrix, 512 ROM characters, defin-
able by user
4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
s
Teletext unit, including Data slicer, Acquisition
Unit and 8 Kbytes TDSRAM for Data Storage
s
VPS and Wide Screen Signalling slicer
s
Integrated Sync Extractor and Sync Controller
s
14-bit Voltage Synthesis for tuning reference
voltage
s
Up to 8 External Interrupts plus 1 non-maskable
interrupt
s
8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
s
16-bit Watchdog timer with 8-bit prescaler
s
One 16-bit standard timer with 8-bit prescaler
s
4-channel
Analog-to-Digital converter; 5-bit
guaranteed
s
Rich instruction set and 14-Addressing modes
Versatile Development Tools, including Assem-
bler, Linker, C-compiler, Archiver, Source Level
Debugger and Hardware Emulators with Real-
Time Operating System available from third par-
ties
Device Summary
Device
Program
Memory
TDS
RAM
VPS/
WSS
Package
ST92R195B9
ROMLESS
8K
Yes
PQFP80
QFP80
1
2/18
ST92R195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92R195B microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The ST92R195B MCU supports
low power consumption and low voltage operation
for power-efficient and low-cost embedded sys-
tems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registers of the on-
chip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (LP WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen
(the clock is
also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 23 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:
Voltage Synthesis
VPS/WSS Slicer
Teletext Slicer
Teletext Display RAM
OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 char-
acter set. The character resolution is 10x10 dots.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colours, character size and fringe
background. Parallel attributes can be used to se-
lect additional foreground and background colors
and underline on a character by character basis.
1.1.6 Teletext and Display RAM
The internal 8k Teletext and Display storage RAM
can be used to store Teletext pages as well as Dis-
play parameters.
3/18
ST92R195B - GENERAL DESCRIPTION
INTRODUCTION (Cont'd)
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers using a single ex-
ternal crystal are used to extract the Teletext, VPS
and WSS information from the video signal. Hard-
ware Hamming decoding is provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is out-
put on one of two separate output pins.
1.1.9 PWM Output
Control of TV settings is able to be made with up to
eight 8-bit PWM outputs, with a frequency maxi-
mum of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency oper-
ation can be programmed.
1.1.10 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices via the SPI, or I C bus communication
standards. The SPI uses a single line for data in-
put and output. A second line is used for a syn-
chronous clock signal.
1.1.11 Standard Timer (STIM)
The ST92R195B has one Standard Timer that in-
cludes a programmable 16-bit down counter and
an associated 8-bit prescaler with Single and Con-
tinuous counting modes.
1.1.12 Analog/Digital Converter (ADC)
In addition there is a 4 channel Analog to Digital
Converter with integral sample and hold, fast
5.75
s conversion time and 6-bit guaranteed reso-
lution.
4/18
ST92R195B - GENERAL DESCRIPTION
Figure 1. ST92R195B Block Diagram
MEMORY
BUS
I/O
PORT 0
REGISTER
BUS
VOLTAGE
SYNTHESIS
PWM
D/A CON-
VERTER
SPI
I/O
PORT 4
I/O
PORT 5
DATA
SLICER
& ACQUI-
SITIO N
UNIT
SYNC.
EXTRAC-
TION
8 Kbytes
TDSRAM TRI
1 Kbyte
RAM
STANDARD
TIMER
TIMI NG AND
CLOCK CTRL
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
I/O
PORT 2
ADC
CVBS1
I/O
PORT 3
SYNC
CONTROL
VSYNC
HSYNC/CSYNC
ON
SCREEN
DISPLAY
FREQ.
MULTIP.
PXFM
NMI
INT[7:0]
256 bytes
Register File
ST9+ CORE
8/16-bit
CPU
Interrupt
Management
RCCU
OSCIN
OSCOUT
RESET
RESETO
P0[2:0]
WSCR
WSCF
CVBS2
R/G/B/FB
PWM[7:0]
SDO/SDI
SCK
STOUT
MMU
MCFM
TXCF
TSLU
AIN[4:1]
VSO[2:1]
EXTRG
P2[5:0]
P4[7:0]
P5[1:0]
P3[7:4]
CSO
HT
All alternate functions
(Italic characters)
are mapped on Ports 0, 2, 3, 4 and 5
2
8
4
6
3
External
Memory I/F
ADDR[15:0]
DAT[7:0]
ASN
RWN
DSN
MMU[5:0]
5/18
ST92R195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
ADDR[15:0] External memory interface address
bus.
CVBS1 Composite video input signal for the Tele-
text slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
CVBSO, JTDO, JTCK Test pins: leave floating.
DAT[7:0] External memory interface data bus.
DSN Data strobe for external memory interface.
FB
Fast Blanking. Video analog DAC output.
GND Digital circuit ground.
GNDA Analog circuit ground (must be tied exter-
nally to digital GND).
GNDM External memory interface ground.
HSYNC/CSYNC
Horizontal/Composite sync. Hori-
zontal or composite video synchronisation input to
OSD. Positive or negative polarity.
JTRST0 Test pin: must be tied to GND.
MCFM Analog pin for the display pixel frequency
multiplier.
MMU[5:0] External memory interface MMU seg-
ment bus
OSCIN, OSCOUT
Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
RESET
Reset (input, active low). The ST9+ is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B
Red/Green/Blue. Video color analog DAC
outputs.
RWN Read/Write strobe for external memory in-
terface.
TEST0 Test pin: must be tied to V
DDA
.
TXCF Analog pin for the teletext PLL.
V
DD
Main power supply voltage (5V
10%, digital)
V
DDA
Analog power supply (must be tied external-
ly to V
DDA
).
V
DDM
External memory interface power supply.
VSYNC
Vertical Sync. Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
WSCF, WSCR Analog pins for the VPS/WPP slic-
er. These pins must be tied to ground or not con-
nected.
P0[2:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]-
I/O
Port Lines (Input/Output, TTL or CMOS compati-
ble). 23 lines grouped into I/O ports, bit program-
mable as general purpose I/O or as Alternate func-
tions (see I/O section).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
Each pin of the I/O ports of the ST92R195B may
assume software programmable Alternate Func-
tions as shown in the Pin Configuration drawings.
Table 1. shows the Functions allocated to each I/O
Port pin.
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