AI01063B

VCC

ST95P04

HOLD

VSS

Figure 1. Logic Diagram

ST95P04

SERIAL ACCESS SPI BUS 4K (512 x 8) EEPROM

NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 3V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
1 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
The ST95P04 will be replaced shortly by the
updated version ST95040

DESCRIPTION

The ST95P04 is a 4K bit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON's High Endurance Single Polysili-
con CMOS technology. The 4K bit memory is or-
ganised as 32 pages of 16 bytes. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q). The device connected to the bus is selected
when the chip select input (S) goes low. Commu-
nications with the chip can be interrupted with a
hold input (HOLD). The write operation is disabled
by a write protect input (W).

Serial Clock

Serial Data Input

Serial Data Output

Chip Select

Write Protect

HOLD

Hold

Supply Voltage

Ground

Table 1. Signal Names

SO8 (M)

PSDIP8 (B)

0.25mm Frame

June 1996

1/16

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

40 to 85

STG

Storage Temperature

65 to 150

LEAD

Lead Temperature, Soldering

(SO8 package)
(PSDIP8 package)

40 sec
10 sec

215
260

Output Voltage

0.3 to V

+0.6

Input Voltage

0.3 to 6.5

Supply Voltage

0.3 to 6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

4000

Electrostatic Discharge Voltage (Machine model)

(3)

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and
other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

)

3. EIAJ IC-121 (Condition C) (200pF, 0

)

Table 2. Absolute Maximum Ratings

(1)

SIGNALS DESCRIPTION

Serial Output (Q). The output pin is used to trans-
fer data serially out of the ST95P04. Data is shifted
out on the falling edge of the serial clock.

Serial Input (D). The input pin is used to transfer
data serially into the device. It receives instructions,
addresses, and data to be written. Input is latched
on the rising edge of the serial clock.

Serial Clock (C). The serial clock provides the
timing of the serial interface. Instructions, ad-
dresses, or data present at the input pin are latched

on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.

Chip Select (S). This input is used to select the
ST95P04. The chip is selected by a high to low
transition on the S pin when C is at '0' state. At any
time, the chip is deselected by a low to high transi-
tion on the S pin when C is at '0' state. As soon as
the chip is deselected, the Q pin is at high imped-
ance state. This pin allows multiple ST95P04 to
share the same SPI bus. After power up, the chip
is at the deselect state. Transitions of S are ignored
when C is at '1' state.

VSS

HOLD

VCC

AI01064B

ST95P04

Figure 2A. DIP Pin Connections

AI01065C

VSS

HOLD

VCC

ST95P04

Figure 2B. SO Pin Connections

2/16

ST95P04

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Figure 4. AC Testing Input Output Waveforms

Input Rise and Fall Times

50ns

Input Pulse Voltages

0.2V

to 0.8V

Input and Output Timing
Reference Voltages

0.3V

to 0.7V

AC MEASUREMENT CONDITIONS

Note that Output Hi-Z is defined as the point where data
is no longer driven.

Symbol

Parameter

Min

Max

Unit

Input Capacitance (D)

Input Capacitance (other pins)

LPF

Input Signal Pulse Width

Note: 1. Sampled only, not 100% tested.

Table 3. Input Parameters

(1)

= 25

C, f = 1 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

Supply Current (Active)

C = 0.1 V

/0.9 V

@ 1 MHz, Q = Open

CC1

Supply Current (Standby)

S = V

, V

= V

or V

= 5.5V

S = V

, V

= V

or V

= 3V

Input Low Voltage

0.3

0.3 V

Input High Voltage

0.7 V

+ 1

Output Low Voltage

= 2mA

0.2 V

Output High Voltage

= 2mA

0.8 V

Table 4. DC Characteristics
(T

= 0 to 70

C or 40 to 85

C; V

= 3V to 5.5V)

4/16

ST95P04

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

Clock Frequency

D.C.

MHz

SLCH

S Setup Time

100

CLSH

S Hold Time

100

Clock High Time

400

Clock Low Time

400

CLCH

Clock Rise Time

CHCL

Clock Fall Time

DVCH

DSU

Data In Setup Time

100

CHDX

Data In Hold Time

100

DLDH

Data In Rise Time

DHDL

Data In Fall Time

HXCH

HSU

HOLD Setup Time

100

CLHX

HOLD Hold Time

100

SHSL

S Deselect Time

400

SHQZ

DIS

Output Disable Time

300

QVCL

Clock Low to Output Valid

400

CLQX

Output Hold Time

QLQH

Output Rise Time

150

QHQL

Output Fall Time

150

HHQX

HOLD High to Output Low-Z

300

HLQZ

HOLD Low to Output High-Z

300

(1)

Write Cycle Time

Note: 1. Not enough characterisation data were available on this parameter at the time of issue this Data Sheet. The typical value is well

below 5ms, the maximum value will be reviewed and lowered when sufficient data is available.

Table 5. AC Characteristics
(T

= 0 to 70

C or 40 to 85

C; V

= 3V to 5.5V)

5/16

ST95P04

AI01072B

HOLD

tCLHX

tHXCH

tCLHX

tHHQX

tHLQZ

Figure 7. Hold Timing

Write Protect (W). This pin is for hardware write
protect. When W is low, non-volatile writes to the
ST95P04 are disabled but any other operation
stays enabled. When W is high, all operations
including non-volatile writes are available. W going
low at any time before the last bit D0 of the data
stream will reset the write enable latch and prevent
programming. No action on W or on the write
enable latch can interrupt a write cycle which has
commenced.

Hold (HOLD). The HOLD pin is used to pause
serial communications with a ST95P04 without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validated by
a high to low transition on HOLD when C is low. To
resume the communications, HOLD is brought high
when C is low. During Hold condition D, Q, and C
are at a high impedance state.

When the ST95P04 is under Hold condition, it is
possible to deselect it. However, the serial commu-
nications will remain paused after a reselect, and
the chip will be reset.

OPERATIONS

All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after

the chip select (S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instruction code, the product must
have been previously selected (S = low). Table 7
shows the instruction set and format for device
operation. When an invalid instruction is sent (one
not contained in Table 7), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don't care.

Write Enable (WREN) and Write Disable (WRDI)

The ST95P04 contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under all the following conditions:
W pin is low
Power on
WRDI instruction executed
WRSR instruction executed
WRITE instruction executed

As soon as the WREN or WRDI instruction is
received by the ST95P04, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.

7/16

ST95P04

Read Status Register (RDSR)

The RDSR instruction provides access to the status
register. The status register may be read at any
time, even during a non-volatile write. As soon as
the 8th bit of the status register is read out, the
ST95P04 enters a wait mode (data on D are not
decoded, Q is in Hi-Z) until it is deselected.

The status register format is as follows:

BP1

BP0

WEL

WIP

BP1, BP0: Read and Write bits
WEL, WIP: Read only bits.

During a non-volatile write to the memory array, all
bits BP1, BP0, WEL, WIP are valid and can be read.
During a non volatile write to the status register, the
only bits WEL and WIP are valid and can be read.
The values of BP1 and BP0 read at that time
correspond to the previous contents of the status
register.

The Write-In-Process (WIP) read only bit indicates
whether the ST95P04 is busy with a write opera-
tion. When set to a '1' a write is in progress, when
set to a '0' no write is in progress.

The Write Enable Latch (WEL) read only bit indi-
cates the status of the write enable latch. When set
to a '1' the latch is set, when set to a '0' the latch is
reset.

The Block Protect (BP0 and BP1) bits indicate the
extent of the protection employed. These bits are
set by the user issuing the WRSR instruction.
These bits are non-volatile.

Write Status Register (WRSR)

The WRSR instruction allows the user to select the
size of protected memory. The ST95P04 is divided

into four 1024 bit blocks. The user may read the
blocks but will be unable to write within the selected
blocks.

The blocks and respective WRSR control bits are
shown in Table 6.

When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S. This
rising edge of S must appear after the 8th bit of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.

Read Operation

The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 of the read
instruction contains address A8 (most significant
address bit). This bit is used to select the first or
second page of the device. Then, the data stored
in the memory at the selected address is shifted out
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock

Status Register Bits

Array Addresses

Protected

BP1

BP0

none

180h - 1FFh

100h - 1FFh

000h - 1FFh

Table 6. Array Addresses Protect

Instruction

Description

Instruction Format

WREN

Set Write Enable Latch

0000 X110

WRDI

Reset Write Enable Latch

0000 X100

RDSR

Read Status Register

0000 X101

WRSR

Write Status Register

0000 X001

READ

Read Data from Memory Array

0000 A011

WRITE

Write Data to Memory Array

0000 A010

Table 7. Instruction Set

Notes: A = 1, Upper page selected

A = 0, Lower page selected
X = Don't care

8/16

ST95P04

pulses. The byte address is automatically incre-
mented to the next higher address after each byte
of data is shifted out. When the highest address is
reached (1FFh), the address counter rolls over to
0h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by dese-
lecting the chip. The chip can be deselected at any
time during data output. Any read attempt during a
non-volatile write cycle will be rejected and will
deselect the chip.

Byte Write Operation

Prior to any write attempt, the write enable latch
must have been set by issuing the WREN instruc-
tion. First, the device is selected (S = low) and a
serial WREN instruction byte is issued. Then, the
product is deselected by taking S high. After the
WREN instruction byte is sent, the ST95P04 will
set the write enable latch and then remain in
standby until it is deselected. Then, the write state
is entered by selecting the chip, issuing a one byte
address (A7-A0), and one byte of data. Bit 3 of the
write instruction contains address A8 (most signifi-
cant address bit). S must remain low for the entire
duration of the operation. The product must be
deselected just after the eigth bit of data has been

latched in. If not, the write process is cancelled. As
soon as the product is deselected, the self-timed
write cycle is initiated. While the write is in progress,
the status register may be read to check BP1, BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is close to completion,
the write enable latch is reset.

Page Write Operation

A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes
must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselecting after the first byte of
data, up to 15 additional bytes can be shifted in
prior to deselecting the chip. A page address begins
with address xxxx 0000 and ends with xxxx 1111.
If the address counter reaches xxxx 1111 and the
clock continues, the counter will roll over to the first
address of the page (xxxx 0000) and overwrite any
previous written data. The programming cycle will
only start if the S transition does occur at the clock
low pulse just after the eigth bit of data of a word is
received.

AI01066

9 10 11 12 13 14 15 16 17 18 19

20 21 22 23

HIGH IMPEDANCE

DATA OUT

INSTRUCTION

BYTE ADDRESS

MSB

Figure 8. Read Operation Sequence

9/16

ST95P04

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

INSTRUCTION

BYTE ADDRESS

DATA BYTE 1

AI01069

27 28 29 30 31

8+8N

DATA BYTE 16

9+8N

10+8N

11+8N

12+8N

13+8N

14+8N

15+8N

136

137

138

139

140

141

142

143

DATA BYTE N

DATA BYTE 2

Figure 11. Page Write Operation Sequence

9 10 11 12 13 14 15

INSTRUCTION

AI01433

STATUS REG. OUT

HIGH IMPEDANCE

MSB

Figure 12. RDSR: Read Status Register Sequence

11/16

ST95P04

POWER ON STATE

After a Power up the ST95P04 is in the following
state:
The device is in the low power standby state.
The chip is deselected.
The chip is not in hold condition.
The write enable latch is reset.
BP1 and BP0 are unchanged (non-volatile

bits).

DATA PROTECTION AND PROTOCOL SAFETY
All inputs are protected against noise, see Ta-

ble 3.

Non valid S and HOLD transitions are not

taken into account.

S must come high at the proper clock count in

order to start a non-volatile write cycle (in the
memory array or in the cycle status register).

The Chip Select S must rise during the clock
pulse following the introduction of a multiple of
8 bits.

Access to the memory array during non-vola-

tile programming cycle is cancelled and the
chip is automatically deselected; however, the
programming cycle continues.

After either of the following operations

(WREN, WRDI, RDSR) is completed, the chip
enters a wait state and waits for a deselect.

The write enable latch is reset upon power-up.
The write enable latch is reset when W is

brought low.

INITIAL DELIVERY STATE

The device is delivered with the memory array in a
fully erased state (all data set at all "1's" or FFh).
The block protect bits are initialized to 00.

AI01434

9 10 11 12 13 14 15

HIGH IMPEDANCE

INSTRUCTION

STATUS REG.

Figure 13. WRSR: Write Status Register Sequence

12/16

ST95P04

ORDERING INFORMATION SCHEME

For a list of available options (Package, Temperature Range, etc...) refer to the current Memory Shortform
catalogue.

For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.

Notes: P * Data In strobed on rising edge of the clock (C) and Data Out synchronized from the falling edge of the clock.

3 * Temperature range on special request only.

Data Strobe

P *

D Q

Package

PSDIP8
0.25 mm Frame

SO8
1501mil Width

Temperature Range

0 to 70

40 to 85

3 *

40 to 125

Option

Tape & Reel

Packing

Example: ST95P04 M 6 TR

13/16

ST95P04

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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ST95P04

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