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STA001
November 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
s
SINGLE CHIP RECEIVER FOR SATELLITE
DIGITAL TRANSMISSION
s
SUPERHETERODYNE RECEIVER WITH IF
OUTPUT
s
HIGH INPUT INTERCEPT POINT, LOW
MIXER NOISE
s
54dB IF VGA GAIN RANGE
s
ADJUSTABLE RF GAIN
s
ADJUSTABLE IF GAIN
s
INTEGRATED RF VCO
s
INTEGRATED IF VCO
s
INTEGRATED SYNTHESIZER
s
I
2
CBUS COMPATIBLE PROGRAMMING
INTERFACE
s
UNREGULATED 2.7 V TO 3.3V VOLTAGE
SUPPLY
s
LOW COST EXTERNAL COMPONENTS
DESCRIPTION
The STA001 is an RF IC using STMicroelectronics
HSB2 High Speed Bipolar Technology for one chip so-
lution for the Starman digital satellite radio receiver.
The STA001 is assembled in a TQFP44 package.
The frontend architecture is a double conversion re-
ceiver (see block diagram) .
The chip includes all the RF functions up to low IF
and manages the signals to and from the baseband.
TQFP44
ORDERING NUMBER: STA001
PRODUCT PREVIEW
RF FRONT-END FOR DIGITAL RADIO
BLOCK DIAGRAM
XTAL1, XTAL2
CHANNEL SELECTION
M_CLK
DIFFERENTIAL
SINGLE ENDED
FLT2
TK2, NTK2
LNI, NLNI
SIP, SIN
AGC1, AGC2
OSC
3.68MHz
113.23KHz
SCL
SDA
14.72MHz
PHASE
DETECTOR
CHARGE
PUMP
: 1034
2nd PLL
:130
VCO
1338.14 - 1375.4 MHz
117.0806 MHz
SOP, SON
CHARGE
PUMP
PHASE
DETECTOR
:363.625- 373.75
1st PLL
VCO
V
DD1
V
SS1
RF MIXER
IF1 BUFFER
VGA
IF1 to IF2 MIXER
IF2 BUFFER
FLT1
CE
1.8366 Mhz
TLCK
LOCK
DETECTOR
:4
ENRFOSC
BUFFER
TK1,
NTK1
SUPPLY2 :PLL1 +
Crystal osc .
SUPPLY3 :DIG.
SUPPLY4 :IF1,
IF2 &PLL2
SUPPLY1 :RF
GADJ1, GADJ2
I2CBUS INTERFACE
REF
XOSEL
MUX
PADJ1, PADJ2
LNA
RXI, NRXI
V
DD2
V
SS2
V
DD4
V
SS4
V
DD3
V
SS3
STA001
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PIN CONNECTION (Top view)
PIN FUNCTION
N
Pin
Function
1
VDD1
Positive supply 1
2
SIP
SAW filter input connection
3
SIN
SAW filter input connection
4
VSS1
Negative supply 1
5
LNI
RF input
6
NLNI
RF input
7
VSS1
Negative supply 1
8
NC
Not connected
9
PADJ1
RF gain adjust connection 1
10
PADJ2
RF gain adjust connection 2
11
ENRFOSC RF Oscillator enable
12
VDD2
Positive supply 2
13
TK1
1st PLL tank connection 1
14
NTK1
1st PLL tank connection 2
15
VDD2
Positive supply 2
16
FLT1
1st PLL loop filter connection
17
VSS2
Negative supply 2
18
XTAL1
Quartz oscillator connection 1
19
XTAL2
Quartz oscillator connection 2
20
REF
External optional TCXO input
21
XOSEL
Internal/external XO selection
22
TLCK
Lock detector output
1
2
3
5
6
4
7
8
9
10
17
11
18
19
20
21
22
44
43
42
41
39
40
38
37
36
35
34
28
27
26
24
23
25
33
32
31
29
30
VDD1
SIP
SIN
VSS1
LNI
NLNI
VSS1
N.C.
PADJ1
PADJ2
ENRFOSC
VDD2
TK1
NTK1
VDD2
FLT1
VSS2
XTAL1
XTAL2
REF
XOSEL
TLCK
FLT2
VDD4
TK2
NTK2
VDD4
AGC2
AGC1
VSS4
SON
SOP
VSS4
M_CLK2
M_CLK1
VSS3
SDA
SCL
VDD3
CE
GADJ2
GADJ1
NRXI
RXI
D97AU602
12
13
14
15
16
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STA001
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
23
M_CLK2
Master clock differential output 1
24
M_CLK1
Master clock differential output 2
25
VSS3
Negative supply 3
26
SDA
Data serial input
27
SCL
Clock input
28
VDD3
Positive supply 3
29
CE
Chip Enable
30
GADJ2
IF gain adjust connection 2
31
GADJ1
IF gain adjust connection 1
32
NRXI
Low IF Signal output 2
33
RXI
Low IF Signal output 1
34
FLT2
2nd PLL loop filter connection
35
VDD4
Positive supply 4
36
TK2
2nd PLL tank connection
37
NTK2
2nd PLL tank connection
38
VDD4
Positive supply 4
39
AGC2
VGA control pin 2
40
AGC1
VGA control pin 1
41
VSS4
Negative supply 4
42
SON
SAW filter output connection
43
SOP
SAW filter output connection
44
VSS4
Negative supply 4
Symbol
Parameter
Value
Unit
T
stg
Storage temperature
-40 , +125
C
T
oper
Operative ambient temperature
-20 , +85
C
V
max
Maximum voltage on any pin (with the exception of CE, SDA, SDL)
VDD+0.3
V
V
min
Minimum voltage on any pin
GND-0.3
V
V
maxi
Maximum voltage on pins CE, SDA, SDL
VDD+0.6
V
VDD
max
Minimum/Maximum power supply between VDD
1,2,3,4
and
VSS
1,2,3,4
-0.3/5.5
V
V
esd
Electrostatic Discharge Voltage (ESD)
2
KV
Symbol
Parameter
Value
Unit
VDD
Operating voltage
2.7, 3.3
V
T
jun
Junction temperature
-30, +95
C
PIN FUNCTION (continued)
N
Pin
Function
STA001
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THERMAL DATA
(1) According to JEDEC specification on a 4 layers board
Symbol
Parameter
Value
Unit
R
Th j-amb
Thermal Resistance Junction to Ambient
(1)
45
C/W
ELECTRICAL CHARACTERISTCS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY CURRENTS (T
amb
= 25, VDD = 3V)
I
CC1
Current supplied by
VDD1
Powered circuits: LNA, RF mixer, IF buffer
9.5
14
17
mA
I
CC2
Current supplied by
VDD2
Powered circuits: RF pll, Crystal Oscillator.
ENRFOSC=high (IC RF Osc. Enabled),
XOSEL=high (IC XO Enabled)
ENRFOSC=low (IC RF Osc. Disabled),
XOSEL=high (IC XO Enabled)
ENRFOSC=high (IC RF Osc. Enabled),
XOSEL=low (IC XO Disabled)
ENRFOSC=low (IC RF Osc. Disabled),
XOSEL=low (IC XO Disabled)
8.5
3
7.5
2
10
5
9
4
12
6
11
5
mA
mA
mA
mA
I
CC3
Current supplied by
VDD3
Powered circuits: Digital cells
12
15
18
mA
I
CC4
Current supplied by
VDD4
Powered circuits: VGA, IF mixer, output
buffer, IF pll.
V(AGC1)=V(AGC2)=1.2 (IF
gain
=75dB)
7
11
14
mA
I
TOT
I
CC1
+ I
CC2
+ I
CC3
+ I
CC4
ENRFOSC=high (IC RF Osc. Enabled),
XOSEL=high (IC XO Enabled)
ENRFOSC=low (IC RF Osc. Disabled),
XOSEL=high (IC XO Enabled)
ENRFOSC=high (IC RF Osc. Enabled),
XOSEL=low (IC XO Disabled)
ENRFOSC=low (IC RF Osc. Disabled),
XOSEL=low (IC XO Disabled)
40
34
39
34
50
45
49
44
61
55
60
54
mA
mA
mA
mA
I
TOTSB
Standby I
CC1
+ I
CC2
+
I
CC3
+ I
CC4
CE=GND
100
A
LNA, RF MIXER AND IF1 BUFFER (T = 25, VDD-VSS = 3V)
BW
i
Input signal BW
1452
1492
MHz
BW
o
Output signal BW
114
116.5
MHz
G
V
Voltage Gain
Input LNI, NLNI pins; output SIP, NIP pins.
R
L
= 200
,
PADJ1, PADJ2 floating
28
30
33
dB
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STA001
G
Vtrim
Minimum Voltage Gain
Input LNI, NLNI pins; output SIP, NIP pins.
R
L
= 200
,
R
ext
=0
22
25
28
dB
Z
i
Input impedance R || C
Balanced, LNI, NLNI pins
75
0.2
pF
Z
o
Output impedance
Balanced, SIP, SIN pins
50
R
l
Input Return Loss
LNI, NLNI pins
14
dB
IIP3
Input IP3
Input LNI, NLNI pins; output SIP, NIP pins,
R
l
=200
,
PADJ1, PADJ2 floating
-20
-15
dBm
IIP3
trim
Input IP3 minimum gain
Input LNI, NLNI pins; output SIP, NIP pins,
R
l
=200
,
R
ext
=0 on PADJ1, PADJ2
-19.5
-11.5
dBm
1dBcp
Input 1 dB compression
point
Input LNI, NLNI pins; output SIP, NIP pins,
R
l
=200
,
PADJ1, PADJ2 floating
-26
dBm
1dBcp
tri
m
Input 1 dB compression
point
Input LNI, NLNI pins; output SIP, NIP pins,
R
l
=200
,
PADJ1, PADJ2 R
ext
=0 on PADJ1,
PADJ2
-24
dBm
NF
Noise figure contribution
Measurement conditions: Input LNI, NLNI
pins; output SIP, NIP pins. R
s
=50
,
R
l
=200
,
DSB, PADJ1, PADJ2 floating
5
dB
NF
trim
Noise figure contribution
minimum gain
Measurement conditions: Input LNI, NLNI
pins; output SIP, NIP pins. R
s
=50
,
R
l
=200
,
DSB, R
ext
=0 on PADJ1, PADJ2
6.5
dB
IF1
leak
LO1 to IF1 leakage
-100
-25
dBm
RF
leak
LO1 to RF leakage
-100
-30
dBm
V
DC
LNI, NLNI common mode
DC voltage
AC coupled to the Balun
V
DD
-
1.2
V
DD
-1
V
DD
-
0.8
V
V
DC
SIP, SIN common mode
DC voltage
AC coupled to the SAW filter
V
DD
-
1.3
V
DD
-
1.1
V
DD
-
0.9
V
IF VGA AMPLIFIER, IF MIXER AND OUTPUT BUFFER (T = 25, VDD-VSS = 3V)
BW
i
Input signal BW
114
116.5
MHz
BW
o
Output signal BW
0.6
3.1
MHz
G
min
Minimum gain
Input LNI, NLNI pins; output SIP, NIP pins.
Rl=high impedance V(AGC
1,2
)=0V
32
37
dB
G
max
Maximum gain
Input LNI, NLNI pins; output SIP, NIP pins.
Rl=high impedance V(AGC
1,2
)=3V
71
86
dB
I
AGC
Input current in AGC
control pin
10
A
Z
AGC
AGC pin input
impedance
600
K
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
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