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Электронный компонент: STB90NF3LL

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PRELIMINARY DATA
September 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STB90NF3LL
N-CHANNEL 30V - 0.0048
- 80A D
2
PAK
LOW GATE CHARGE STripFETTM II POWER MOSFET
s
TYPICAL R
DS
(on) = 0.0048
@ 10 V
s
OPTIMAL R
DS(on)
x Qg TRADE-OFF @ 4.5 V
s
CONDUCTION LOSSES REDUCED
s
SWITCHING LOSSES REDUCED
s
SURFACE-MOUNTING D
2
PAK (TO-263)
POWER PACKAGE IN TUBE (NO SUFFIX) OR
IN TAPE & REEL (SUFFIX "T4")
DESCRIPTION
This application specific Power MOSFET is the third
genaration of STMicroelectronis unique "Single Feature
SizeTM" strip-based process. The resulting transistor
shows the best trade-off between on-resistance and gate
charge. When used as high and low side in buck
regulators, it gives the best performance in terms of both
conduction and switching losses. This is extremely
important for motherboards where fast switching and
high efficiency are of paramount importance.
APPLICATIONS
s
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
TYPE
V
DSS
R
DS(on)
I
D
STB90NF3LL
30 V
< 0.0055
80 A(#)
1
3
D
2
PAK
TO-263
(Suffix "T4")
ABSOLUTE MAXIMUM RATINGS
(
)
Pulse width limited by safe operating area.
(#) Value limited by wire bonding
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
30
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
30
V
V
GS
Gate- source Voltage
16
V
I
D
(#)
Drain Current (continuous) at T
C
= 25C
80
A
I
D
Drain Current (continuous) at T
C
= 100C
80
A
I
DM
(
)
Drain Current (pulsed)
320
A
P
tot
Total Dissipation at T
C
= 25C
200
W
Derating Factor
1.3
W/C
T
stg
Storage Temperature
-55 to 175
C
T
j
Max. Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
STB90NF3LL
2/7
THERMAL DATA
ELECTRICAL CHARACTERISTICS (T
CASE
= 25 C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(*)
DYNAMIC
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
0.75
62.5
300
C/W
C/W
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 A, V
GS
= 0
30
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating T
C
= 125C
1
10
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 16 V
100
nA
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
I
D
= 250 A
1
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10 V
I
D
= 40 A
V
GS
= 4.5 V
I
D
= 40 A
0.0048
0.0070
0.0055
0.0090
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs (*)
Forward Transconductance
V
DS
= 15 V
I
D
= 40 A
TBD
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V f = 1 MHz V
GS
= 0
3000
950
190
pF
pF
pF
3/7
STB90NF3LL
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(*)
Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
(
)
Pulse width limited by safe operating area.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
V
DD
= 15 V
I
D
= 40 A
R
G
= 4.7
V
GS
= 4.5 V
(Resistive Load, Figure 3)
30
225
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 24 V I
D
= 80 A V
GS
= 5 V
39
14
21
51
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
V
DD
= 15 V
I
D
= 40 A
R
G
= 4.7
,
V
GS
= 4.5 V
(Resistive Load, Figure 3)
37
24
ns
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(
)
Source-drain Current
Source-drain Current (pulsed)
80
320
A
A
V
SD
(*)
Forward On Voltage
I
SD
= 80 A V
GS
= 0
1.3
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 80 A
di/dt = 100A/s
V
DD
= 10 V
T
j
= 150C
(see test circuit, Figure 5)
55
115
3.5
ns
nC
A
ELECTRICAL CHARACTERISTICS (continued)
STB90NF3LL
4/7
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
5/7
STB90NF3LL
DIM.
mm.
inch.
MIN.
TYP. MAX.
MIN.
TYP. TYP.
A
4.4
4.6
0.173
0.181
A1
2.49
2.69
0.098
0.106
A2
0.03
0.23
0.001
0.009
B
0.7
0.93
0.028
0.037
B2
1.14
1.7
0.045
0.067
C
0.45
0.6
0.018
0.024
C2
1.21
1.36
0.048
0.054
D
8.95
9.35
0.352
0.368
D1
8
0.315
E
10
10.4
0.394
0.409
E1
8.5
0.334
G
4.88
5.28
0.192
0.208
L
15
15.85
0.591
0.624
L2
1.27
1.4
0.050
0.055
L3
1.4
1.75
0.055
0.069
M
2.4
3.2
0.094
0.126
R
0.4
0.015
V2
0
8
0
8
D
2
PAK MECHANICAL DATA