STKM2000 SERIES
2
/2 POLY/2 METAL BiCMOS
MIXED ANALOG-DIGITAL STANDARD CELLS
November 1989
ASIC PRODUCTS DESCRIPTION
s
ADVANCED BICMOS 2
/2 POLY/ 2 METAL
PROCESS
s
TWIN TUB PROCESS
s
HIGH LATCH-UP IMMUNITY
s
POWER SUPPLY :
MAXIMUM RATING : -0.5V TO 12V
OPERATING CONDITIONS : 3V TO 10V
s
MIXED ANALOG - DIGITAL LIBRARY :
ANALOG BIPOLAR LIBRARY
ANALOG CMOS LIBRARY
ANALOG BICMOS LIBRARY
DIGITAL CMOS LIBRARY
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HIGH PROCESS PERFORMANCES:
TRANSITION FREQUENCY, NPN = 6 GHz
VERTICAL PNP = 2, 5 GHz
DIGITAL CMOS OPERATING FREQUENCY :
UP TO 30 MHz
s
CAD SOFTWARE SUPPORT:
FULLY INTEGRATED A.D.S. (ANALOG DE-
SIGN SYSTEM) WITH ANALOG BLOCK GEN-
ERATORS, SWITCHED CAPACITOR FILTER
COMPILER; DIGITAL FUNCTIONS GENER-
ATOR, RAM, ROM, PLA GENERATORS
s
AVAILABILITY OF EEPROM DEVICES, ZENER
DIODE, SCHOTTKY DIODE
With the STKM2000 series, SGS-THOMSON
Microelectronics introduces the "state of the art"
product for analog signal processing, chain from
sensor to actuator.
The introduction of new concepts (cells library and
CAD) opens the design of analog functions and
mixed analog and digital circuits with a safe and
powerful approach. This new ASIC approach is the
combination of innovative :
q
BICMOS process
q
Mixed libraries (ANALOG + DIGITAL)
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Generators and compilers
q
"User friendly" CAD system
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Customer interface
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OPERATING TEMPERATURE RANGE:
COMMERCIAL: 0 TO 70
o
C
INDUSTRIAL: -40 TO 85
o
C
MILITARY: -55 TO 125
o
C
s
PACKAGE OPTIONS:
DIL: PLASTIC OR CERAMIC
SMD: SO, PLCC, QFP
WAFER OR DIE
Figure 1 : The STKM2000 Series, a complete system solution
SENSOR
A
D S P
~
~
~
A
A / D
CONVERTER
D / A
CONVERTER
A
ACTUATOR
BIP : GB = 100MHz
MOS : GB = 10MHz
C(MAX)
12 Bits 1/2 Bit
+
-
f
MAX = 30MHz
15 s
12 Bits 1/2 Bit
+-
15 s
500 mA max.
f = 150kHz
1/10
STKM2000 ARCHITECTURE
Technology
T h e S T K M 20 0 0 S e r ie s de v el ope d by
SGS-THOMSON Microelectronics uses an
advanced BICMOS silicon gate process with dual
polysilicon layers and dual metal layers. This
process is optimized to achieve high performance
in digital CMOS applications. Depending on the
operating supply voltage (10V, or 5V), the CMOS
process behaves as an N-WELL technology
(respectively with 2
gate length or 1.8
gate
length) with operating speeds up to 30MHz.
Thanks to the two metal layers, the digital part of
the circuit can reach high gate density with low
parasitic capacitances.
For analog functions, the STKM2000 series takes
advantage of the bipolar structure:
q
very high speed NPN transistor : f
T
= 6 GHz
q
very high speed vertical PNP
: f
T
= 2.5 GHz
This allows high gain - bandwith operational
amplifier (50 MHz), low noise input amplifier, short
propagation delay comparator, ...
With the same BICMOS process, the analog
CMOS performance come from the high density
CMOS structure with a double poly layer for
accurate capacitors, low consumption CMOS
amplifier (30
A), CMOS switches, high accuracy
switched capacitor filters (up to 100 kHz for center
frequency).
STKM2000 cell concepts
S G S - T H O M S O N M ic r o el e c t r on i c s h as
predesigned and precharacterized cells which are
selected, placed and interconnected on the chip to
implement digital and analog cells having different
height and supply voltages. In addition some
macrocells are designed as fixed blocks, so called
"hard blocks" : filters, A/D and D/A converters; some
hard blocks are automatically generated and
parametrized from a compiler: S.C. filters, PLA,
RAM, ROM...
STKM2000 chip topology
The chip is optimized versus the cell complexity, in
a row based structure with different heights.
Peripheral cells surround the internal active chip
area to interface with its external environment.
Despite the row based architecture, "hard blocks"
can be implemented with efficient floor planning
organization.
STKM2000 Cell libraries
SGS-THOMSON Microelectronics introduces the
"programmable" library; instead of working with a
finite number of cells of the library, the designer has
now access to an infinite number of functions.
Defining only some properties, the designer is able
to create himself the cells needed for his
application. For example, the following electrical
parameters are accessible and adjustable:
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gain-bandwith product
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phase margins, frequency compensation
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output buffer current
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biasing currents
q
resistor, capacitor fields
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current, source or sink
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adjustable Ron switch resistor
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supply voltage assignment
The analog library is operating in a large voltage
range: 3V to 10V.
The basic analog library contains:
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60 analog CMOS functions
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25 analog BIPOLAR functions
From single transitor to 12 bits A to D converter
(with autocalibration), each setup becomes
possible.
The digital CMOS library uses the same flexibility
with a complete set of basic digital functions
(NAND, NOR, Flip-Flop, ...) and some cell
generators:
q
register, counter, logic comparator, ...
More than 60 digital cells are available.
STKM2000 SERIES
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Figure 2: The STKM2000 Series, a complete system solution
ANALOG LIBRARY
NPN transistor
P input CMOS Op-Amp
Lateral PNP
Crystal oscillator
Substrate PNP
RC oscillator
Isolated PNP
Transconductance
NPN input comparator
Power-on reset
PNP input comparator
(with adjustable threshold and hysteresis)
N input comparator
Analog multiplexer
P input comparator
Voltage to current converter
N-MOS transistor
Voltage reference
P-MOS transistor
8 bits, A/D and D/A converters
NPN high-speed amplifier
12 bits A/D and D/A converters
N input CMOS Op-Amp
DIGITAL LIBRARY
AND, NAND, OR, NOR, inverter
Shift register
Exclusive OR, NOR
Binary counter
D latch
Decimal counter
Input buffer (TTL/CMOS)
Magnitude comparator
Output buffer (TTL/CMOS)
STKM2000 SERIES
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CAD SUPPORT: A.D.S. (Analog Design System)
SGS-THOMSON Microelectronics has introduced
a sophisticated CAD approach to reduce the
development leadtime and to increase design
flexibility and safety.
Programmable cells in the library are defined as:
q
alternative cell or,
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adjustable cell or,
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telescopic cell or,
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parametrisable cell
Some specific parts of the design are automatically
handled by an analog design manager, in order to:
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reduce capture errors
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make unexperienced designer's task easier
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improve schematics lisibility
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check electrical design rules (Analog or Digital)
The Analog Design manager takes into account:
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transconductance block generation
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automatic cell biasing
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unconnected pins and power down processing
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multipower supplies processing
A major step has been made with the introduction
of function generator and compiler approaches to
improve design automation and design efficiency.
Operational amplifier generator
From a generic symbol and some properties,
several parameters of the amplifier will be adjusted:
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Biasing current which controls major parameters
of amplifier (gain-bandwidth, slew rate, power
consumption).
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Frequency compensation which allows to adjust
and optimize the dynamic parameters versus the
capacitive and resistive load.
q
Power down capabilities.
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Supply voltage of the cell.
A specific software manages all these properties
and automatically updates all libraries included in
the design flow: macro models and transistor level
models, footprint, GDS2 layout, LVS netlist.
Figure 3: Analog Design System (A.D.S.) flow
Digital Analog
Symbols
Schematic
Capture
Data Base
Filter Compiler
DIGITAL
Generator
D
Netlist
Extractor
Analog Generator
G
G
Programmable Cells
Generation
G
Behavioral
Models
Top Level
Simulation
SABER
Digital
Models
D
G
Transistor
Models
Place & Route
Cells Boxes
G
Analog
Simulation
ST SPICE
Digital
Simulation
HILO 3
Back Annotation
GDSII File
DRC/LVS
Cells
Layout
G
PG Tape
STKM2000 SERIES
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Filter compiler
From the template defined at the beginning up to
the complete layout, the software handles
automatically the filter synthesis and the layout
compilation:
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evaluation/mathematical analysis
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switched capacitor synthesis
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simulation
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Monte-Carlo analysis
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layout generation
Any kind of filters is available from 2nd up to 12th
order.
Digital cell generator
For a set of basic digital cells, the user has access
to generators which handle the netlists and
interface with the layout tools.
The schematic capture uses a block which is
pr ogr am ma ble ac cor ding t o t he r equired
complexity.
The generator creates a " so-called" soft macrocell
taking into account the complete netlist:
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counters
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shift registers
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magnitude comparators, ...
A part from the software automation, the A.D.S.
CAD tool works around standard softwares.
The CAD approach is compatible with both
approaches:
q
VAX
TM
/VMS operating system
q
SUN
TM
/UNIX operating system
VAX
TM
SUN
TM
Schematic capture
CASS
EDGE
(SILVAR LISCO
TM
)
(CADENCE
TM
)
Logic simulation
HILO 3
MOZART
(GENRAD
TM
)
(SGS-THOMSON)
Analog simulation
ST-SPICE
ST-SPICE
(SGS-THOMSON)
(SGS-THOMSON)
Top level simulation
SABER
SABER
(ANALOGY
TM
)
(ANALOGY
TM
)
Layout
CALMP
(SILVAR LISCO
TM
)
EDGE (CADENCE
TM
)
DRC - LVS
DRACULA
EDGE
(CADENCE
TM
)
(CADENCE
TM
)
STKM2000 SERIES
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