1/31

STLC1511

November 2000

This is preliminary information on a new product now in development. Details are subject to change without notice.

Wide transmit (~80dB) and receive (~69dB)
dynamic range to limit the external filtering
requirements for extended loop reach operation

Programmable tx gain: 0 � -32dB in 2dB steps

14-bit D/A converter in transmit path

Programmable rx gain: 0 �40dB in 0.5dB steps

12-bit A/D converter in receive path

Integrated phase-locked loop with an externall
LC or crystal oscillator

Low power: 300mW @ 5.0V

64-pin TQFP package

1.0 GENERAL DESCRIPTION

The STLC1511 G.lite Analog Front End (AFE) chip
implements the analog transceiver functions required
in both a central office modem and a customer
premise modem. It connects the digital modem chip
with the loop driver and hybrid balance circuits. The
STLC1511 has been designed with excellent dynam-
ic range in order to greatly reduce the external filter-
ing requirements at the front end. The AFE chip and
its companion digital chip along with a loop driver, im-
plement the complete G.992.2 DMT modem solution.

The STLC1511 transmit path consists of a 14-bit
Nyquist rate D/A converter, followed by a program-
mable gain amplifier (TxPGA). The transmit gain is
programmable from 0 to -32dB in 2dB steps.

The STLC1511 receive path contains a buffer ampli-
fier followed by a programmable gain amplifier (RxP-
GA), a low pass anti-aliasing filter, and a 12-bit
Nyquist rate A/D converter. The RxPGA is digitally
programmable from 0 to 40dB in 0.5dB steps.

2.0 PACKAGING AND PIN INFORMATION

2.1 STLC1511 Pin Allocation

The pinout for the STLC1511 is depicted in Figure 1.

TQFP64

ORDERING NUMBER: STLC1511

PRODUCT PREVIEW

NorthenLiteTM G.lite BiCMOS

Analog Front-End Circuit

Figure 1. STLC1511 pinout

28 29 30 31 32

59 58 57 56

53 52 51 50 49

VSSDIGE1

RXSOUT[1]

RXSOUT[0]

CK35M

VDDDIG1

DIGREF

DIGCLK

DTX

VDDDIG2

VSSDIG2

VDDDIGE1

RXDCINP

RXDCINN

RXDCON

RXDCOP

RXINP

RXINN

RXOPIINN

RXOPINP

VCCRXPGA

VEERXPGA

QVEERX

QVEEDAC

TXDADC1

VEEDAC

VCCDAC

VDDESD2

VSSESD2

VEETXPGA

VCCTXPGA

TXON

TXOP

QVEETX

VCCPLL

VEEPLL

FREQ

OSCNB

OSCPB

OSCNE

QVEEBIAS

VEEBIAS

VCCBIAS

V3P75V

IREF50m

TQFP64

22 23 24 25 26

RESETN

TXSIN[0]

TXSIN[1]

FRMCLK

VSSDIG1

ADCDC3

ADCDC2

ADCDC1

VSSESD1

VDDESD1

17 18 19 20 21

OSCPE

VCAP

VSSPLL

QVEEPLL

VDDPLL

QVEEADC

VCCADC

VEEADC

ENB

DRX

STLC1511

2/31

2.2 Pin Description

Table 1. details the pinout assignment for the
STLC1511. The following list gives the different pin
types for the STLC1511.

VDD/VCC - 5V power supply

VEE/VSS - Ground supply

DO/DI - Digital Output/ Digital Input

AO/AI/AIO - Analog Output/ Analog Input/
Analog Input-Output

Table 1. Pin Assignement

Pin #

Pin Name

Pin Type

Pad Type

Description

VDDDIG1

VDD

VDDCO

5V supply (digital) for ADC and DAC

CK35M

TLCHT

35.328MHz serial interface clock input (also used in
Test Mode to test PFD. See Table on page 21)

DIGREF

BT4CR

35.328/17.644MHz reference for Digital ASIC PLL

RXSOUT[0]

BT4CR

Rx serial data (lsb) output

RXSOUT[1]

BT4CR

Rx serial data (msb) output

VSSDIGE1

VSS

VSSE

Ground for digital output drivers

VSSDIG2

VSS

VSSCO

Ground supply for digital interface, serial interface

VDDDIGE1

VDD

VDDE

5 V supply for digital output drivers

VDDDIG2

VDD

VDDCO

5 V supply for digital interface, serial interface

DTX

BT4CR

Data Output for digital interface

DIGCLK

TLCHT

35.328MHz clock input for digital interface

ENB

TLCHT

Enable input for digital interface

DRX

TLCHT

Data Input for digital interface

VEEADC

VEE

VSSCO

Ground for ADC

VCCADC

VCC

VDDCO

5 V supply for ADC

QVEEADC

VEE

VSSCO

Quiet ground for ADC circuitry

ADCDC3

AIO

ANA

ADC reference decoupling (3.75 V) 0.1uF

ADCDC2

AIO

ANA

ADC reference decoupling (2.5 V) 0.1uF

ADCDC1

AIO

ANA

ADC reference decoupling (1.25 V) 0.1uF

VSSESD1

VSS

VSSA

Ground for ESD ring

VDDESD1

VDD

VDDA

5 V supply for ESD ring

RXDCINP

ANA

RxPGA positive input from DC blocking capacitor

RXDCINN

ANA

RxPGA negative input from DC blocking capacitor

RXDCON

ANA

RxPGA negative output to DC blocking capacitor

RXDCOP

ANA

RxPGA positive output to DC blocking capacitor

RXINN

ANA

Rx negative input (AC coupled)

RXINP

ANA

Rx positive input (AC coupled)

3/31

STLC1511

RXOPINN

ANA

Rx opamp negative input (must be DC coupled)

RXOPINP

ANA

Rx opamp positive input (must be DC coupled)

VCCRXPGA

VCC

VDDCO

5V supply for RxPGA

VEERXPGA

VEE

VSSCO

Ground for RxPGA

QVEERX

VEE

VSSCO

Quiet ground for Rx circuitry

QVEEPLL

VEE

VSSCO

Quiet ground for PLL circuitry

VSSPLL

VSS

VSSCO

Ground for Oscillator

VDDPLL

VDD

VDDCO

5 V supply for Oscillator

VCAP

ANA

Charge pump output to varactor

OSCPE

AIO

ANA

Oscillator I/O (emitter)

OSCPB

AIO

ANA

Oscillator I/O (base)

OSCNB

AIO

ANA

Oscillator I/O (base)

OSCNE

AIO

ANA

Oscillator I/O (emitter)

FREF

ANA

2.56 MHz PLL input reference/ 35.328 MHz clock
input

VEEPLL

VEE

VSSCO

Ground for oscillator

VCCPLL

VCC

VDDCO

5 V supply for oscillator

V3P75V

AIO

ANA

3.75V output from Bandgap to 0.22mF capacitor

IREF50m

AIO

ANA

External resistor for bias current R=2.5V/
50mA=50kohm

VCCBIAS

VCC

VDDCO

5V supply for biasing

VEEBIAS

VEE

VSSCO

Ground for biasing

QVEEBIAS

VEE

VSSCO

Quiet ground for bias circuitry

QVEETX

VEE

VSSCO

Quiet ground for Tx circuitry

TXOP

ANA

Tx positive output

TXON

ANA

Tx negative output

VCCTXPGA

VCC

VDDCO

5V supply for TxPGA

VEETXPGA

VEE

VSSCO

Ground for TxPGA

VDDESD2

VDD

VDDA

5V supply for ESD ring

VSSESD2

VSS

VSSA

Ground for ESD ring

VCCDAC

VCC

VDDCO

5V supply for DAC

VEEDAC

VEE

VSSCO

Ground for DAC

TXDADC1

AIO

ANA

DAC reference (2.5V) 0.1uF

Table 1. Pin Assignement

Pin #

Pin Name

Pin Type

Pad Type

Description

STLC1511

4/31

QVEEDAC

VEE

VSSCO

Quiet ground for DAC circuitry

RESETN

TLCHT

ResetN for the AFE

TXSIN[0]

TLCHT

Tx serial data (lsb) input

TXSIN[1]

TLCHT

Tx serial data (msb) input

FRMCLK

BT4CR

Tx 4.416MHz frame clock reference output

VSSDIG1

VSS

VSSCO

Ground (digital) for ADC and DAC

<1>HCMOS5 guidelines are for 1 pair of power/ground for 4 output drivers (4mA)

<2>Pins 35 and 43 are both connected to the analog VCC supplying the on chip oscillator. Similarly, Pins 34 and 42 are connected

to analog VSS for the oscillator. Supply line inductance is reduced using two pads for VCC (and VSS) in this manner. At the board
level, Pins 35 and 43 should be connected to analog VCC, and pins 34 and 42 should be connected to analog VSS.

Table 1. Pin Assignement

Pin #

Pin Name

Pin Type

Pad Type

Description

3.0 FUNCTIONAL DESCRIPTION

3.1 General Functional Description

The STLC1511 consists of the following functional
blocks:

Transmit Signal Path

Receive Signal Path

Phase Lock Loop and Amplifier for an external
oscillator.

Bias Voltage and Current Generation

Digital Interface

Serial Interface

The transmit path contains the 14-bit digital to analog
converter (DAC) necessary to generate the transmit
signal from a 14-bit digital input word. This transmit
signal is then scaled by the on chip programmable
gain amplifier (TxPGA) from 0 to -32dB in 2dB steps.
The scaled output signal is then driven off chip to the
external filters and power amplifier (PA) which drives
the DMT signal to the subscriber loop. The transmit
path is fully differential but may be used single ended
if both outputs from the TxPGA are terminated cor-
rectly.

The receive path contains an optional unity gain buff-
er followed by a two stage programmable gain ampli-
fier (RxPGA), a 1st order low pass anti-aliasing filter,
and a 12-bit analog to digital converter (ADC). The
RxPGA consists of two stages and the gain is digitally
programmable from 0 to 40dB in 0.5dB steps. The re-
ceive path is fully differential but may be used single
ended provided the other input to the RxPGA is
grounded.

The STLC1511 contains the circuits required to con-

struct a PLL that generates either a 17.644MHz/
35.328 MHz clock from a 2.56 MHz reference clock
when supplied with an external LC or crystal oscilla-
tor and tuning circuit. This clock is supplied to the
both the transmit and receive converters, and the se-
rial interface used to transfer the Rx/Tx data between
the STLC1511 and digital chip. The STLC1511 also
has the ability to be driven directly by an external
35.328MHz clock supplied to the FREF pin.

The bias circuitry contains a bandgap voltage refer-
ence from which the converter references and analog
ground voltage is generated. This block also gener-
ates an accurate current using an external resistor
from which all of the STLC1511 circuits are biased. In
addition, the bias circuitry also generates a 2.5V ref-
erence for the external Vco/Vcxo components and
can be used for other external circuits if necessary.

There is a 4 pin serial digital interface (DTX, DRX,
DIGCLK, ENB) that loads a one of four 8-bit control
register that controls all the programmable features
on the STLC1511. Refer to "Digital Interface And
Memory Map" on page 20 for more information on
the programmability of the AFE.

To facilitate data transfer between the STLC1511
and the digital ASIC (STLC1510), a 2-bit wide serial
interface for the transmit path and a 2-bit wide serial
interface for the receive path is incorporated into the
AFE. This interface consists of two transmit pins (TX-
SIN[0:1]), two receive pins (RXSOUT[1:0]), and the
necessary control signals (FRMCLK, CK35M) to
transmit the required data. For more information See
"Serial Interface" on page 18.

5/31

STLC1511

Figure 2. The block diagram of the STLC1511

3.2 Receive Path Specifications

Note: The first stage of the RxPGA provides a coarse gain of 0/20dB with a differential input or 6/26dB with a
single ended input. The second stage implements a programmable gain from 0dB to 20dB in 0.5dB steps.

i
g

ita

l
I

/
F

Ser

i
a
l
I

/
F

B a nd ga p/
Bias Gen

14 -bit

12 -b it
A D C

D A C

4.416M

35.328M /

8/4

2.56M /35.328M

2.56M

35.328M

(Externa l Clock M ode)

(O scillator M ode)

D I G C L K

E N B

D R X

R X IN N

R X I N P

RXD

XDC

I
P

XDC

I
N

T X SIN [1:0]

F R M C L K

R X S O U T [1:0]

C K 3 5 M

I
R

50U

0.22

T X O P

T X O N

F R E F

V C A P

ETN

E x

O S C N E

O S C P E

O S C P B

O S C N B

D T X

�

D IG R E F

17.622M

R X O P IN P

R X O P I N N

2 /3 /4 /8

PFD

C P

G =1

fp=2M H z

fp= 2M H z

CDC

DCD

CDC

ADC

0.1

0.1u

0.1

0.1u

Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC
based resonator for the CO Oscillator Mode. 35.328 MHz external reference in CO External Clock Mode.

Электронный компонент: STLC1511