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STLC1512

November 2000

This is preliminary information on a new product now in development. Details are subject to change without notice.

Low power architecture -- Class AB, current
drive, output stage through a centre tapped
transformer to facilitate power supply switching
between 5.0V and a lower voltage. (3.3V in the
reference design) This gives a reduction in
power consumption.

480mW power consumption with a typical G.lite
signal.

600mA current driving capability

Positive +5.0V and one lower supply. (3.3V in
the reference design)

Switching power supplies to save power

Thermal overload shutdown

Four programmable receive gains

Opamp for a low pass filter in the receive path

Undedicated opamp with separate power down
control (used as a transmit path filter in the
reference design)

Separate power down control for Tx and Rx
path

48-pin TQFP (7x7x1.4mm) package

1.0 GENERAL DESCRIPTION

The STLC1512 G.lite line driver chip contains the line
driver as well as part of the receive path required in a
central office G.lite modem. It provides an interface
between the AFE chip (STLC1511) and the tele-
phone line. The line driver chip has been designed
with low power consumption, high signal to noise
plus distortion ratio and high current driving capabili-
ty.

TQFP48 (7x7x1.40)

ORDERING NUMBER: STLC1512

PRODUCT PREVIEW

NorthenLiteTM G.lite Loop Driver

Figure 1. Block Diagram

TXANG

RBIAS

RXPD

LPFOUT

LPFIN

REF2P5

DCFBON

DCFBOP

FPN

FPP

PAIP

PAIN

PWRVEEx

PAOPx

BUFFP

BUFFN

PAONx

PGA

RX REF

Buffer

LPF AMP

BIAS

Thermal

Shutdown

Preamp

Power

Stage

Feedback

Amp

OPAMP

TX REF

Buffer

AMPPD
TXPD

PGAIN

PGA1

PGA0

RXANG

DCFBIN

DCFBIP

AMPIP

AMPIN

AMPOUT

PGAOUT

STLC1512

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1.0 GENERAL DESCRIPTION

The line driver transmit path contains a preamplifier
followed by a power output stage. The power stage
has current outputs that directly drive the primary
side of a center tapped transformer.

The receive path contains a programmable gain am-
plifier followed by an opamp which is used with off
chip passive components in an active low pass filter.
The Programmable Grain Amplifier (PGA) has four
steps optimized for the recommended G.lite CO line
interface.

There is also an undedicated opamp which can be
used for active filtering in either the transmit or re-

ceive paths

2.0 PACKAGING AND PIN INFORMATION

2.1 Package Technology

STLC1512 will be packaged in a TQFP 48 package,
according to JEDEC Specification reference MS-
026-BBC.

2.2 STLC1512 Pin Allocation

The pin out for the STLC1512 is depicted in the fol-
lowing Figure 2.

Figure 2. STLC1512 pinout

TQFP48 (7x7x1.4mm)

TXANG

RBIAS

PGA

I
N

XAN

XVC

XVEE

QVEER

PGA0

XVEE

PPD

RXPD

LPFOUT

LPFIN

REF2P5

DCFBON

DCFBOP

FPN

FPP

PAIP

PAIN

XVC

XVE

QVE

I
P

I
N

PWRVEE1

PWRVEE2

PAOP1

PAOP2

BUFFP

BUFFN

PAON1

PAON2

PWRVEE3

PWRVEE4

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STLC1512

2.3 Pin Description

The pin description for the STLC1512 is given in the following Table 1.

Table 1. Pin Description

Pin #

Pin Name

Pin Type

Pin Description

PGAOUT

Rx PGA output (programmable gain amplifier)

PGAIN

Rx PGA input

RXANG

2.5V Rx buffered reference

RXVCC1

VCC

+5.0V supply for Rx path circuitry

RXVCC2

VCC

+5.0V supply for Rx path circuitry

QVEERX

VEE

Quiet ground for the Rx circuitry

RXVEE1

VEE

Ground for Rx path circuitry

RXVEE2

VEE

Ground for Rx path circuitry

PGA0

PGA gain setting control bit 0

PGA1

PGA gain setting control bit 1

TXPD

Tx path power down control (Active low)

AMPPD

Undedicated opamp power down control (Active low)

RXPD

Rx path power down control (Active low)

PWRVEE4

VEE

Power stage ground.

PWRVEE3

VEE

Power stage ground.

PAON2

Tx Power Amplifier Negative output

PAON1

Tx Power Amplifier Negative output

BUFFN

Current generator buffer negative output

BUFFP

Current generator buffer positive output

PAOP2

Tx Power Amplifier Positive output

PAOP1

Tx Power Amplifier Positive output

PWRVEE2

VEE

Power stage ground.

PWRVEE1

VEE

Power stage ground.

Not connected

DCFBIN

Power amp DC feedback amplifier negative input

DCFBIP

Power amp DC feedback amplifier positive input

QVEETX

VEE

Quiet ground for Tx circuitry

TXVEE3

VEE

Ground for Tx path circuitry

TXVEE2

VEE

Ground for Tx path circuitry

TXVEE1

VEE

Ground for Tx path circuitry

TXVCC1

VCC

+5.0V supply for power amp output stage

STLC1512

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TXVCC2

VCC

+5.0V supply for power amp output stage

TXVCC3

VCC

+5.0V supply for Tx path circuitry and bias blocks

AMPOUT

Undedicated opamp output

AMPIN

Undedicated opamp negative input

AMPIP

Undedicated opamp positive input

DCFBON

Power amp DC feedback amplifier negative output

DCFBOP

Power amp DC feedback amplifier positive output

TXANG

2.5V Tx buffered reference

FPP

Fast path positive output

FPN

Fast path negative output

PAIP

Tx Power amplifier positive input

PAIN

Tx Power amplifier negative input

RBIAS

Reference resistor generating bias current

REF2P5

Externally supplied 2.5V reference

Not connected

LPFOUT

LPF (low pass filter) Op Amp output

LPFIN

LPF (low pass filter) Op Amp negative input

<1>The values of the components that are connected to the pins are shown in Figure 11.
<2>If the undedicated opamp is used in the transmit path, AMPPD can be connected to TXPD on the board. If the undedicated opamp

is used in the receive path, AMPPD can be connected to RXPD on the board. This opamp is powered off of TXVCC3.

Table 1. Pin Description

3.0 FUNCTIONAL DESCRIPTION

The STLC1512 consists of the following functional
blocks:

Transmit Signal Path

Receive Signal Path

Thermal Protection

The transmit signal that comes from the AFE is fil-
tered before it reaches the line driver. STLC1512
contains an opamp that can be utilized as part of this
filter. The AMPPD pin allows this op amp to be pow-
ered down independently. The line driver consists of
a preamp followed by a current drive power stage.
The preamplifier provides large open loop gain while
the power stage provides open collector current drive
to allow for single supply switching. The center tap of
the primary side of the transformer is connected to a
supply that can be switched between 5.0V and a low-
er supply to realize power savings on a DMT signal.
The reference design sets this supply at 3.3V. The
line driver can be powered down by a low at the
TXPD pin.

The receive path consists of a Programmable Gain
Amplifier (PGA) and an active low pass filter. The
PGA is programmable in four steps. The active low
pass filter is composed of an on chip op amp and ex-
ternal passive components. The receive signal pass-
es through the PGA, is low pass filtered and then
driven off chip to the AFE chip. Both the PGA and the
opamp can be powered down by RXPD signal.

A thermal protection circuit has also been implement-
ed on the chip to prevent the chip from overheating
under fault conditions.

4.0 SPECIFICATIONS

4.1 Chip Specifications

The cross-talk specifications are based on the as-
sumption that cross-talk should not degrade the
SNDR of the receive signal. If there is receive cross-
talk into the transmit path, this signal will come back
through the hybrid balance and cause noise in the re-
ceive path. If the signal is undistorted it will cause a
small gain and phase error which will not affect per-
formance. If it is distorted it will cause an increased

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STLC1512

noise floor which will degrade the SNDR of the re-
ceive signal.

The same is true of the transmit signal. If the signal is
undistorted it will show up out of band in the receive
path and will not degrade SNDR. However, if the

transmit signal is distorted by the cross-talk mecha-
nism it will show up in the receive band and could re-
duce the SNDR.

The cross-talk numbers are specified from output to
output under maximum gain conditions.

4.2 Power Amplifier Performance

Specifications

The power amplifier must be specified with all of the
external components in the application diagram.
Without these components the amplifier will not func-
tion correctly. Specifications that are measured at the
chip are specified as such in the comments.

Table 3 contains the conditions over which the spec-
ifications in Table 4 apply. The limits on the specifica-
tions in Table are valid over all of the ranges
specified in Table 3. The nominal values of the spec-
ification occur at the nominal value of all of the condi-
tions in Table 3 unless otherwise specified.

...

Table 2. Chip Performance Specifications

Description

min

nom

max

Units

Comments

Rx Cross-Talk into Tx
Undistorted

-55

Measured from the active low pass filter
output in the receive path to tip and ring.

Rx Cross-Talk into Tx
Distorted

-73

Measured from the active low pass filter
output in the receive path to tip and ring.

Tx Cross-talk into Rx
Undistorted

-50

Measured from tip and ring to the active
low pass filter output with the maximum
gain setting in place.

Tx Cross-talk into Rx
Distorted

-86

Measured from tip and ring to the active
low pass filter output with the maximum
gain setting in place.

Table 3. Power Amplifier Performance Limits

Description

min

nom

max

Units

Comments

Gain

19.9

20.1

20.3

Ambient Temperature

-40

Line Impedance

100

160

A nominal chip will have no problem
driving 200

or 50

Supply voltage for TXVCC

4.75

5.0

5.25

<1>Nominal specifications are for nominal bias and process
<2>Maximum and minimum specifications are for worst case process and bias conditions

Электронный компонент: STLC1512