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STLC5466
November 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PRELIMINARY DATA
64 CHANNEL-MULTI HDLC WITH
N X 64KB/S SWITCHING MATRIX ASSOCIATED
s
64 TX HDLCs with broadcasting capability and/
or CSMA/CR function with automatic restart in
case of Tx frame abort
s
64 RX HDLCs including Address
Recognition
s
16 Command/Indicate Channels (4 or 6-bit
primitive)
s
16 Monitor Channels processed in accordance
with GCI or V*
s
256 x 256 Switching Matrix without blocking
and with Time Slot Sequence Integrity and
loopback per bidirectional connection
s
DMA Controller for 64 Tx Channels and 64 Rx
Channels
s
HDLCs AND DMA CONTROLLER ARE
CAPABLE OF HANDLING A MIX OF
LAPD,LAPB, SS7, CAS AND
PROPRIETARY SIGNALLINGS
s
External shared memory access
between DMA Controller and Micro
processor
s
SINGLE MEMORY SHARED BETWEEN
n x MULTI-HDLCs AND SINGLE MICRO
PROCESSOR ALLOWS TO HANDLE n x 64
CHANNELS
s
Bus Arbitration
s
Interface for various 8,16 or 32 bit
Microprocessors with fetch memory
to accelerate the exchanges
between Microprocessor and
SHARED MEMORY
s
SDRAM Controller allows to inter
face up to 16 Megabytes of
Synchronous Dynamic RAM
s
Interrupt Controller to store
automatically events in shared memory
s
Boundary scan for test facility
s
TQFP176 package 24 x 24 x 1.40
#MS-026BGA
s
HCMOS6; 0.35 micron; 3.3volts +/-5%
s
Operating temperature: -40 to +85 /C
DESCRIPTION
The STLC5466 is a Subscriber line interface card
controller for Central Office, Central Exchange, NT2
and PBX capable of handling:
s
16 U Interfaces or
s
2 Megabits line interface cards or
s
16 SLICs (Plain Old Telephone Service) or
s
Mixed analogue and digital Interfaces
(SLICs or U Interfaces) or
s
16 S Interfaces
s
Switching Network with centralized processing.
TQFP176
(Plastic Quad Flat Pack)
ORDERING NUMBER: STLC5466
STLC5466
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TABLE OF CONTENTS
I
PIN INFORMATION................................................................................................................6
I.1
PIN CONNECTIONS ..............................................................................................................6
I.2
PIN DESCRIPTION ................................................................. ..............................................7
I.3
PIN DEFINITION...................................................................... ............................................12
I.3.1
Input Pin Definition................................................................................................................12
I.3.2
Output Pin Definition ............................................................................................................12
I.3.3
Input/Output Pin Definition. ..................................................................................................12
II
BLOCK DIAGRAM ...............................................................................................................13
III
FUNCTIONAL DESCRIPTION .............................................................................................13
III.1
THE SWITCHING MATRIX N X 64 KBITS/S........................................................................13
III.1.1
Function Description .............................................................................................................13
III.1.2
Architecture of the Matrix .....................................................................................................13
III.1.3
Connection Function ............................................................................................................13
III.1.4
Loop Back Function .............................................................................................................15
III.1.5
Delay through the Matrix ......................................................................................................15
III.1.5.1
Variable Delay Mode ........................................................................................................15
III.1.5.2
Sequence Integrity Mode ..................................................................................................15
III.1.6
Connection Memory .............................................................................................................15
III.1.6.1
Description .......................................................................................................................15
III.1.6.2
Access to Connection Memory .........................................................................................15
III.1.6.3
Access to Data Memory....................................................................................................15
III.1.7
Switching at 32 Kbit/s ...........................................................................................................15
III.1.8
Switching at 16 Kbit/s ...........................................................................................................16
III.2
HDLC CONTROLLER.............................................................. ............................................16
III.2.1
Function description .............................................................................................................16
III.2.1.1
Format of the HDLC Frame ..............................................................................................16
III.2.1.2
Composition of an HDLC Frame .......................................................................................16
III.2.1.3
Description and Functions of the HDLC Bytes..................................................................16
III.2.2
CSMA/CR Capability ............................................................................................................17
III.2.3
Time Slot Assigner Memory .................................................................................................17
III.2.4
Data Storage Structure .........................................................................................................18
III.2.4.1
Reception..........................................................................................................................18
III.2.4.2
Transmission.....................................................................................................................18
III.2.4.3
Frame Relay .....................................................................................................................18
III.2.5
Transparent Modes ..............................................................................................................18
III.2.6
Command of the HDLC Channels ........................................................................................19
III.2.6.1
Reception Control .............................................................................................................19
III.2.6.2
Transmission Control ........................................................................................................19
III.3
C/I AND MONITOR.................................................................. ............................................19
III.3.1
Function Description ............................................................................................................19
III.3.2
GCI and V* Protocol .............................................................................................................19
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III.3.3
Structure of the Treatment ...................................................................................................20
III.3.4
CI and Monitor Channel Configuration..................................................................................20
III.3.5
CI and Monitor Transmission/Reception Command .............................................................20
III.4
SCRAMBLER AND DESCRAMBLER...................................... ............................................20
III.5
CONNECTION BETWEEN "ISDN CHANNELS" AND GCI CHANNELS ..............................20
III.6
MICROPROCESSOR INTERFACE......................................... ............................................21
III.6.1
Description ...........................................................................................................................21
III.6.2
Buffer ...................................................................................................................................21
III.6.2.1
Write FIFO ........................................................................................................................21
III.6.2.2
Read Fetch Memory .........................................................................................................23
III.6.2.3
Definition of the Interface for the different microprocessors..............................................23
III.7
MEMORY INTERFACE ........................................................... ............................................23
III.7.1
Function Description ............................................................................................................23
III.7.2
Choice of memory versus microprocessor and capacity required ........................................23
III.7.3
Memory Cycle .......................................................................................................................23
III.7.4
Memories composed of different circuits ..............................................................................23
III.7.4.1
Memory obtained with 1M x16 SDRAM circuit..................................................................23
III.7.4.2
Memory obtained with 2M x 8 SDRAM circuit...................................................................23
III.7.4.3
Memory obtained with 8M x 8 SDRAM circuit...................................................................23
III.7.4.4
Memory obtained with 4M x 16 SDRAM circuit.................................................................24
III.8
BUS ARBITRATION ................................................................ ............................................24
III.9
CLOCKS .................................................................................. ............................................24
III.9.1
Clock Distribution Selection and Supervision .......................................................................24
III.9.2
VCXO Frequency Synchronization .......................................................................................24
III.10
INTERRUPT CONTROLLER................................................... ............................................25
III.10.1
Description ........................................................................................................... ................25
III.10.2
Operating Interrupts (INT0 Pin)........................................................................................ .....25
III.10.3
Time Base Interrupts (INT1 Pin) ........................................................................................ ...25
III.10.4
Emergency Interrupts (WDO Pin) ......................................................................................... 25
III.10.5
Interrupt Queues ..................................................................................................................25
III.11
WATCHDOG............................................................................ ............................................25
III.12
RESET ..................................................................................... ............................................25
III.13
BOUNDARY SCAN.................................................................. ............................................26
IV
DC SPECIFICATIONS..........................................................................................................27
V
LIST OF REGISTERS ..........................................................................................................29
VI
INTERNAL REGISTERS ......................................................................................................31
VI.1
IDENTIFICATION AND DYNAMIC COMMAND REGISTER... IDCR (00)H .........................31
VI.2
GENERAL CONFIGURATION REGISTER 1 .......................... GCR1 (02)H........................31
VI.3
INPUT MULTIPLEX CONFIGURATION REGISTER 0............ IMCR0 (04)H.......................33
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VI.4
INPUT MULTIPLEX CONFIGURATION REGISTER 1 ........... IMCR1 (06)H.......................34
VI.5
OUTPUT MULTIPLEX CONFIGURATION REGISTER 0........ OMCR0 (08)H.....................34
VI.6
OUTPUT MULTIPLEX CONFIGURATION REGISTER 1........ OMCR1 (0A)H ....................34
VI.7
SWITCHING MATRIX CONFIGURATION REGISTER ........... SMCR (0C)H.......................35
VI.8
CONNECTION MEMORY DATA REGISTER ......................... CMDR (0E)H.......................37
VI.9
CONNECTION MEMORY ADDRESS REGISTER ................. CMAR (10)H .......................41
VI.10
SEQUENCE FAULT COUNTER REGISTER ......................... SFCR (12)H ........................45
VI.11
TIME SLOT ASSIGNER ADDRESS REGISTER 1.................. TAAR1 (14)H ......................45
VI.12
TIME SLOT ASSIGNER DATA REGISTER 1 ......................... TADR1 (16)H ......................45
VI.13
HDLC TRANSMIT COMMAND REGISTER 1 ......................... HTCR1 (18)H......................46
VI.14
HDLC RECEIVE COMMAND REGISTER 1 ............................ HRCR1 (1A)H .....................48
VI.15
ADDRESS FIELD RECOGNITION ADDRESS REGISTER 1 . AFRAR1 (1C)H ...................50
VI.16
ADDRESS FIELD RECOGNITION DATA REGISTER 1 ......... AFRDR1 (1E)H ...................50
VI.17
FILL CHARACTER REGISTER 1 ............................................ FCR1 (20)H ........................51
VI.18
GCI CHANNELS DEFINITION REGISTER 0 ......................... GCIR0 (22)H.......................51
VI.19
GCI CHANNELS DEFINITION REGISTER 1 .......................... GCIR1 (24)H.......................51
VI.20
GCI CHANNELS DEFINITION REGISTER 2 .......................... GCIR2 (26)H.......................52
VI.21
GCI CHANNELS DEFINITION REGISTER 3 .......................... GCIR3 (28)H.......................52
VI.22
TRANSMIT COMMAND / INDICATE REGISTER .................. TCIR (2A)H .........................52
VI.23
TRANSMIT MONITOR ADDRESS REGISTER....................... TMAR (2C)H .......................53
VI.24
TRANSMIT MONITOR DATA REGISTER .............................. TMDR (2E)H .......................54
VI.25
TRANSMIT MONITOR INTERRUPT REGISTER.................... TMIR (30)H .........................55
VI.26
MEMORY INTERFACE CONFIGURATION REGISTER ......... MICR (32)H.........................55
VI.27
INITIATE BLOCK ADDRESS REGISTER 1 ........................... IBAR1 (34)H .......................56
VI.28
INTERRUPT QUEUE SIZE REGISTER ................................. IQSR (36)H .........................56
VI.29
INTERRUPT REGISTER ........................................................ IR (38)H ..............................57
VI.30
INTERRUPT MASK REGISTER.............................................. IMR (3A)H...........................58
VI.31
TIMER REGISTER 1 ............................................................... TIMR1 (3C)H ......................59
VI.32
TEST REGISTER .................................................................... TR (3E)H.............................59
VI.33
GENERAL CONFIGURATION REGISTER 2 .......................... GCR2 (42)H........................60
VI.34
SPLIT FETCH MEMORY REGISTER ..................................... SFMR (4E)H .......................61
VI.35
TIME SLOT ASSIGNER ADDRESS REGISTER 2.................. TAAR2 (54)H ......................62
VI.36
TIME SLOT ASSIGNER DATA REGISTER 2 ......................... TADR2 (56)H ......................62
VI.37
HDLC TRANSMIT COMMAND REGISTER 2 ........................ HTCR2 (58)H......................63
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VI.38
HDLC RECEIVE COMMAND REGISTER 2 ........................... HRCR2 (5A)H .....................65
VI.39
ADDRESS FIELD RECOGNITION ADDRESS REGISTER 2 AFRAR2 (5C)H ...................67
VI.40
ADDRESS FIELD RECOGNITION DATA REGISTER 2 ......... AFRDR2 (5E)H ...................67
VI.41
FILL CHARACTER REGISTER 2 ........................................... FCR2 (60)H ........................68
VI.42
SDRAM MODE REGISTER..................................................... SDRAMR (72)H ..................68
VI.43
INITIATE BLOCK ADDRESS REGISTER 2 ........................... IBAR2 (74)H .......................69
VI.44
TIMER REGISTER 2 ............................................................... TIMR2 (7C)H ......................70
VII
EXTERNAL REGISTERS.....................................................................................................71
VII.1
INITIALIZATION BLOCK IN EXTERNAL MEMORY (IBA1 AND IBA2)
71
VII.2
RECEIVE DESCRIPTOR.........................................................
72
VII.2.1
Bits written by the Microprocessor only ...............................................................................72
VII.2.2
Bits written by the Rx DMAC only ........................................................................................72
VII.2.3
Receive Buffer .....................................................................................................................73
VII.3
TRANSMIT DESCRIPTOR ...................................................... ............................................73
VII.3.1
Bits written by the Microprocessor only ...............................................................................73
VII.3.2
Bits written by the Tx DMAC only ........................................................................................74
VII.3.3
Transmit Buffer ....................................................................................................................74
VII.4
RECEIVE & TRANSMIT HDLC FRAME INTERRUPT ............ ............................................75
VII.5
RECEIVE COMMAND / INDICATE INTERRUPT.................... ............................................76
VII.5.1
Receive Command / Indicate Interrupt when TSV = 0 .........................................................76
VII.5.2
Receive Command / Indicate Interrupt when TSV = 1 .........................................................77
VII.6
RECEIVE MONITOR INTERRUPT.......................................... ............................................77
VII.6.1
Receive Monitor Interrupt when TSV = 0 .............................................................................77
VII.6.2
Receive Monitor Interrupt when TSV = 1 .............................................................................78
VIII
TQFP176 PACKAGE MECHANICAL DATA .......................................................................79
IX
FIGURES AND TIMING........................................................................................................80
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