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December 2002
s
100ps PART-TO-PART SKEW
s
50ps BANK SKEW
s
DIFFERENTIAL DESIGN
s
MEETS LVDS SPEC. FOR DRIVER
OUTPUTS AND RECEIVER INPUTS
s
REFERENCE VOLTAGE AVAILABLE
OUTPUT V
BB
s
LOW VOLTAGE V
CC
RANGE OF 2.375V TO
2.625V
s
HIGH SIGNALLING RATE CAPABILITY
(EXCEEDS 700MHz)
s
SUPPORT OPEN, SHORT, AND
TERMINATED INPUT FAIL-SAFE (LOW
OUTPUT STATE)
s
PROGRAMMABLE DRIVERS POWER OFF
CONTROL
DESCRIPTION
The STLVD210 is a low skew programmable
1-to-5 dual differential LVDS driver, designed with
clock distribution in mind. The LVDS input signals
can be either differential or single-ended if the
VBB output is used.
The STLVD210 is provided with a 11 bit shift
register with a serial in and a Control Register.
The purpose is to enable or power off each output
clock channel and to select the clock input. The
STLVD210 is specifically designed, modelled and
produced with low skew as the key goal. Optimal
design and layout serve to minimize gate to gate
skew within a device. The net result is a
dependable guaranteed low skew device.
The STLVD210 can be used for high performance
clock distribution in 2.5V systems with LVDS
levels. Designers can be take advantage of the
device's performance to distribute low skew
clocks across the backplane or the board.
ORDERING CODES
Type
Temperature
Range
Package
Comments
STLVD210BF
-40 to 85 C
TQFP32 (Tray)
250 parts per Tray
STLVD210BFR
-40 to 85 C
TQFP32 (Tape & Reel)
2400 parts per reel
STLVD210
DIFFERENTIAL LVDS CLOCK DRIVER
TQFP32
STLVD210
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PIN CONFIGURATION
PIN DESCRIPTION
PlN N
SYMBOL
NAME AND FUNCTION
1
CK
Control Register Clock
2
SI
Control Register Serial IN/CLK_SEL
3, 4, 6, 7
CLKn/CLKn
LVDS CLK Inputs
5
V
BB
Reference Voltage Output
8
EN
Device Enable/Program
9, 25
GND
GROUND
10, 11, 12, 13, 14, 15, 17,
18, 19, 20, 21, 22, 23, 24,
26, 27, 28, 29, 30, 31
Qn0:4/Qn0:4
LVDS
16, 32
V
CC
Supply Voltage
STLVD210
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LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
THERMAL DATA
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.3 to 2.8
V
V
I
Input Voltage
-0.2 to (V
CC
+0.2)
V
V
O
Output Voltage
-0.2 to (V
CC
+0.2)
V
I
OSD
Driver Short Circuit Current
Continuous
ESD
Electrostatic Discharge (HBM 1.5K
,
100pF)
>2
KV
Symbol
Parameter
Value
Unit
R
Tj-c
Thermal Resistance Junction-Case
13
C/W
Symbol
Parameter
Min
TYP
Max
Unit
V
CC
Supply Voltage
2.375
2.625
V
V
IC
Receiver Common Mode Input Voltage
0.5(V
ID
)
2-0.5(V
ID
)
V
T
OPR
Operating Free-Air Temperature Range
-40
85
C
T
J
Operating Junction Temperature
-40
105
C
STLVD210
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DRIVER ELECTRICAL CHARACTERISTICS (T
A
= -40 to 85 C, V
CC
= 2.5V 5%, unless otherwise
noted. Typical values are at T
A
= 25C) (Note 1)
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
RECEIVER ELECTRICAL CHARACTERISTICS (T
A
= -40 to 85 C, V
CC
= 2.5V 5%, unless otherwise
noted. Typical values are at T
A
= 25C) (Note 1)
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
DRIVER ELECTRICAL CHARACTERISTICS (T
A
= -40 to 85 C, V
CC
= 2.5V 5%, unless otherwise
noted. Typical values are at T
A
= 25C) (Note 1)
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
V
OD
Output Differential Voltage
R
L
= 100
400
500
600
mV
V
OD
V
OD
Magnitude Change
30
mV
V
OS
Offset Voltage
1.05
1.15
1.25
V
V
OS
V
OS
Magnitude Change
30
mV
I
OS
Output Short Circuit Current V
O
= 0V
15
30
mA
V
OD
= 0V
7
15
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
V
IDH
Input Threshold High
100
mV
V
IDL
Input Threshold Low
-100
mV
I
IN
Input Current
V
I
= 0V
42
100
A
V
I
= V
CC
2
10
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
V
BB
Output Reference Voltage
V
CC
= 2.5 V
I
BB
= 0.5 mA
1.15
1.25
1.35
V
I
CCD
Power Supply Current
All driver enabled and loaded
125
180
mA
All driver disabled
18
25
C
IN
Input Capacitance
V
I
= 0V to V
CC
5
pF
C
OUT
Output Capacitance
5
pF
V
IH
Logic Input High Threshold
V
CC
= 2.5 V
2
V
V
IL
Logic Input Low Threshold
V
CC
= 2.5 V
0.8
V
I
I
Logic Input Current
V
CC
= 2.5 V,
V
IN
= V
CC
or GND
10
A
STLVD210
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LVDS TIMING CHARACTERISTICS (T
A
= -40 to 85 C, V
CC
= 2.5V 5%, unless otherwise noted. Typical
values are at T
A
= 25C) (Note 1)
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
SPECIFICATION OF CONTROL REGISTER
The STLVD210 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose
is to enable or power of each output clock channel. The STLVD210 provides two working modality:
PROGRAMMED MODE (EN=1)
The shift register have a serial input to load the working configuration. Once the configuration is loaded
with 11-clock pulse, another clock pulse loads the configuration into the control register. The first bit on
the serial input line enables the outputs Qb4 and Qb4, the second bit enables the outputs Qb3 and Qb3
and so on. The last bit is the fewer significations. To restart the configuration of the shift register a reset
of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register
can be configured on time after each reset.
STANDARD MODE (EN=0)
In Standard Mode the STLVD210 isn't programmable, all the clock outputs are enabled.
TRUTH TABLE OF STATE MACHINE INPUTS
SERIAL INPUT SEQUENCE
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
t
TLH
Transition Time Low to High
R
L
= 100
,
C
L
= 5 pF
220
300
ps
t
THL
Transition Time High to Low
220
300
ps
t
PHL,
t
PLH
Propagation Delay to Output
2
2.5
ns
f
MAX
Maximum Input Frequency
700
900
MHz
t
SKEW
Bank Skew
50
ps
Part-to-Part Skew
100
Pulse Skew
60
EN
SI
CK
OUTPUT
L
X
X
All Outputs Enable
H
L
First stage stores "L", other stages store the data of previous stage
H
H
First stage stores "H", other stages store the data of previous stage
L
X
Reset of the state machine, Shift register and Control Register
BIT#10
BIT#9
BIT#8
BIT#7
BIT#6
BIT#5
BIT#4
BIT#3
BIT#2
BIT#1
BIT#0
N.A.
Qa0
Qa1
Qa2
Qa3
Qa4
Qb0
Qb1
Qb2
Qb3
Qb4
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