1/10
December 2002
s
MAIN SWITCHES MAX. R
ON
LESS THAN 2
s
PROVIDES 7 AUXILIARY SWITCHES WITH
R
ON
< 75
s
6V
PP
AMPLITUDE OF ANALOG INPUT
SIGNAL
s
DIGITAL INPUTS ARE TTL LEVELS
COMPATIBLE
DESCRIPTION
The STM7E1 consists in 7 identical ISDN E1
channels, each channel corresponding to 4 main
low-resistant switches (a and b) and 2 auxiliary
switches (c and d). The switches positions in all
the channels are identical and controlled by a
unique control resource driven by the digital inputs
Lm, Ls and Sc.
In each channel, the TX and RX lines can be
switched between a Main port or a Spare-port by
the main switches: if both "a" switches are closed
and both "b" switches are open, the Main port is
connected to the line, while if both "a" switches
are open and both "b' switches are closed, the
spare port is connected to the line.
The 2 auxiliary switches enable to close a local
loop between the TX and RX access of a port: if
"c" is closed, the Spare port RX and TX access is
connected between each other to form a local
loop, while if "d" is closed, the Main port RX and
TX access is connected between each other to
form a local loop.
The Spare port is only used for test purpose on the
system
board
while
the
Main
port
is
the
communication
channel.
Consequently,
a
switching from the Main port to the Spare port
occurs very rarely (<10 times a day).
The power supplies of the chip need to be de
coupled properly. This means that at least one
external capacitor C1 must be connected in
between GND and VPOS, one external capacitor
C2 between GND and VNEG, and one external
capacitor C3 between each pair of VNEG and
VPOS.
ORDERING CODES
Type
Temperature
Range
Package
Comments
STM7E1A
-40 to 85 C
TQFP64 (Tray)
160 parts per Tray
STM7E1AR
-40 to 85 C
TQFP64 (Tape & Reel)
1000 parts per reel
STM7E1A
7 E 1 CHANNELS SWITCH ARRAY
TQFP64
STM7E1A
3/10
NOTE 1: All VNEG pins to be connected together on board.
NOTE 2: All VPOS pins to be connected together on board.
31
Rx#6
IOA
Channel 6: RX line
32
Rxs#6
IOA
Channel 6: RX spare port
35
Sc
I
Control digital input
36
Ls
I
Control digital input
37
Lm
I
Control digital input
39
Txm#6
IOA
Channel 6: TX main port
40
Tx#6
IOA
Channel 6: TX line
41
Txs#6
IOA
Channel 6: TX spare port
42
Mode
I
Control Digital Input
43
Rxm#0
IOA
Channel 0: RX main port
44
Rx#0
IOA
Channel 0: RX line
45
Rxs#0
IOA
Channel 0: RX spare port
46
TEST/Sn
I
Channel 6: RX main port
49
Txm#0
IOA
Channel 0: TX main port
50
Tx#0
IOA
Channel 0: TX line
51
Txs#0
IOA
Channel 0: TX spare port
53
Rxm#1
IOA
Channel 1: RX main port
54
Rx#1
IOA
Channel 1: RX line
55
Rxs#1
IOA
Channel 1: RX spare port
57
Txm#1
IOA
Channel 1: TX main port
58
Tx#1
IOA
Channel 1: TX line
59
Txs#1
IOA
Channel 1: TX spare port
61
Rxm#2
IOA
Channel 2: RX main port
62
Rx#2
IOA
Channel 2: RX line
63
Rxs#2
IOA
Channel 2: RX spare port
PlN N
SYMBOL
TYPE
NAME AND FUNCTION
STM7E1A
5/10
DECODING OF FUNCTIONAL MODE 1 (MODE = L)
When closing the main port local loop (Lm high), it is external system responsibility to ensure that the main
port has previously been disconnected from the line (Sc has to be high). There is no internal mechanism
to ensure this.
When closing the spare port local loop (Ls high), it is external system responsibility to ensure that the
spare port has previously been disconnected from the line (Sc has to be high). There is no internal
mechanism to ensure this.
DECODING OF FUNCTIONAL MODE 2 (MODE = H)
C = Closed
O = Open
C = Closed
O = Open
TEST MODE DESCRIPTION (MODE = 0, TEST = 1)
In order to test the main switches (4-point measurement), test modes are foreseen where the main
switches can be controlled independently from each other. One can enter in test mode by controlling the
Sc, Lm and Ls pins according to the following table.
The digital part and auxiliary switches can be tested in functional mode.
Note 1: Although there is an internal pull down in the TEST pin, an external hardware connection from TEST to GND is required on the board
to work in functional, mode.
Main Switches
Sc low
a closed, b open
Main port is connected to the line
Sc high
a open, b closed
Spare port is connected to the line
Auxiliary
Switches
Lm low
d open
Main port local loop open
Lm high
d closed
Main port local loop closed
Ls low
c open
Spare port local loop open
Ls high
c closed
Spare port local loop closed
INPUT
OUTPUTS
TEST/Sn
A_TX
B_TX
L
O
C
H
C
O
INPUTS
OUTPUTS
Sc
Lm
Ls
A_RX
B_RX
c
d
L
L
L
C
C
O
O
L
L
H
C
O
C
O
L
H
L
O
C
O
C
L
H
H
C
O
O
O
H
L
L
O
C
O
O
Signification
Sc
Lm
Ls
A_TX closed
H
H
L
A_RX closed
L
H
L
B_TX closed
H
L
H
B_RX closed
L
L
H
B_TX & c closed
H
L
L
A_RX & d closed
L
L
L
All main switches open
H
H
H
L
H
H
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