1/8
May 2001
STP3NC50
N-CHANNEL 500V - 3
- 2.8A TO-220
PowerMeshTMII MOSFET
s
TYPICAL R
DS
(on) = 3
s
EXTREMELY HIGH dv/dt CAPABILITY
s
100% AVALANCHE TESTED
s
NEW HIGH VOLTAGE BENCHMARK
s
GATE CHARGE MINIMIZED
DESCRIPTION
The PowerMESH
TM
II is
the evolution of the first
generation of MESH OVERLAY
TM.
The layout re-
finements introduced greatly improve the Ron*area
figure of merit while keeping the device at the lead-
ing edge for what concerns swithing speed, gate
charge and ruggedness.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVER
ABSOLUTE MAXIMUM RATINGS
()Pulse width limited by safe operating area
.
TYPE
V
DSS
R
DS(on)
I
D
STP3NC50
500 V
< 4
2.8 A
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
500
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
500
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuos) at T
C
= 25C
2.8
A
I
D
Drain Current (continuos) at T
C
= 100C
1.8
A
I
DM
(1)
Drain Current (pulsed)
11.2
A
P
TOT
Total Dissipation at T
C
= 25C
75
W
Derating Factor
0.6
W/C
dv/dt
Peak Diode Recovery voltage slope
3
V/ns
T
stg
Storage Temperature
60 to 150
C
T
j
Max. Operating Junction Temperature
150
C
(1)I
SD
2.8A, di/dt
100A/s, V
DD
V
(BR)DSS
, T
j
T
JMAX
TO-220
1
2
3
INTERNAL SCHEMATIC DIAGRAM
STP3NC50
2/8
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(1)
DYNAMIC
Rthj-case
Thermal Resistance Junction-case Max
1.67
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300
C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
2.8
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
110
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 A, V
GS
= 0
500
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1
A
V
DS
= Max Rating, T
C
= 125 C
50
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 30V
100
nA
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250A
2
3
4
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 1.4 A
3
4
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 1.4A
2
S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
260
pF
C
oss
Output Capacitance
45
pF
C
rss
Reverse Transfer
Capacitance
5
pF
3/8
STP3NC50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
V
DD
= 250V, I
D
= 1.4 A
R
G
= 4.7
V
GS
= 10V
(see test circuit, Figure 3)
10
10
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 400V, I
D
= 2.8 A,
V
GS
= 10V
10
2.5
4.5
13.5
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 400V, I
D
= 2.8 A,
R
G
= 4.7
,
V
GS
= 10V
(see test circuit, Figure 5)
10
8
20
ns
ns
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
Source-drain Current
2.8
A
I
SDM
(2)
Source-drain Current (pulsed)
11.2
A
V
SD
(1)
Forward On Voltage
I
SD
= 2.8 A, V
GS
= 0
1.6
V
t
rr
Reverse Recovery Time
I
SD
= 2.8A, di/dt = 100A/s,
V
DD
= 100V, Tj = 150C
(see test circuit, Figure 5)
380
ns
Q
rr
Reverse Recovery Charge
2200
nC
I
RRM
Reverse Recovery Current
11.5
A
Safe Operating Area
Thermal Impedence
STP3NC50
4/8
Gate Charge vs Gate-source Voltage
Static Drain-source On Resistance
Transconductance
Transfer Characteristics
Output Characteristics
Capacitance Variations
5/8
STP3NC50
Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
STP3NC50
6/8
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
7/8
STP3NC50
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
0.107
D1
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
0.409
L2
16.4
0.645
L4
13.0
14.0
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.2
6.6
0.244
0.260
L9
3.5
3.93
0.137
0.154
DIA.
3.75
3.85
0.147
0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
STP3NC50
8/8
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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