STPC
ATLAS
X86 Core PC Compatible System-on-Chip for Terminals
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Figure 0-1. Logic Diagram
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POWERFUL x86 PROCESSOR
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64-BIT SDRAM UMA CONTROLLER
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GRAPHICS CONTROLLER
- VGA & SVGA CRT CONTROLLER
- 135MHz RAMDAC
- ENHANCED 2D GRAPHICS ENGINE
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VIDEO INPUT PORT
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VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
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TFT DISPLAY CONTROLLER
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PCI 2.1 MASTER / SLAVE / ARBITER
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ISA MASTER / SLAVE CONTROLLER
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16-BIT LOCAL BUS INTERFACE
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PCMCIA INTERFACE CONTROLLER
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EIDE CONTROLLER
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2 USB HOST HUB INTERFACES
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I/O FEATURES
- PC/AT+ KEYBOARD CONTROLLER
- PS/2 MOUSE CONTROLLER
- 2 SERIAL PORTS
- 1 PARALLEL PORT
- 16 GENERAL PURPOSE I/Os
- IC INTERFACE
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INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
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POWER MANAGEMENT UNIT
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WATCHDOG
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JTAG IEEE1149.1
PBGA516
ST
PC
Atla
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x86
Core
Host
I/F
SDRAM
CTRL
SVGA
GE I/F
VIP
PCI
m/s
LB
ctrl
PCI Bus
ISA
m/s
IPC
PCI
m/s
ISA Bus
CRTC
Cursor
Monitor
IDE
I/F
PMU
wdog
Video
Pipeline
C Key
K Key
LUT
Local Bus
PCMCIA
I/Os
USB
TFT
TFT I/F
Video In
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ATLAS
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Issue 1.0 - July 24, 2002
DESCRIPTION
The STPC Atlas integrates a standard 5th
generation x86 core along with a powerful UMA
graphics/video chipset, support logic including
PCI, ISA, Local Bus, USB, EIDE controllers and
combines them with standard I/O interfaces to
provide a single PC compatible subsystem on a
single device, suitable for all kinds of terminal and
industrial appliances.
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X86 Processor core
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Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
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Can access up to 4GB of external memory.
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8Kbyte unified instruction and data cache
with write back and write through capability.
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Parallel processing integral floating point unit,
with automatic power down.
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Runs up to 133 MHz (X2).
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Fully static design for dynamic clock control.
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Low power and system management modes.
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Optimized design for 2.5V operation.
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SDRAM Controller
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64-bit data bus.
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Up to 90MHz SDRAM clock speed.
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Integrated system memory, graphic frame
memory and video frame memory.
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Supports 8MB up to 128 MB system memory.
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Supports 16-Mbit, 64-Mbit and 128-Mbit
SDRAMs.
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Supports 8, 16, 32, 64, and 128 MB DIMMs.
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Supports buffered, non buffered, and
registered DIMMs
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4-line write buffers for CPU to DRAM and PCI
to DRAM cycles.
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4-line read prefetch buffers for PCI masters.
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Programmable latency
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Programmable timing for SDRAM
parameters.
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Supports -8, -10, -12, -13, -15 memory parts
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Supports memory hole between 1MB and
8MB for PCI/ISA busses.
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32-bit access, Autoprecharge & Power-down
are not supported.
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Enhanced 2D Graphics Controller
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Supports pixel depths of 8, 16, 24 and 32 bit.
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Full BitBLT implementation for all 256 raster
operations defined for Windows.
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Supports 4 transparent BLT modes - Bitmap
Transparency, Pattern Transparency, Source
Transparency and Destination Transparency.
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Hardware clipping
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Fast line draw engine with anti-aliasing.
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Supports 4-bit alpha blended font for anti-
aliased text display.
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Complete double buffered registers for
pipelined operation.
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64-bit wide pipelined architecture running at
90 MHz. Hardware clipping
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CRT Controller
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Integrated 135MHz triple RAMDAC allowing
for 1280 x 1024 x 75Hz display.
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8-, 16-, 24-bit pixels.
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Interlaced or non-interlaced output.
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Video Input port
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Accepts video inputs in CCIR 601/656 mode.
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Optional 2:1 decimator
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Stores captured video in off setting area of
the onboard frame buffer.
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HSYNC and B/T generation or lock onto
external video timing source.
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Video Pipeline
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Two-tap interpolative horizontal filter.
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Two-tap interpolative vertical filter.
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Color space conversion (RGB to YUV and
YUV to RGB).
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Programmable window size.
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Chroma and color keying for integrated video
overlay.
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ATLAS
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TFT Interface
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Programmable panel size up to 1024 by 1024
pixels.
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Support for VGA and SVGA active matrix
TFT flat panels with 9, 12, 18-bit interface (1
pixel per clock).
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Support for XGA and SXGA active matrix
TFT flat panels with 2 x 9-bit interface (2
pixels per clock).
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Programmable image positionning.
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Programmable blank space insertion in text
mode.
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Programmable horizontal and vertical image
expansion in graphic mode.
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One fully programmable PWM (Pulse Width
Modulator) signals to adjust the flat panel
brightness and contrast.
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Supports PanelLink
TM
high speed serial
transmitter externally for high resolution
panel interface.
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PCI Controller
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Compatible with PCI 2.1 specification.
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Integrated PCI arbitration interface. Up to 3
masters can connect directly. External logic
allows for greater than 3 masters.
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Translation of PCI cycles to ISA bus.
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Translation of ISA master initiated cycle to
PCI.
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Support for burst read/write from PCI master.
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PCI clock is 1/2, 1/3 or 1/4 Host bus clock.
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ISA master/slave
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Generates the ISA clock from either
14.318MHz oscillator clock or PCI clock
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Supports programmable extra wait state for
ISA cycles
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Supports I/O recovery time for back to back
I/O cycles.
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Fast Gate A20 and Fast reset.
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Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
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Supports flash ROM.
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Supports ISA hidden refresh.
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Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host
bus.
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Local Bus interface
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Multiplexed with ISA/DMA interface.
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Low latency asynchronous bus
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16-bit data bus with word steering capability.
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Programmable timing (Host clock granularity)
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4 Programmable Flash Chip Select.
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8 Programmable I/O Chip Select.
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I/O device timing (setup & recovery time)
programmable
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Supports 32-bit Flash burst.
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2-level hardware key protection for Flash boot
block protection.
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Supports 2 banks of 32MB flash devices with
boot block shadowed to 0x000F0000.
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Reallocatable Memory space Windows
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EIDE Interface
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Supports PIO
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Transfer Rates to 22 MBytes/sec
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Supports up to 4 IDE devices
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Concurrent channel operation (PIO modes) -
4 x 32-Bit Buffer FIFOs per channel
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Support for PIO mode 3 & 4.
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Individual drive timing for all four IDE devices
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Supports both legacy & native IDE modes
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Supports hard drives larger than 528MB
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Support for CD-ROM and tape peripherals
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Backward compatibility with IDE (ATA-1).
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Integrated Peripheral Controller
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2X8237/AT compatible 7-channel DMA
controller.
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2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
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Three 8254 compatible Timer/Counters.
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Co-processor error support logic.
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Supports external RTC (Not in Local Bus
Mode).
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ATLAS
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Issue 1.0 - July 24, 2002
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PCMCIA interface
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Support one PCMCIA 68-pin standard PC
Card Socket.
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Power Management support.
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Support PCMCIA/ATA specifications.
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Support I/O PC Card with pulse-mode
interrupts.
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USB Interface
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USB 1.1 compatible.
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Open HCI 1.0 compliant.
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User configurable RootHub.
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Support for both LowSpeed and HighSpeed
USB devices.
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No bi-directionnal or Tri-state busses.
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No level sensitive latches.
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System Management Interrupt pin support
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Hooks for legacy device support.
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Keyboard interface
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Fully PC/AT+ compatible
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Mouse interface
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Fully PS/2 compatible
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Serial interface
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15540 compatible
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Programmable word length, stop bits, parity.
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16-bit programmable baud rate generator.
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Interrupt generator.
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Loop-back mode.
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8-bit scratch register.
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Two 16-bit FIFOs.
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Two DMA handshake lines.
Parallel port
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All IEEE Standard 1284 protocols supported:
Compatibility, Nibble, Byte, EPP, and ECP
modes.
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16 bytes FIFO for ECP.
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Power Management
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Four power saving modes: On, Doze,
Standby, Suspend.
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Programmable system activity detector
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Supports Intel & Cyrix SMM and APM.
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Supports STOPCLK.
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Supports IO trap & restart.
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Independent peripheral time-out timer to
monitor hard disk, serial & parallel port.
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128K SM_RAM address space from
0xA0000 to 0xB0000
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JTAG
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Boundary Scan compatible IEEE1149.1.
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Scan Chain control.
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Bypass register compatible IEEE1149.1.
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ID register compatible IEEE1149.1.
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RAM BIST control.
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ExCA is a trademark of PCMCIA / JEIDA.
PanelLink is a trademark of SiliconImage, Inc
GENERAL DESCRIPTION
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1. GENERAL DESCRIPTION
At the heart of the STPC Atlas is an advanced
processor block that includes a powerful x86
processor core along with a 64-bit SDRAM
controller, advanced 64-bit accelerated graphics
and video controller, a high speed PCI bus
controller and industry standard PC chip set
functions (Interrupt controller, DMA Controller,
Interval timer and ISA bus).
The STPC Atlas has in addition, a TFT output, a
Video Input, an EIDE controller, a Local Bus
interface, PCMCIA and super I/O features
including USB host hub.
1.1. ARCHITECTURE
The STPC Atlas makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main
memory and graphics frame-buffer. This means a
reduction in total system memory for system
performances that are equal to that of a
comparable frame buffer and system memory
based system, and generally much better, due to
the higher memory bandwidth allowed by
attaching the graphics engine directly to the 64-bit
processor host interface running at the speed of
the processor bus rather than the traditional PCI
bus.
The 64-bit wide memory array provides the
system with an 800MB/s peak bandwidth. This
allows for higher resolution screens and greater
color depth. The processor bus runs at 133 MHz,
further increasing "standard" bandwidth by at least
a factor of two.
The `standard' PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor core; additional low bandwidth
functions such as communication ports are
accessed by the STPC Atlas via an internal ISA
bus.
The PCI bus is the main data communication link
to the STPC Atlas chip. The STPC Atlas translates
appropriate host bus I/O and Memory cycles onto
the PCI bus. It also supports the generation of
Configuration cycles on the PCI bus. The STPC
Atlas, as a PCI bus agent (host bridge class), is
compatible with PCI specification 2.1. The chip-
set also implements the PCI mandatory header
registers in Type 0 PCI configuration space for
easy porting of PCI aware system BIOS. The
device contains a PCI arbitration function for three
external PCI devices.
Figure 1-1
describes this architecture.
1.2. GRAPHICS FEATURES
Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or off-
screen frame buffer areas of SDRAM memory.
The frame buffer can occupy a space up to 4
Mbytes anywhere in the physical main memory.
The maximum graphics resolution supported is
1280 x 1024 in 16 Million colours at 75 Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
To generate the TFT output, the STPC Atlas
extracts the digital video stream before the
RAMDAC and reformats it to the TFT format. The
height and width of the flat panel are
programmable.
1.3. INTERFACES
An industry standard EIDE (ATA 2) controller is
built in to the STPC Atlas and connected internally
via the PCI bus.
The STPC Atlas integrates two USB ports.
Universal Serial Bus (USB) is a general purpose
communications interface for connecting
peripherals to a PC. The USB Open Host
Controller Interface (Open HCI) Specification,
revision 1.1, supports speeds of up to 12 MB/s.
USB is royalty free and is likely to replace low-
speed legacy serial, parallel, keyboard, mouse
and floppy drive interfaces. USB Revision 1.1 is
fully supported under Microsoft Windows 98 and
Windows 2000.
The STPC Atlas PCMCIA controller has been
specifically designed to provide the interface with
PCMCIA cards which contain additional memory
or I/O
The power management control facilities include
socket power control, insertion/removal capability,
power saving with Windows inactivity, NCS
controlled Chip Power Down, together with further
controls for 3.3V suspend with Modem Ring
Resume Detection.
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