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STPC CONSUMER-S

PC Compatible Embeded Microprocessor

ADVANCED DATA

1/51

29/10/99

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Figure 1. Logic Diagram

POWERFUL x86 PROCESSOR

64-BIT 66MHz SDRAM UMA CONTROLLER

VGA & SVGA CRT CONTROLLER

2D GRAPHICS ENGINE

VIDEO INPUT PORT

VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT

TV OUTPUT
- 3-LINE FLICKER FILTER
- CCIR 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO

PCI MASTER / SLAVE CONTROLLER

ISA MASTER / SLAVE CONTROLLER

INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS

OPTIONAL 16-BIT LOCAL BUS INTERFACE

EIDE CONTROLLER

I C INTERFACE

POWER MANAGEMENT UNIT

3.3V OPERATION

STPC CONSUMER-S OVERVIEW

The STPC Consumer-S integrates a standard 5th
generation x86 core, a Synchronous DRAM con-
troller, a graphics subsystem, a video input port,
video pipeline, and support logic including PCI,
ISA, and IDE controllers to provide a single con-
sumer orientated PC compatible subsystem on a
single device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.

The STPC Consumer-S is packaged in a 388
Plastic Ball Grid Array (PBGA).

PBGA388

x86

Core

Host

I/F

SDRAM

CTRL

SVGA

VIP

PCI

m/s

CTR

PCI Bus

ISA
m/s

IPC

PCI
m/s

ISA Bus

CRTC

Cursor

Moni tor

IDE

I/F

PMU

W.dog

Video

Pipeline

C Key

K Key

LUT

Local Bus

Encoder

TVO

STPC CONSUMER-S

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X86 Processor core

Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.

Can access up to 4GB of external memory.

8Kbyte unified instruction and data cache
with write back and write through capability.

Parallel processing integral floating point unit,
with automatic power down.

Fully static design for dynamic clock control.

Low power and system management modes.

SDRAM Controller

64-bit data bus.

Up to 66MHz SDRAM clock speed.

Integrated system memory, graphic frame
memory and video frame memory.

Supports 2MB up to 128 MB memory.

Supports 8MB, 16M, and 32MB DIMMs.

Supports buffered, non buffered, and
registered DIMMs

4-line write buffers for CPU to DRAM and PCI
to DRAM cycles.

4-line read prefetch buffers for PCI masters.

Programmable latency

Programmable timing for DRAM parameters.

Supports -8, -10, -12, -13, -15 memory parts

Supports 1MB up to 8MB memory hole.

32-bit accesses not supported.

Autoprecharge not supported.

Power down not supported.

FPM and EDO not supported.

Graphics Controller

64-bit windows accelerator.

Compatibility to VGA & SVGA standards.

Hardware acceleration for text, bitblts,
transparent blts and fills.

Up to 64 x 64 bit graphics hardware cursor.

Up to 4MB long linear frame buffer.

8-, 16-, and 24-bit pixels.

CRT Controller

Integrated 135MHz triple RAMDAC allowing
for 1024 x 768 x 75Hz display.

8-, 16-, 24-bit pixels.

Interlaced or non-interlaced output.

Video Input port

Accepts video inputs in CCIR 601 mode.

Optional 2:1 decimator

Stores captured video in off setting area of
the onboard frame buffer.

Video pass through to the onchip PAL/NTSC
encoder for full screen video images.

HSYNC and B/T generation or lock onto
external video timing source.

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Color space conversion.

Programmable window size.

Chroma and color keying for integrated video
overlay.

TV Output

Programmable two tap filter with gamma
correction or three tap flicker filter.

Progressive to interlaced scan converter.

NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy
programmable video outputs.

CCIR601 encoding with programmable color
subcarrier frequencies.

Line skip/insert capability

Interlaced or non-interlaced operation mode.

625 lines/50Hz or 525 lines/60Hz 8 bit
multiplexed CB-Y-CR digital input.

CVBS and R,G,B simultaneous analog
outputs through 10-bit DACs.

Cross color reduction by specific trap filtering
on luma within CVBS flow.

Power down mode available on each DAC.

STPC CONSUMER-S

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PCI Controller

Fully compliant with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3
masters can connect directly. External PAL
allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to
PCI.

Support for burst read/write from PCI master.

PCI clock is 1/3 or 1/2 Host clock .

ISA master/slave controller

Generates the ISA clock from either
14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for
ISA cycles

Supports I/O recovery time for back to back I/
O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.

Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
NSP compliant.

Integrated Peripheral Controller

2X8237/AT compatible 7-channel DMA
controller.

2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Supports external RTC.

Local Bus interface

Multiplxed with ISA interface.

Low latency bus

22-bit address bus.

16-bit data bus with word steering capability.

Programmable timing (Host clock granularity)

2 Programmable Flash Chip Select.

5 Programmable I/O Chip Select.

Supports 32-bit Flash burst.

2-level hardware key protection for Flash boot
block protection.

Supports 2 banks of 8MB flash devices with
boot block shadowed to 0x000F0000.

IDE Interface

Supports PIO and Bus Master IDE

Supports up to Mode 5 Timings

Transfer Rates to 22 MBytes/sec

Supports up to 4 IDE devices

Concurrent channel operation (PIO & DMA
modes) - 4 x 32-Bit Buffer FIFO per channel

Support for PIO mode 3 & 4.

Support for DMA mode 1 & 2.

Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.

Supports 13.3/16.6 MB/s DMA data transfers

Bus Master with scatter/gather capability

Multi-word DMA support for fast IDE drives

Individual drive timing for all four IDE devices

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

Power Management

Four power saving modes: On, Doze,
Standby, Suspend.

Programmable system activity detector

Supports SMM.

Supports STOPCLK.

Supports IO trap & restart.

Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.

Supports RTC, interrupts and DMAs wake-up

GENERAL DESCRIPTION

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1 GENERAL DESCRIPTION

At the heart of the STPC Consumer-S is an ad-
vanced 64-bit processor block, dubbed the
5ST86. The 5ST86 includes a 486 processor core
along with a 64-bit SDRAM controller, advanced
64-bit accelerated graphics and video controller, a
high speed PCI local-bus controller and Industry
standard PC chip set functions (Interrupt control-
ler, DMA Controller, Interval timer and ISA bus).

The STPC Consumer-S makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for sys-
tem performances that are equal to that of a com-
parable frame buffer and system memory based
system, and generally much better, due to the
higher memory bandwidth allowed by attaching
the graphics engine directly to the 64-bit proces-
sor host interface running at the speed of the proc-
essor bus rather than the traditional PCI bus.

The 64-bit wide memory array provides the sys-
tem with 528MB/s peak bandwidth. This allows for
higher resolution screens and greater color depth.

The `standard' PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated together with the x86 processor
core; additional functions such as communica-
tions ports are accessed by the STPC Consumer-
S via internal ISA bus.

The PCI bus is the main data communication link
to the STPC Consumer-S chip. The STPC Con-
sumer-S translates appropriate host bus I/O and
Memory cycles onto the PCI bus. It also supports
generation of Configuration cycles on the PCI bus.
The STPC Consumer-S, as a PCI bus agent (host
bridge class), fully complies with PCI specification
2.1. The chip-set also implements the PCI manda-
tory header registers in Type 0 PCI configuration
space for easy porting of PCI aware system BI-
OS. The device contains a PCI arbitration function
for three external PCI devices.

The STPC Consumer-S has two functionnal
blocks

sharing the same balls : The ISA / IPC /

IDE block and the Local Bus / IDE block (see Ta-
ble 3). Any board with the STPC Consumer-S
should be built using only one of these two config-
urations.

At reset, the configuration is done by `strap op-
tions' which initialises the STPC Consumer-S to
the right settings. It is a set of pull-up or pull-down
resistors on the memory data bus, checked on re-
set, which auto-configure the STPC Consumer-S.

GRAPHICS FUNCTIONS

Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include hard-
ware acceleration of text, bitblts, transparent blts
and fills. The results of these operations change
the contents of the on-screen or off-screen frame
buffer areas of DRAM memory. The frame buffer
can occupy a space up to 4 Mbytes anywhere in
the physical main memory and always starts from
the bottom of the main physical memory.

The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours and 1024x768 in
true color at 75Hz refresh rate and is VGA and
SVGA compatible. Horizontal timing fields are
VGA compatible while the vertical fields are ex-
tended by one bit to accommodate above display
resolution.

VIDEO FUNCTIONS

The STPC Consumer-S provides several addition-
al functions to handle MPEG or similar video
streams. The Video Input Port accepts an encod-
ed digital video stream in one of a number of in-
dustry standard formats, decodes it, optionally
decimates it, and deposits it into an off screen
area of the frame buffer. An interrupt request can
be generated when an entire field or frame has
been captured. The video output pipeline incorpo-
rates a video-scaler and color space converter
function and provisions in the CRT controller to
display a video window. While repainting the
screen the CRT controller fetches both the video
as well as the normal non-video frame buffer in
two separate internal FIFOs. The video stream
can be color-space converted (optionally) and
smooth scaled. Smooth interpolative scaling in
both horizontal and vertical direction are imple-
mented. Color and Chroma key functions are also
implemented to allow mixing video stream with
non-video frame buffer.

The video output passes directly to the RAMDAC
for monitor output or through another optional
color space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Win-
dows type displays). The fliker filter is optional and
can be software disabled for use with large screen
area's of video.

GENERAL DESCRIPTION

5/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

The Video output pipeline of the STPC Consumer-
S interfaces directly to the internal digital TV en-
coder. It takes a 24 bit RGB non-interlaced pixel
stream and converts to a multiplexed 4:2:2 YCrCb
8 bit output stream, the logic includes a progres-
sive to interlaced scan converter and logic to in-
sert appropriate CCIR656 timing reference codes
into the output stream. It facilitates the high quality
display of VGA or full screen video streams re-
ceived via the Video input port to standard NTSC
or PAL televisions.

The digital PAL/NTSC encoder outputs interlaced
or non-interlaced video in PAL-B,D,G,H,I PAL-N,
PAL-M or NTSC-M standards and "NTSC- 4.43" is
also possible.

The four frame (for PAL) or 2 frame (for NTSC)
burst sequences are internally generated, subcar-
rier generation being performed numerically with
CKREF as reference. Rise and fall times of syn-
chronisation tips and burst envelope are internally
controlled according to the relevant ITU-R and
SMPTE recommendations.

Video output signals are directed to four analog
output pins through internal D/A converters giving,
simultaneous R,G,B and composite CVBS out-
puts.

IDE INTERFACE

An industry standard EIDE (ATA 2) controller is
built into the STPC Consumer-S. The IDE port is
capable of supporting a total of four devices.

POWER MANAGEMENT

The STPC Consumer-S core is compliant with the
Advanced Power Management (APM) specifica-
tion to provide a standard method by which the
BIOS can control the power used by personal
computers. The Power Management Unit module
(PMU) controls the power consumption providing
a comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency's
Energy Star Computer Program. The PMU pro-
vides following hardware structures to assist the
software in managing the power consumption by
the system.

- System Activity Detection.
- Three power down timers.
- Doze timer for detecting lack of system activity
for short durations.
- Stand-by timer for detecting lack of system activ-
ity for medium durations
- Suspend timer for detecting lack of system activ-
ity for long durations.
- House-keeping activity detection.

- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer for detecting lack of peripheral
activity
- SUSP# modulation to adjust the system perform-
ance in various power down states of the system
including full power on state.
- Power control outputs to disable power from dif-
ferent planes of the board.

Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI in-
terrupts to CPU so that the SMM software can put
the system in decreasing states of power con-
sumption. Alternatively, system activity in a power
down state can generate SMI interrupt to allow the
software to bring the system back up to full power
on state. The chip-set supports up to three power
down states: Doze state, Stand-by state and Sus-
pend mode. These correspond to decreasing lev-
els of power savings.

POWER DOWN

Power down puts the STPC Consumer-S into sus-
pend mode. The processor completes execution
of the current instruction, any pending decoded in-
structions and associated bus cycles. During the
suspend mode, internal clocks are stopped.

Re-

moving power down, the processor resumes in-
struction fetching and begins execution in the in-
struction stream at the point it had stopped. Be-
cause of the static nature of the core, no internal
data is lost.

Электронный компонент: STPCC0366BTC3