STPC

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INDUSTRIAL

PC Compatible Embedded Microprocessor

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11/2/02

Issue 2.4

ISA

I/F

Figure 1. Logic Diagram

POWERFUL X86 PROCESSOR

64-BIT BUS ARCHITECTURE

64-BIT 66MHz DRAM CONTROLLER

SVGA GRAPHICS CONTROLLER

135MHz RAMDAC

UMA ARCHITECTURE

TFT DISPLAY CONTROLLER

PCI MASTER / SLAVE / ARBITER

LOCAL BUS INTERFACE

ISA (MASTER/SLAVE) INTERFACE
-INCLUDING THE IPC

PC-CARD INTERFACE
- PCMCIA
- CARDBUS

I/O FEATURES
- PC/AT+ KEYBOARD CONTROLLER
- PS/2 MOUSE CONTROLLER
- 2 SERIAL PORTS
- 1 PARALLEL PORT

IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS

POWER MANAGEMENT

STPC INDUSTRIAL OVERVIEW

The STPC Industrial integrates a fully static x86
processor, fully compatible with standard fifth gen-
eration x86 processors, and combines it with pow-
erful chipset, graphics, TFT, PC-Card, Local Bus,
keyboard, mouse, serials and parallel interfaces to
provide a single Industrial oriented PC compatible
subsystem on a single device. The performance of
the device is comparable with the performance of
a typical P5 generation system.
The device is packaged in a 388 Plastic Ball Grid
Array (PBGA).

TFT

ext

x86

Core

Host I/F

Serial2

// Port

Serial1

Kbd

Mouse

DRAM

I/F

VGA

PCI
m/s

Local

Bus I/F

PCMCIA

CARDBUS

PCI BUS

IPC

82C206

PCI

CONTROLLER

ISA BUS

CRTC

HW Cursor

Monitor

TFT Output

SYNC Output

TFT I/F

PBGA388

STPC INDUSTRIAL

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Issue 2.4 - February 11, 2002

X86 Processor core

Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.

Access up to 4GB of external memory.

8Kbyte unified instruction and data cache
with write back capability.

Parallel processing integral floating point unit,
with automatic power down.

Clock core speeds up to 100 MHz.

Fully static design for dynamic clock control.

Low power and system management modes.

Optimized design for 3.3V operation.

DRAM Controller

Integrated system memory and graphic frame
memory.

Supports up to 128-MByte system memory in
4 banks and down to as little as 2Mbytes.

Supports 4-MByte, 8-MByte, 16-MByte, and
32-MByte single-sided and double-sided
DRAM SIMMs.

Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.

Four quad-word read prefetch buffers for PCI
masters.

Supports Fast Page Mode & EDO DRAMs.

Programmable timing for DRAM parameters
including CAS pulse width, CAS pre-charge
time, and RAS to CAS delay.

60, 70, 80 & 100ns DRAM speeds.

Memory hole between 1 MByte & 8 MByte
supported for PCI/ISA busses.

Hidden refresh.

To check if your memory device is supported by
the STPC, please refer to

Table 6-24

in the

Programming Manual.

Graphics Controller

64-bit windows accelerator.

Complete backward compatibility to VGA and
SVGA standards.

Hardware acceleration for text (generalized
bit map expansion), bitblts, transparent blts
and fills.

Up to 64 x 64 bit graphics hardware cursor.

Up to 4MB long linear frame buffer.

8, 16, 24 and 32 bit pixels.

Drivers for Windows and other operating
systems.

CRT Controller

Integrated 135MHz triple RAMDAC allowing
for 1280 x 1024 x 75Hz display.

Requires external frequency synthesizer and
reference sources.

8, 16, 24 and 32-bit pixels.

Interlaced or non-interlaced output.

TFT Interface

Programmable panel size up to 1024 by 1024
pixels.

Support for 640 x 480, 800 x 600 & 1024 x
768 active matrix TFT flat panels with 9, 12,
18-bit interface.

Support 1 & 2 Pixels per Clock.

Programmable image positionning.

Programmable blank space insertion in text
mode.

Programmable horizontal and vertical image
expansion in graphic mode.

A fully programmable PWM (Pulse Width
Modulator) signals to adjust the flat panel
brightness and contrast.

Supports PanelLink

high speed serial

transmitter externally for high resolution
panel interface.

PCI Controller

Fully compliant with PCI Version 2.1
specification.

Integrated PCI arbitration interface. Up to 3
masters can connect directly. External PAL
allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to
PCI.

Support for burst read/write from PCI master.

0.33X and 0.5X CPU clock PCI clock.

Local Bus interface

66MHz, low latency bus.

Asynchronous / synchronous.

22-bit address and 16-bit data busses.

2 Programmable Flash EPROM Chip Select.

4 Programmable I/O Chip Select.

Separate memory and I/O address spaces.

Memory prefetch (improved performances).

STPC INDUSTRIAL

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ISA master/slave

Generation of the ISA clock from either
14.318MHz oscillator clock or system clock

Programmable extra wait state for ISA cycles

Supports I/O recovery time for back to back
I/O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.

Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
NSP compliant.

PC-Card interface

Support one PCMCIA 2.0 / JEIDA 4.1 68-pin
standard PC Card Socket.

Power Management support.

Support PCMCIA/ATA specifications.

Support I/O PC Card with pulse-mode
interrupts.

Provides an ExCA

implementation to

PCMCIA 2.0 / JEIDA 4.1 standards.

DMA support.

Keyboard interface

Fully PC/AT& compatible

Mouse interface

Fully PS/2 compatible

Serial interface

16550A compatible

Programmable word length, stop bits, parity.

16-bit programmable baud rate generator.

Interrupt generator.

Loop-back mode.

8-bit scratch register.

Two 16-bit FIFOs.

Two DMA handshake lines.

Parallel port

Standard Centronics mode supported.

Nibble mode supported.

Integrated Peripheral Controller

Two 8237/AT compatible 7-channel DMA
controllers.

Two 8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Power Management

Four power saving modes: On, Doze,
Standby, Suspend.

Programmable system activity detector

Supports SMM.

Supports IO trap & restart.

Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.

Supports APM

Supports RTC, interrupt and DMA wake ups

ExCA is a trademark of PCMCIA / JEIDA.

PanelLink is a trademark of SiliconImage, Inc

GENERAL DESCRIPTION

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1 GENERAL DESCRIPTION

At the heart of the STPC Industrial is an
advanced 64-bit processor block, dubbed the
5ST86. The 5ST86 includes a powerful x86
processor core along with a 64-bit DRAM
controller, advanced 64-bit accelerated graphics
and video controller, a high speed PCI local-bus
controller and Industry standard PC chip set
functions (Interrupt controller, DMA Controller,
Interval timer and ISA bus).

The STPC Industrial has in addition to the 5ST86
a TFT output, a Local Bus interface, PC Card and
super I/O features.

The STPC Industrial makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for
system performances that are equal to that of a
comparable frame buffer and system memory
based system, and generally much better, due to
the higher memory bandwidth allowed by
attaching the graphics engine directly to the 64-bit
processor host interface running at the speed of
the processor bus rather than the traditional PCI
bus.

The 64-bit wide memory array provides the
system with 320MB/s peak bandwidth, double
that of an equivalent system using 32 bits. This
allows for higher resolution screens and greater
color depth. The processor bus runs at 66Mhz
further increasing "standard" bandwidth by at
least a factor of two.

The `standard' PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor core; additional functions such as
communication ports are accessed by the STPC
Industrial via an internal ISA bus.

The PCI bus is the main data communication link
to the STPC Industrial chip. The STPC Industrial
translates appropriate host bus I/O and Memory
cycles onto the PCI bus. It also supports the
generation of Configuration cycles on the PCI
bus. The STPC Industrial, as a PCI bus agent
(host bridge class), fully complies with PCI
specification 2.1. The chip-set also implements
the PCI mandatory header registers in Type 0 PCI
configuration space for easy porting of PCI aware
system BIOS. The device contains a PCI
arbitration function for three external PCI devices.

Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or off-
screen frame buffer areas of DRAM memory. The
frame buffer can occupy a space up to 4 Mbytes
anywhere in the physical main memory.

The maximum graphics resolution supported is
1280x1024 in 65536 colours at 75Hz refresh rate
and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.

To generate the TFT output, the STPC Industrial
extracts the digital video stream before the
RAMDAC and reformats it to the TFT format. The
height and width of the flat panel are
programmable through configuration registers up
to a size of 1024 by 1024.

By default, lower resolution images cover only a
part of the larger TFT panel. The STPC Industrial
allows to expand the image vertically and
horizontally in text mode by inserting
programmable blank pixels. It allows expantion of
the image vertically and horizontally in graphics
mode by replicating pixels. The replication of J
times every K pixel is independently
programmable in the vertical and horizontal
directions.

PanelLink

is a proprietary interconnect

protocol defined by Silicon Image, Inc. It consists
of a transmitter that takes parallel video/graphics
data from the host LCD graphics controller and
transmits it serially at high speed to the receiver
which controls the TFT panel. The TFT interface
is designed to support the connection of this
control signal to the PanelLink

transmitter.

The STPC Industrial CARDBUS / PCMCIA
controller has been specifically designed to
provide the interface with PC-Cards which contain
additional memory or I/O and provides an
ExCA

implementation to PCMCIA 2.0 / JEIDA

4.1 standards.

The power management control facilities include
socket power control, insertion/removal capability,
power saving with Windows inactivity, NCS
controlled Chip Power Down, together with further
controls for 3.3v suspend with Modem Ring
Resume Detection.

Электронный компонент: STPCI01