1/12
June 2003
s
SUPPLY VOLTAGE RANGE: 4V TO 5.5V
s
TYPICAL PEAK OUTPUT CURRENT:
(SOURCE 2A, SINK 3.5A)
s
OPERATING FREQUENCY: 30 TO 750 KHz
s
SMART TURN-OFF ANTICIPATION TIMING
s
AUTOMATIC TURN OFF FOR DUTY CYCLE
LESS THAN 14%
s
POSSIBILITY TO OPERATE IN
DISCONTINUOUS MODE
DESCRIPTION
STSR3 Smart Driver IC provides a high current
outputs
to
properly
drive
secondary
Power
Mosfets used as Synchronous Rectifier in low
output
voltage,
high
efficiency
Flyback
Converters. From a synchronizing clock input,
withdrawn on the secondary side of the isolation
transformer, the IC generates a driving signal with
set dead times with respect to the primary side
PWM signal.
The
IC
operation
prevents
secondary
side
shoot-through conditions at turn-on of the primary
switch providing anticipation in turn-off the output.
This smart function is implemented by a fast
cycle-after-cycle logic control mechanism, based
on a high frequency oscillator synchronized by the
clock signal. This anticipation is externally set
through external component. A special Inhibit
function allows to shut-off the drive output. This
feature makes discontinuous conduction mode
possible and avoids reverse conduction of the
synchronous rectifier.
STSR3
SYNCHRONOUS RECTIFIERS
SMART DRIVER FOR FLYBACK
PEAK
DETECTOR
BIAS
UVLO
CK
Vcc
6
5.7V
8
4
2
OUTPUT
BUFFER
1
N/C
PWRGND
SGLGND
ANTICIPATION
SET
3
5
INHIBIT
25mV
-
+
DIGITAL
CONTROL
HIGH
FREQUENCY
OSCILLATOR
7
+
+
+
OUT
GATE
SETANT
SCHEMATIC DIAGRAM
SO-8
STSR3
2/12
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum
THERMAL DATA
(*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 C/W can be
obtained improving thermal conductivity of the board
ORDERING CODES
CONNECTION DIAGRAM (top view)
Symbol
Parameter
Value
Unit
V
CC
DC Input Voltage
-0.3 to 6
V
V
OUTGATE
Max Gate Drive Output Voltage
-0.3 to V
CC
V
V
INHIBIT
Max INHIBIT Voltage (*)
-0.6 to V
CC
V
V
CK
Clock Input Voltage Range (*)
-0.3 to V
CC
V
P
TOT
Continuous Power Dissipation at T
A
=105C without heatsink
270
mW
ESD
Human Body Model
Pins 1,2, 4, 5, 6, 7, 8
1
KV
Pin 3
0.9
KV
T
stg
Storage Temperature Range
-55 to +150
C
T
op
Operating Junction Temperature Range
-40 to +125
C
Symbol
Parameter
SO-8
Unit
R
thj-amb
Thermal Resistance Junction-case
40
C/W
R
thj-amb
Thermal Resistance Junction-ambient (*)
160
C/W
TYPE
SO-8
SO-8 (T&R)
STSR3
STSR3CD
STSR3CD-TR
STSR3
3/12
PIN DESCRIPTION
Pin N
Symbol
Name and Function
1
NC
No internally connected
2
V
CC
The supply voltage range from 4.0V to 5.5V allows applications with logic gate
threshold mosfets. UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.
3
SET
ANT
The voltage on this pin sets the anticipation (t
ANT
) in turning off the OUT
GATE
It is
possible to choose among three different anticipation times by discrete
partitioning of the supply voltage.
4
CK
This input provides synchronization for IC's operations, being the transitions
between the two output conditions based on a positive threshold, equal for the
two slopes. A smart internal control logic mechanism using a 15MHz internal
oscillator generates proper anticipation timing at the turn-off of each output. This
feature allows safe turn-off of Synchronous Rectifier avoiding any eventual
shoot-through situation on secondary side at both transitions. Smart clock
revelation mechanism makes these operations independent by false triggering
pulses generated in light load conditions. Absolute maximum voltage rating of the
pin can be exceeded limiting the current flowing into the pin to 10mA max.
5
INHIBIT
This input enables OUT
GATE
to work when its voltage is lower than the negative
threshold voltage (V
INHIBIT
<V
H
). If V
INHIBIT
>V
H
the OUT
GATE
will be high for a
minimum conduction time (t
ON(GATE)
). In typical flyback converter application, it is
possible to turn off the synchronous MOSFET when the current through it tends to
reverse, allowing discontinuous conduction mode and providing protection to the
converter from eventual sinking current from the load.Absolute maximum voltage
rating of the pin can be exceeded limiting the current flowing into the pin to 10mA
max.
6
SGLGND
Reference for all the control logic signals. This pin is completely separated from
the PWRGND to prevent eventual disturbances to affect the control logic.
7
OUT
GATE
Gate Drive signal for synchronous MOSFET. Anticipation [t
ANT
] in turning off
OUT
GATE
is provided during the transition in which the clock input goes to high
level.
8
PWRGND
Reference for power signals, this pin carries the full peak currents for the two
outputs.
STSR3
4/12
ELECTRICAL CHARACTERISTICS (V
CC
=5V, CK= 250kHz, duty-cycle=50%, V
INHIBIT
=-200mV, T
J
=-40
to 125C, unless otherwise specified.)
Note1: t
R
is measured between 10% and 90% of the final voltage; t
F
is measured between 90% and 10% on the initial voltage
Note2: Parameter guaranteed by design
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT
V
CCON
Start Threshold
3.8
4
V
V
CCOFF
Turn OFF Threshold After
Start
3.5
3.6
V
V
Z
Zener Voltage
CK=0V
I
Z
= 2mA
5.5
5.8
6
V
I
CC
Unloaded Supply Current
OUT
GATE
= no load
15
20
mA
CK=0V
OUT
GATE
= no load
3
5
GATE DRIVER OUTPUTS
V
OL
Output Low Voltage
I
OUTGATE
=-200mA
0.10
0.16
V
V
OH
Output High Voltage
I
OUTGATE
=200mA
4.70
4.85
V
I
OUT
Output Source Peak
Current
2
A
Output Sink Peak Current
3.5
R
OUT
Output Series Source
Resistance
I
OUTGATE
=-200mA
0.75
1.5
Output Series Sink
Resistance
I
OUTGATE
=200mA
0.5
0.8
t
R
OUT
GATE
Rise Time
C
LOAD
=5nF (Note 1)
40
ns
t
F
OUT
GATE
Fall Time
C
LOAD
=5nF (Note 1)
30
ns
t
P
Clock Propagation Delay to
Turn ON of OUT
GATE
No Load
50
ns
TURN-OFF ANTICIPATION TIME
t
ANT
OUT
GATE
Turn-off
Anticipation Time
V
ANT
= 0 to 1/3V
CC
; no load
75
ns
V
ANT
= 1/3V
CC
to 2/3V
CC
; no load
150
V
ANT
= 2/3V
CC
to V
CC
; no load
225
I
SETANT
Leakage Current (Note 2)
-0.1
0.1
A
INHIBIT OUT
GATE
ENABLE
V
H
Threshold Voltage
T
J
= 25C
-30
-25
mV
I
H
Leakage Current (Note 2)
V
INHIBIT
= 200mV
-400
nA
V
INHIBIT
= -200mV
1
A
t
ON(GATE)
Minimum OUT
GATE
On time V
INHIBIT
= +200mV
250
ns
SYNCHRONIZATION INPUT
V
CK
Reference Voltage
T
J
= 25C
2.6
2.8
V
D
OFF
Duty Cycle Shut Down
T
J
= 25C
13
14
%
Duty Cycle Turn ON after
Shut Down
T
J
= 25C
18
20
STSR3
5/12
TIMING DIAGRAM
APPLICATION INFORMATION: STSR3 IN FLYBACK CONVERTER SECONDARY SIDE
NOTES
1) Ceramic Capacitors C1 and C2 must be placed very close to the IC;
2) R1 and R2 set the anticipation time by partitioning the V
CC
voltage;
3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range;
4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high;
5) D1 could be necessary to protect INHIBIT pin from negative voltages.
6) D2 could be necessary to protect INHIBIT pin from voltages higher than V
CC
7) D3 could be necessary to protect CK pin from voltages higher than V
CC
.
8) SGLGND layout trace must not include OUT
GATE
current paths.
9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike.
+5V
+5V
Vout
Vin
+5V
Cout
C2
100nF
R1
R2
R3
R4
D1
D2
C1
100nF
R5
STSR3
4
5
7
8
2
6
3
Ck
I
NHI
B
I
T
OU
T
G
a
t
e
P
W
RG
ND
Vc
c
SGLGND
SETANT
TRANSFORMER
MosfetN
D3
PWM
Feedback
Loop
option
PDF 
ZIP