STV0042A

SATELLITE SOUND AND VIDEO PROCESSORS

March 1997

PRODUCT PREVIEW

SHRINK42

(Plastic Package)

ORDER CODE : STV0042A

SOUND

TWO INDEPENDENT SOUND DEMODULATORS

PL L

DEMODULATION

WITH

5-10MHz

FREQUENCY SYNTHESIS

PROGRAMMABLE

DEMODULATOR

BANDWIDTH ACCOMODATING FM DEVIA-
TIONS FROM

30kHz TILL

400kHz

PROGRAMMABLE 50/75

s OR NO DE-EM-

PHASIS

DYNAMIC NOISE REDUCTION

ONE OR TWO AUXILIARY AUDIO INPUTS
AND OUTPUTS

GAIN

CONTROLLED

AND

MUTEABLE

AUDIO OUTPUTS

HIGH IMPEDANCE MODE AUDIO OUTPUTS
FOR TWIN TUNER APPLICATIONS

VIDEO

COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN
CONTROL

COMPOSITE

VIDEO

SELECTABLE

IN-

VERTER

TWO SELECTABLE VIDEO DE-EMPHASIS
NETWORKS

4 x 2 VIDEO MATRIX

HIGH IMPEDANCE MODE VIDEO OUTPUTS
FOR TWIN TUNER APPLICATIONS

MISCELLANEOUS

22kHz TONE GENERATION FOR LNB CONTROL

C BUS CONTROL :

CHIP ADDRESSES = 06

HEX

LOW POWER STAND-BY MODE WITH ACTIVE
AUDIO AND VIDEO MATRIXES

DESCRIPTION

The STV0042A BICMOS integrated circuit realizes
all the necessary signal processing from the tuner
to the Audio/Video input and output connectors
regardless the satellite system.
The STV0042 is intended for low cost satellite
receiver application.

A GND R

FC L

PK OUT

REF

CPUMP R

U75 R

DET R

AMPLK R

A 12V

REF

A GND L

AGC R

AMPLK L

U75 L

DET L

CPUMP L

GND 5V

XTL

SDA

SCL

AGC L

FM IN

S2 RTN R

S2 RTN L

B-BAND IN

V GND

CLAMP IN

VIDEEM1

V 12V

VIDEEM2/22kHz

UNCL DEEM

S2 OUT R

S2 OUT L

S2 VID RTN

VOL L

S2 VID OUT

S1 VID OUT

VOL R

SUM OUT

PK IN

FC R

0042A

-
0

.
E

PIN CONNECTIONS

1/24

PIN ASSIGNMENT

Pin Number

Name

Function

FC R

Audio Roll-off Right

SUM OUT

Noise Reduction Summing Output

PK IN

Noise Reduction Peak Detector Input

VOL R

Volume Controlled Audio Out Right

S1 VID OUT

TV-Scart 1 Video Output

S2 VID OUT

VCR-Scart 2 Video Output

VOL L

Volume Controlled Audio Out Left

S2 VID RTN

VCR-Scart 2 Video Return

S2 OUT L

Fixed Level Audio Output Left

CLAMP IN

Sync-Tip Clamp Input

S2 OUT R

Fixed Level Audio Output Right

UNCL DEEM

Unclamped Deemphasized Video Output

VIDEEM2/22kHz

Video Deemphasis 2 or 22kHz Output

V 12V

Video 12V Supply

VIDEEM1

Video Deemphasis 1

V GND

Video Ground

B-BAND IN

Base Band Input

S2 RTN L

Auxiliary Audio Return Left

S2 RTN R

Auxiliary Audio Return Right

FM IN

FM Demodulator Input

AGC L

AGC Peak Detector Capacitor Left

SCL

C Bus Clock

SDA

C Bus Data

XTL

4/8MHz Quartz Crystal or Clock Input

Digital 5V Power Supply

GND 5V

Digital Power Ground

CPUMP L

FM PLL Charge Pump Capacitor Left

DET L

FM PLL Filter Left

U75 L

Deemphasis Time Constant Left

AMPLK L

Amplitude Detector Capacitor Left

AGC R

AGC Peak Detector Capacitor Right

A GND L

Audio Ground

REF

2.4V Reference

A 12V

Audio 12V Supply

AMPLK R

Amplitude Detector Capacitor Left

DET R

FM PLL Filter Right

U75 R

Deemphasis Time Constant Right

CPUMP R

FM PLL Charge Pump Capacitor Right

REF

Current Reference Resistor

PK OUT

Noise Reduction Peak Detector Output

FC L

Audio Roll-off Left

A GND R

Audio Ground

-
01.

STV0042A

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PIN DESCRIPTION

1 - Sound Detection
FMIN
This is the input to the two FM demodulators. It
feeds two AGC amplifiers with a bandwidth of at
least 5-10MHz. There is one amplifier for each
channel both with the same input. The AGC ampli-
fiers have a 0dB to +40dB range.
Z

= 5k

, Min input = 2mV

per subcarrier.

Max input = 500mV

(max when all inputs are

added together, when their phases coincide).

AGC L, AGC R
AGC amplifiers peak detector capacitor connec-
tions. The output current has an attack/decayratio
of 1:32. That is the ramp up current is approxi-
mately 5

A and decay current is approximately

160

A. 11V gives maximum gain. These pins are

also driven by a circuit monitoring the voltage on
AMPLK L and AMPLK R respectively.

AMPLK L, AMPLK R
The outputs of amplitude detectors LEFT and
RIGHT. Each requires a capacitor and a resistor to
GND. The voltage across this is used to decide
whether there is a signal being received by the FM
detector. The level detector output drives a bit in
the detector I

C bus control block.

AMPLK L and AMPLK R drive also respectively
AGC L and AGC R. For instance when the voltage
on AMPLK L is > (V

REF

+ 1 V

) it sinks current to

REF

from pin AGCL to reduce the AGC gain.

DET L, DET R
Respectively the outputs of the FM phase detector
left and right. This is for the connection of an
external loop filter for the PLL. The output is a
push-pull current source.

CPUMP L, CPUMP R
The output from the frequency synthesizer is a
push-pullcurrent source which requiresa capacitor
to ground to derive a voltage to pull the VCO to the
target frequency. The output is

100

A to achieve

lockand

A during lock to provide a trackingtime

constant of approximately 10Hz.

VREF
This is the audio processor voltage reference used
through out the FM/audio section of the chip. As
such it is essential that it is well decoupled to
ground to reduce as far as possible the risk of
crosstalk and noise injection. This voltage is de-
rived directly from the bandgap reference of 2.4V.
The V

REF

output can sink up to 500

A in normal

operation and 100

A when in stand-by.

IREF
This is a bufferedV

REF

outputto an off-chip resistor

to produce an accurate current reference, within

the chip, for the biasing of amplifiers with current
outputs into filters. It is also required for the Noise
reduction circuit to provide accurate roll-off fre-
quencies.
This pin should not be decoupled as it would inject
current noise. The target current is 50

2% thus

a 47.5k

1% is required.

A 12V
Double bonded main power pin for the audio/FM
section of the chip. The two bond connections are
to the ESD and to power the circuit and on chip
regulators/references.

A GND L
This ground pin is double bonded :
1) to channel LEFT : RF section & VCO,
2) to both AGC amplifiers, channel LEFT and

RIGHT audio filter section.

A GND R
This ground pin is double bonded :
1) to the volume control, noise reduction system,

ESD + Mux + V

REF

2) to channel right : RF section & VCO

2 - Baseband Audio Processing
PK OUT
The noise reduction control loop peak detector
output requires a capacitor to ground from this pin,
and a resistor to V

REF

pin to give some accurate

decaytime constant.An on chip5k

25 % resistor

and external capacitor give the attack time.

PK IN
This pin is an input to a control loop peak detector
and is connectedto the output of the offchip control
loop band pass filter.

SUM OUT
The two audio demodulated signals are summed
together by means of an amplifier with a gain of 0.5.
If both inputs are 1V then the output is 1V. This
amplifier has an input follower buffer which gives a
V

offset in the DC bias voltage. Thus the filter

which this amplifier drives must include AC cou-
pling to the next stage (PK IN Pin).

FC L, FC R
The variable bandwidth transconductance ampli-
fier has a current output which is variable depend-
ing on the input signal amplitude as defined by the
control loop of the noise reduction. The output
current is then dumped into an off-chip capacitor
which together with the accurate current reference
define the min/max rolloff frequencies.A resistor in
series with a capacitor is connected to ground from
these two pins.

STV0042A

3/24

U75 L, U75 R
External deemphasis networks for channels left and
right. For each channel a capacitor and resistor in
parallel of 75

s time constant are connectedbetween

hereandV

REF

to provide 75

s de-emphasis.Internally

selectable is an internal resistor that can be pro-
grammedtobe addedin paralleltherebyconvertingthe
networkto approx50

s de-emphasis(see controlblock

map).The value of theinternal resistors is 30k

30%.

Theamplifier forthisfilterisvoltageinput,currentoutput;
with

500mV input the outputwill be

VOL L, VOL R
Themainaudiooutputfrom thevolumecontrolamplifier
the signal to get output signals as high as 2V

RMS

(+12dB) on a DC bias of 4.8V.Control is from +12dBto
-26.75dB plus Mute with 1.25dB steps. This amplifier
has short circuit protection and is intended to drive a
SCART connector directly via AC coupling and meets
thestandardSCARTdriverequirements.Theseoutputs
featurehigh impedancemode for parallel connection.

S2 OUT L, S2 OUT R
These audio outputs are sourced directly from the
audioMUX, andas a result do not includeany volume
controlfunction.Theywill outputa1V

RMS

signalbiased

at4.8V.They are shortcircuit protected.Theseoutputs
feature high impedance mode for parallel connection
and meetSCART drive requirement.

S2 RTN L, S2 RTN R
These pins allow auxiliary audio signals to be con-
nected to the audio processor and hence makes
use of the on-chip volume control. For additional
details please refer to the audio switching table.

3 - Video Processing
B-BAND IN
AC-coupled video input from a tuner.
Z

> 10k

25%. This drives an on-chipvideo ampli-

fier.TheotherinputofthisampisACgroundedbybeing
connectedto an internal V

REF

. The videoamplifier has

selectablegain from 0dBto 12.7dBin 63 stepsand its
output signal can be selected normal or inverted.

UNCL DEEM
Deemphasized still unclamped output. It is also an
input of the video matrix.

VIDEEM1
Connected to an external de-emphasis network
(for instance 625 lines PAL de-emphasis).

VIDEEM2 / 22kHz
Connected to an external de-emphasis network
(for instance 525 lines NTSC or other video de-em-
phasis). Alternatively a precise 22kHz tone may be
output by I

C bus control.

CLAMP IN
This pin clampsthemost negativeextremeof theinput
(the sync tips) to 2.7V

(or appropriatevoltage). The

video at the clamp input is only 1V

. This clamped

video which is de-emphasised, filtered and clamped
(energydispersalremoved) is normal, negativesyncs,
video. This signal drives the Video Matrix input called
Normal Video. It has a weak (1.0

15 %) stable

current source pulling the input towards GND. Other-
wise the input impedance is very high at DC to 1kHz
Z

> 2M

. Video bandwidth through this is -1dB at

5.5MHz. The CLAMP input DC restore voltageis then
usedas a means for gettingthecorrect DC voltageon
the SCART outputs.

S2 VID RTN
External video input 1.0V

AC coupled 75

source impedance. This input has a DC restoration
clamp on its input. The clamp sink current is 1

15% with the buffer Z

> 1M

. This signal is an

input to the Video Matrix.

S1 VID OUT, S2 VID OUT
Videodrivers for SCART 1 and SCART 2. An external
emitter follower bufferis required to drive a 150

load.

The average DC voltage to be 1.5V on the O/P. The
signalis video2.0V

5.5MHzBW with synctip = 1.2V.

These pins get signals from the Video Matrix. The
signalselected from theVideo Matrix for outputon this
pin is controlled by a control register. This output also
featureahighimpedancemodeforparallelconnection.

V 12V
+12V double bonded : ESD+guard rings and video
circuit power.

V GND
Doubled bonded. Clean VID IN GND. Strategically
placed video power ground connection to reduce
video currents getting into the rest of the circuit.

4 - Control Block
GND 5V
The main power ground connection for the control
logic, registers, the I

C bus interface, synthesizer

& watchdog and XTLOSC.

VDD 5V
Digital +5V power supply.

SCL
This is the I

C busclock line. Clock = DC to 100kHz.

Requires external pull up eg. 10k

to 5V.

SDA
This is the I

C bus data line. Requires external pull

up eg. 10k

to 5V.

XTL
This pin allows for the on-chip oscillator to be either
used with a crystal to ground of 4MHz or 8MHz, or
to be driven by an external clock source. The
external source can be either 4MHz or 8MHz. A
programmablebit in the control block removes a

block when the 4MHz option is selected.

PIN DESCRIPTION (continued)

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