STV1601A
SERIAL INTERFACE TRANSMISSION ENCODER
November 1992
28
29
30
31
32
33
34
35
18
17
16
15
14
13
12
11
10
27
26
25
24
23
22
21
20
19
36
1
2
3
4
5
6
7
8
9
37
V
EE
D3X
D4Y
D4X
D5Y
D5X
D6Y
D6X
D7Y
D7X
NC
PCK
TN1
TRP
FV
GND
PCY
PCX
RSE
V
CC
V
EE
D0Y
D0X
D1Y
D1X
D2Y
D2X
D3Y
LST
GND
SX
SY
GND
D9X
D9Y
D8X
D8Y
1601A-01.EPS
PIN CONNECTIONS
PGA37
(Ceramic Package)
ORDER CODE : STV1601A
THIS IC CONTAINS ALL THE CIRCUITS NEEDED
FOR CONVERSION FROM PARALLEL DATA,
AND PARALLEL CLOCK, INTO SERIAL DATA.
APPLICATIONS ARE STRAIGHTFORWARD AS
ONLY A FEW EXTERNAL COMPONENTS ARE
NEEDED.
OTHER RELATED IC's INCLUDE :
.
STV1602A, A SERIAL TRANSMISSION DE-
CODER (WITH A BUILT-IN CABLE EQUAL-
IZER
AND
PARALLEL-TO-SERIAL
CONVERSION)
.
STV1389AQ COAXIAL CABLE DRIVER
STRUCTURE
.
Hybrid IC
APPLICATIONS
SERIAL DATA TRANSMISSION ENCODER
.
100 to 270 Mb/s
APPLICATIONS EXAMPLES
.
Serial data transmission of digital television
signal 525-625 lines
.
4:2:2 component 270Mb/s (10-BIT)
.
4*FSC PAL composite 177Mb/s (10-BIT)
.
4*FSC NTSC composite 143Mb/s (10-BIT)
FUNCTIONS
.
Parallel-to-serial conversion
.
Scrambler : Modulo - 2 division by
G(x) = (x
9
+ x
4
+ 1) (x + 1)
.
PLL for serial clock generation
.
PLL lock detection
.
Sync word required with the parallel data
stream
8 bit
10 bit
1st word
FFH
3FFH
2nd word
00H
000H
3rd word
00H
000H
Sync word conversion (8-bit timing reference signal
is internally converted to 10-bit).
CODE LIMITATION
The word composing the Sync word listed above
shall not appear during data words.
This limitation includes 00 and FF in 8-bit use and
000 through 003 and 3FC through 3FF in 10-bit
use.
DESCRIPTION
The STV1601Ais a Hybrid IC encoder that converts
parallel data into serial data for a serial transmis-
sion line.
1/17
PIN DESCRIPTION
Pin
N
Symbol
Equivalent circuit
Description
I/O
Standard
Min. Typ. Max. Unit
1
LST
PLL lock detection. Is High
while PLL locked. If
unlocked, becomes irregular.
At free running (TN1 H)
turns Low
H
L
O
-1.0
-4.0
V
V
36
PCK
Clock output frequency
divided to 1/10 VCO output.
Used to check VCO free
running frequency
H
L
O
-0.8
-1.6
V
V
3
SX
Differential Serial Output
Input parallel data is
converted to serial, then
from scrambled NRZ to
NRZI data
H
L
O
-1.6
-2.4
V
V
4
SY
1601A-01.TBL
1
V
CC
GND
2k
4k
2k
EE
V
1601A-02.EPS
GND
EE
V
36
600
600
240
1601A-03.EPS
GND
V
CC
V
CC
3
4
EE
V
V
R3
30
10 0
1 00
30
2 k
2k
115
1601A-04.EPS
STV1601A
2/17
PIN DESCRIPTION (continued)
Pin
N
Symbol
Equivalent circuit
Description
I/O
Standard
Min. Typ. Max. Unit
29
V
CC
Parallel data and clock input
buffers power supply. When
this pin is connected to +5V,
parallel data clock turns to
TTL mode. When this pin is
connected to GND, parallel
data clock turns to ECL
mode.
-
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D9X
D9Y
D8X
D8Y
D7X
D7Y
D6X
D6Y
D5X
D5Y
D4X
D4Y
D3X
D3Y
D2X
D2Y
D1X
D1Y
D0X
D0Y
Parallel input ports:
LSB : D0X or Y
MSB : D9X or Y
Signal : DnX
Return : DnY
For ECL mode, V
CC
shalll be
0V
H
L
ForTTL mode, VCC shall be
+5V
H
L
-1.0
2.0
-1.6
0.8
V
V
V
V
28
RSE
VCO range selection
H : high range 140 to 270MHz
L : low range 100 to 145MHz
H
L
I
-0.4
-4.0
V
V
1601A-02.TBL
EE
V
29
6
7
2k
1k
V
R3
1601A-05.EPS
GND
E E
V
28
70k
2k
10k
10k
1601A-06.EPS
STV1601A
3/17
PIN DESCRIPTION (continued)
Pin
N
Symbol
Equivalent circuit
Description
I/O
Standard
Min. Typ. Max. Unit
30
PCX
Parallel clock (PCX) and its
return (PCY)
For ECL mode, V
CC
= 0
H
L
For TTL mode, V
CC
= +5V
H
L
I
-1.0
2.0
-1.6
0.8
V
V
V
V
31
PCY
2, 5,
32
GND
GND
26
V
EE
-5V power supply
I/O buffer PLL
-5.2
-5.0
-4.8
V
27
V
EE
-5V power supply
Logic part
-5.2
-5.0
-4.8
V
33
FV
VCO free running frequency
adjustment :
V
EE
level gives the lowest
frequency. To adjust, set
TN1 high.
I
-3.9
V
34
TRP
VCO input and phase
comparator output should be
connected to a parallel clock
frequency trap filter to
minimize jitter
O
-3.2
V
35
TN1
Test mode :
High : VCO free running
condition (input disabled)
Low : Normal mode (input
enabled)
I
-1.0
-4.5
V
V
1601A-03.TBL
EE
V
2k
V
R3
30
31
V
CC
2k
2k
1601A-07.EPS
GND
34
33
E E
V
1k
1k
1k
1k
1k
10k
0.1
F
V
CC
0.022
F
V
9
2
F
220
1601A-08.EPS
1
V
CC
GND
EE
V
V
R3
20k
12k
4k
1601A-09.EPS
STV1601A
4/17
PLL LOCK
DE TECTOR
VCO
TIMING
GENERATOR
NRZ
NRZI
000hex
DETECTO R
PHAS E
DETECT OR
35
30
31
33
34
28
36
PAR ALE LL TO SERIAL CONVER TER
X
+ X + 1 SCR AMBLER
9
4
1
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
29
27
26
32
5
2
37 N.C.
GND
GND
GND
V
EE
V
EE
CC
V
PCY PCX
TN1
FV
TRP
RSE
PCK
LST
SX
SY
D9X
D9Y
D8X
D8Y
D7X
D7Y
D6X
D6Y
D5X
D5Y
D4X
D4Y
D3X
D3Y
D2X
D2Y
D1X
D1Y
D0X
D0Y
Parallel Clock
Serial
Clock
Parallel
Load
10-BIT X 3 WORD SHIFT REGISTER
1601A-10.EPS
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
EE
Supply Voltage
-6
V
V
CC
Supply Voltage
+6
V
V
IN
Input Voltage
V
EE
to V
CC
V
I
OUT
Output Current
-30
mA
T
oper
Operating Temperature
0 to 65
o
C
T
stg
Storage Temperature
-50 to 125
o
C
P
D
Allowable Power Dissipation
2.0
W
1601A-04.TBL
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
EE
Supply Voltage
-4.8 to -5.2
V
V
CC
Supply Voltage *
4.8 to 5.2
V
T
oper
Operating Temperature
0 to 65
o
C
* For TTL input. Voltages are given with respect to GND
1601A-05.TBL
ELECTRICAL CHARACTERISTICS (V
EE
= -5V, V
CC
= GND/+5V, T
A
= 25
o
C unless otherwise speciied)
Symbol
Parameter
Test Conditions
Test Circuit
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS
I
EE
Supply Current 1
Figure 2
140
mA
I
CC
Supply Current 2
7
mA
1601A-06.TBL
STV1601A
5/17
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