September 2003

1/24

Main Features

I²C Bus Control

5 Y/CVBS Inputs, 3 Y/CVBS Outputs

3 C Inputs, 1 C Output

2 RGB/YPrPb Inputs, 1 RGB/YPrPb Output

6 dB Gain on all 150

Buffer Outputs

Integrated 150

Buffers

Video Muting on all Outputs

Bottom Clamp on all CVBS/Y, Average
Clamp on C Inputs, Bottom Clamp on RGB,
Sync-tip Clamp on PrPb signals

Bandwidth: 17 MHz

Crosstalk: 50 dB

Description

The STV6618 is a highly integrated I²C bus-
controlled video switch matrix, optimized for use in
recordable Digital Video Disk applications or DVD
players. It is adapted to video signals with 1H and
2H formats video routings. It provides required for
connections to two external devices (Europe 2
SCARTs), internal tuners, digital encoders and
recorders.

TQFP44

(10 x 10 x 1.4 mm)

(Thin Full Plastic Quad Flat Pack)

ORDER CODE: STV6618

STV6618

Video Switch Matrix for DVDs

STV6618

2/24

Table of Contents

Chapter 1

GENERAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1

Pin Connections .................................................................................................................. 3

1.2

Pin Description ................................................................................................................... 4

Chapter 2

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1

Absolute Maximum Ratings ................................................................................................ 7

2.2

Thermal Data ...................................................................................................................... 7

2.3

Recommended Operating Conditions .................................................................................. 7

2.4

Video Section Characteristics .............................................................................................. 8

2.5

Fast Blanking Section Characteristics ................................................................................. 9

2.6

Chroma Section Characteristics ......................................................................................... 10

2.7

Digital Outputs .................................................................................................................... 10

2.8

I²C Bus Characteristics ...................................................................................................... 11

Chapter 3

I²C BUS SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.1

I²C Bus Addresses ............................................................................................................. 12

3.2

Power-on Reset: Bus Register Initial Conditions ............................................................... 15

Chapter 4

INPUT/OUTPUT GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Chapter 5

APPLICATION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Chapter 6

PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Chapter 7

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3/24

STV6618 GENERAL

OVERVIEW

GENERAL OVERVIEW

1.1

Pin Connections

Figure 1: Pinout Diagram

FBOUT_TV

FBIN_AUX

VDD

SCL

SDA

GNDD

CIN_TV

Y/CVBSIN_TV

DIGOUT1

CIN_TUN

Y/C

CCB

R/P

/
C

CCB

PBO

NDB

Y/C

CCB

Y/CVBSOUT_REC
VCCB_REC
Y/CVBSIN_AUX

R/PR/CIN_AUX
DIGOUT5
G/YIN_AUX

B/PBIN_AUX
GND2

B/P

/
YI

/CI

VBSI

34
35
36
37
38
39
40
41
42
43
44

DIGOUT2

DIGOUT4

DIGOUT6

GNDB_REC

ND1

BSI

GENERAL OVERVIEW

STV6618

4/24

1.2

Pin Description

Pin No.

Symbol

Description

Y/CVBSIN_TUN

Y/CVBS Input from Tuner

DIGOUT3

Digital Output Pin 3

GND1

Ground Supply 1 for Video Inputs

CVBSIN_ENC

CVBS Input from Encoder

DECV

Video decoupling capacitor

CIN_ENC

Chroma Input from Encoder

YIN_ENC

Y Input from Encoder

+5 V Power Supply for Video Inputs

R/PR/CIN_ENC

Red or Pr or Chroma Input from Encoder

G/YIN_ENC

Green or Y Input from Encoder

B/PBIN_ENC

Blue or Pb Input from Encoder

GND2

Ground Supply 2 for Video Inputs

B/PBIN_AUX

Blue or Pb Input from Auxiliary (SCART2 or external Cinch)

DIGOUT4

Digital Output Pin 4

G/YIN_AUX

Green or Y Input from Auxiliary (SCART2 or external Cinch)

DIGOUT5

Digital Output Pin 5

R/PR/CIN_AUX

Red or Pr or Chroma input from Auxiliary (SCART2 or external Cinch)

DIGOUT6

Digital Output Pin 6

Y/CVBSIN_AUX

Y/CVBS Input from Auxiliary (SCART2 or external Cinch)

VCCB_REC

Video Output Recorder Buffer Supply Pin

Y/CVBSOUT_REC

Y/CVBS Output to Recorder

GNDB_REC

Ground Supply for Recorder Buffer

COUT_AUX

Chroma Output to Auxiliary (SCART2 or external Cinch)

VCCB1

Video Output Buffer Supply Pin

Y/CVBSOUT_AUX

Y/CVBS Output to Auxiliary (SCART2 or external Cinch)

GNDB

Ground Supply for Video Buffer

B/PBOUT_TV

Blue or Pb Output to TV (SCART1 or external Cinch)

C_GATE

External Transistor Command for Bidirectinnal B/C SCART I/O

G/YOUT_TV

Green or Y Output to TV (SCART1 or external Cinch)

VCCB2

Video Buffer

R/PR/COUT_TV

Red or Pr or Chroma Output to TV (SCART1 or external Cinch)

VCCB3

Video Output Buffer Supply Pin

Y/CVBSOUT_TV

Y/CVBS Output to TV (SCART1 or external Cinch)

FBOUT_TV

Fast Blanking Output to TV (SCART1)

FBIN_AUX

Fast Blanking Input from Auxiliary (SCART2)

5/24

STV6618 GENERAL

OVERVIEW

VDD

+5 V Digital Power Supply

SCL

I²C Bus Clock

SDA

I²C Bus Data

GNDD

Digital Ground Supply

CIN_TV

Chroma Input from TV (SCART1 or external Cinch)

Y/CVBSIN_TV

Y/CVBS Input from TV (SCART1 or external Cinch)

DIGOUT1

Digital Output Pin 1

CIN_TUN

Chroma Input from Tuner

DIGOUT2

Digital Output Pin 2

Figure 2: STV6618 Input/Output Diagram

Pin No.

Symbol

Description

SCART1

R/PR/COUT_TV

G/YOUT_TV

B/PBOUT_TV

FBOUT_TV

Y/CVBSOUT_TV

Y/CVBSIN_TV

Tuner

Y/CVBSIN_TUN

Encoder

R/PR/CIN_ENC

G/YIN_ENC

B/PBIN_ENC

CVBSIN_ENC

CIN_ENC

YIN_ENC

Recorder

Y/CVBS_REC

SCART2

R/PR/CIN_AUX

G/YIN_AUX

B/PB_AUX

FBIN_AUX

Y/CVBSIN_AUX

COUT_AUX

COUT_REC

CIN_TV

Transistor

C_GATE

STV6618

(TQFP 44)

DIGOUT1

DIGOUT2

Y/CVBSOUT_AUX

CIN_TUN

DIGOUT3

DIGOUT4

DIGOUT5

DIGOUT6

(Auxiliary)

GENERAL OVERVIEW

STV6618

6/24

Figure 3: STV6618 Block Diagram

VBSI

I
N

VBSI

/
YI

/
P

PBI

/
YI

/
P

PBI

t
e

0 d

VBSO

STV6

r
d

t
e

6 dB

VBSO

t
e

6 d

VBSO

t
e

6 d

/
P

r
/
C

t
e

6 d

t
e

6 d

/
P

Y/CVBS_TUN

Y/CVBS_TV

Y/CVBS_AUX

CVBSIN_ENC

YIN_ENC

CIN_TV

CIN_ENC

G/YIN_ENC

G/YIN_AUX

R/Pr/CIN_AUX

B/PbIN_AUX

R/Pr/CIN_ENC

B/PbIN_ENC

I
N

C_GATE

I
²C B

I
N

/
CV

I
N

t
e

6 d

/
CV

I
N

__T

r
/
C

I
N

r
/
CI

G/Y

/
YI

I
N

CIN_TUN

N__T

DIGOUT1

DIGOUT2

DIGOUT3

DIGOUT4

DIGOUT5

DIGOUT6

. Cl

.
C

l
a

t/Sy

/
A

v
.

. /

t
/
Sy

/Av

. /

7/24

STV6618 ELECTRICAL

CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

2.1

Absolute Maximum Ratings

2.2

Thermal Data

2.3

Recommended Operating Conditions

AMB

= 25 °C, V

CCV

= 5 V, V

= 5 V, R

OUT_VREC

= 4.7 k

, R

OUT_VBUF

= 150

, unless otherwise

specified. Output impedances of sources: R

= 75

Symbol

Parameter

Value

Unit

Digital Section

CCV

Video Section

Voltage at Pin 1 to GND
- Video pins
- Bus pins, DIGOUT1,2,3 and C_GATE

0, 5.5
0, 5.5

DIGOUT4-5-6

Voltage at pin DIGOUT4-5-6

0, 13

ESD

Maximum ESD voltage allowed. 100 pF capacitor discharged through
1.5 k

serial resistor (Human Body Model)

±4

OPER

Operating Ambient Temperature

0, +70

°C

STG

Storage Temperature

-20, +150

°C

Symbol

Parameter

Value

Unit

thJA

Junction-ambient Thermal Resistance (Maximum) on a single-layer
board

°C/W

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply Voltages

Digital Supply Voltage

4.75

5.00

5.25

CCV

Video Operating Supply Voltage

4.75

5.00

5.25

Active Mode (All channels ON)

Digital Supply Current

= 5 V,

3.5

5.0

6.5

CCV

Total Video Supply Current

CCV

= 5 V, No Load

Standby Mode (All channels OFF)

Digital Supply Current

= 5 V

3.0

4.5

6.0

CCVSTD

Total Video Supply Current

= 5 V

0.5

1.0

ELECTRICAL CHARACTERISTICS

STV6618

8/24

2.4

Video Section Characteristics

AMB

= 25 °C, V

CCV

= 5 V, V

= 5 V, R

OUT_VREC

= 4.7 k

, R

OUT_VBUF

= 150

, unless otherwise

specified. Output impedances of sources: R

= 75

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DCIN_BOT

DC Input Level

Bottom Sync Pulse

1.9

2.0

2.2

CLAMP_BOT

Clamping Current, Bottom clamp

at V

DCIN

- 400 mV

LEAK

Input Leakage Current

= V

DCIN

+ 1 V,

Bottom clamp input

µA

DCIN_YSYNC

DC Input Level

Y input, YPrPb mode, Black Level

2.2

2.3

2.5

DCIN_SYNC

DC Input Level

Sync clamp input (Pr,Pb)
Sync signal on Y input

2.9

3.0

3.1

CLAMP_SYNC

Max. Clamping Current during Sync
Clamp

Sync clamp input (Pr,Pb)
at V

DCIN

- 400 mV

100

µA

Input Capacitance

Maximum Input Signal

Y/CVBS, RGB

Pr, Pb

1.5
1.0

DYN

Dynamic Output Signal

Y/CVBS, RGB

Pr, Pb

3
2

Bandwidth at -3 dB
Y/CVBS OUT
RGB OUT
Pr/Pb OUT

= 0.7 V

14
14
14

17
17
17

MHz

Flatness

Video Band Gain Spread
(15 kHz to 5 MHz)
Y/CVBS OUT
RGB OUT
Pr/Pb OUT

= 1 V

= 0.7 V

±0.5
±0.5
±0.5

CTi

Crosstalk Isolation between Input
Channel

= 1 V

at 4.43 MHz on 1 point

CTo

Crosstalk Isolation between Output
Channel

= 1 V

at 4.43 MHz on 1

point, R

LOAD

= 150

OUT

Output Resistance

G0V

Gain at video outputs (0 dB), recorder
output

= 1 V

and Gain = 0 dB at

1 MHz

-0.5

0.0

0.5

G6V

Gain at video outputs (6 dB)

= 1 V

and Gain = 6 dB at

1 MHz

5.5

6.0

6.5

RGBmatch

Gain matching Between RGB outputs

= 0.7 V

and Gain = 6 dB at

1 MHz

-0.3

0.3

OUTZY/CVSS

DC Output Voltage,
TV and AUX Y/CVBS outputs

Bottom Sync Pulse

Mute

0.32
0.57

0.40
0.60

0.43
0.67

OUTREC

DC Output Voltage,
Recorder Y/CVBS Output

Bottom Sync Pulse

Mute

1.2
1.3

1.3
1.4

1.4
1.5

9/24

STV6618 ELECTRICAL

CHARACTERISTICS

2.5

Fast Blanking Section Characteristics

OUTRGB

DC Output Voltage, RGB outputs

Black Level

Mute

0.45
0.50

0.60
0.60

0.70
0.70

OUTYOUT

DC Output Voltage, TV Y Output (G/
YOUT_TV, YPrPb mode)

Bottom Sync Pulse

Mute

0.50
0.45

0.60
0.60

0.70
0.70

OUTPrPb

DC Output Voltage, PrPb outputs

Black Level

Mute

1.4
1.4

1.5
1.5

1.6
1.6

DPHI

Differential Phase, Y/CVBS

= 1 V

at 4.43 MHz

0.2

2.5

deg.

Differential Gain, Y/CVBS

= 1 V

at 4.43 MHz

0.3

Mute

Mute Suppression

= 1 V

at 5 MHz on 1 point

-55

LNL

Luminance non-linearity

0.3

VSN

Video Signal-to-Noise Ratio

1. Minimum Crosstalk values estimated during Qualification phase, based on ST Evaluation Board

measurement, TQFP44 package soldered on board.

2. Measured at IC output pin.

3. Signal-to-Noise = 20log (VOUTblack-to-white = 0.7 V

/ Vnoise(mVrms) weighted CCIR 567)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

INPUT MODE

LOW/HIGH

Input Low/High Level Threshold

0.4

0.7

0.9

Input Current

µA

OUTPUT MODE

LOW

Output Low Level

LOAD

= 150

0.5

HIGH

Output High Level

LOAD

= 150

3.0

3.4

3.8

DEL

Fast Blanking RGB delay

At 50% on digital RGB
transients, at 2 V on FB rise
transient, at 1 V on FB fall,
C

LOAD

= 10 pF maximum

TRANS

FB Transitions at FB output

Rise Time
Fall Time

LOAD

= 10 pF maximum

between 10% and 90%
between 90% and 10%

10
10

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

ELECTRICAL CHARACTERISTICS

STV6618

10/24

2.6

Chroma Section Characteristics

AMB

= 25 °C, V

CCV

= 5 V, V

= 5 V, R

OUT_VREC

= 4.7 k

, R

OUT_VBUF

= 150

unless otherwise

specified. Output impedances of sources: R

= 75

2.7

Digital Outputs

AMB

= 25 °C, V

CCV

= 5 V, V

= 5 V.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DCIN

DC Input Level

2.9

3.0

3.1

Input Resistance

Input Capacitance

Max Input Signal

1.0

DYN

Dynamic Output Signal

2.0

OUT

DC Output Voltage
AUX C Output

No Chroma input signal

1. Measured at IC output pin.

1.4

1.5

1.6

CBW

Chroma Bandwidth

= 1 V

at -3 dB

MHz

CTi

Crosstalk Isolation between Input
Channel

= 1 V

at 4.43 MHz,

on one input

2. Minimum Crosstalk values estimated during Qualification phase, based on ST Evaluation Board

measurement, TQFP44 package soldered on board.

CTo

Crosstalk Isolation between Output
Channel

= 1 V

at 4.43 MHz,

on one input, R

LOAD

= 150

OUT

Output Resistance

G6C

Gain at Chroma Outputs

= 1 V

and Gain = 6 dB at

1 MHz

5.5

6.0

6.5

Mute

Mute Suppression

= 1 V

at 4.43 MHz, on one

input

-55

CToYdel

Chroma to Luma Delay, Source Y/C

= V

at 4.43 MHz

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

C_gate_H

Pull-up resistor value to VccB3

C_gate_L

Output Low level

= 0 mA

= 1 mA

0.3
0.7

C_gate_H

Output High level

LOAD

= 20 k

DIGOUT1-2-3 Load

External pull-up resistor value to VDD

DIGOUT1-2-3 Low

Output low level, DIGOUT1-2-3

LOAD

= 10 k

0.7

DIGOUT1-2-3 Middle

Output middle level, DIGOUT1-2-3

LOAD

= 10 k

2.2

DIGOUT1-2-3 High

Output high level,DIGOUT1-2-3

LOAD

= 10 k

Opened collector output

DIGOUT4-5-6 Low

Output low level, DIGOUT4-5-6

LOAD

= 2 mA

0.7

DIGOUT4-5-6 High

Output high level, DIGOUT4-5-6

Opened Collector Output

11/24

STV6618 ELECTRICAL

CHARACTERISTICS

2.8

I²C Bus Characteristics

AMB

= 25 °C, V

CCV

= 5 V, V

= 5 V

Note:

The device can also operate at 400 kHz and can interface with +3.3 V or + 5 V logic levels.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

SCL

Low Level Input Voltage

-0.3

1.5

High Level Input Voltage

2.3

5.5

Input Leakage Current

= 0 to 5.5 V

-10

µs

SDA

Low Level Input Voltage

-0.3

1.5

High Level Input Voltage

2.3

5.5

Input Leakage Current

= 0 to 5.5 V

-10

µs

Input Capacitance

Input Rise Time

1.5 V to 3 V

µs

Input Fall Time

3 V to 1.5 V

300

Low Level Output Voltage

= 3 mA

0.4

Output Fall Time

3 V to 1.5 V

250

Load Capacitance

400

TIMING

LOW

Clock Low Period

4.7

µs

HIGH

Clock High Period

µs

SU,DAT

Data Setup Time

250

HD,DAT

Data Hold Time

340

SU,STO

Setup Time from Clock High to Stop

µs

BUF

Start Setup Time following a Stop

4.7

µs

HD,STA

Start Hold Time

µs

SU,STA

Start Setup Time following Clock Low to High Transition

4.7

µs

Figure 4: I²C Bus Timing

tBUF

tLOW

tHIGH

tHD,STA

tSU,STA

tHD,DAT

tSU,DAT

tSU,STO

SDA

SCL

SDA

I²C BUS SELECTION

STV6618

12/24

I²C BUS SELECTION

Data transfers follow the usual I²C format; i.e. after the start condition (S), a 7-bit slave address is
sent, followed by an eight-bit data direction bit (W). An 8-bit sub-address is sent to select a register,
followed by an 8-bit data word to be included in the register. The IC's I²C bus decoder enables the
automatic incrementation mode in write mode.

String Format

Write only mode (S = Start condition, P = Stop condition, A = Acknowledge)

Read only mode

Slave Address

Auto Increment Mode

3.1

I²C Bus Addresses

Write Address: 1001 0100 = 94(hex)
Input Signal Summary (Write Mode)

Slave Address

Sub-address

Data

Slave Address

Data

Address

Value

Slave Address

Sub-address

DATA0

DATA1

....

DATAn

Sub-Address

Sub-Address +1 Sub-Address + N

Reg

Addr

(Hex)

Data

Y/CVBS and C Output Selection

DigOUT6

Not Used

TV Y/CVBS Output Selection

Recorder Y/CVBS Output Selection

DigOUT5

Not Used

Auxiliary C Output Selection

Auxiliary Y/CVBS Output Selection

RGB/YPrPb & Fast Blanking Selection

RGB/YPrPb

High Impedance State

RGB or YPrPb or C mode

Selection

Auxiliary or Encoder

Selection

Fast Blanking Selection

Digital Outputs

DIGOUT4

DIGOUT3

DIGOUT2 Control

DIGOUT1 Control

C_GATE

Control

13/24

STV6618

I²C BUS SELECTION

Note:

Unused data must be set to "0".

Standby

TV Output

Standby

AUX Chroma

Output

Standby

AUX CVBS

Output

Standby

REC Output

Standby

AUX Input

Disable

TV Input

Disable

TUN Input

Disable

ENC Input

Disable

Reg.

Addr

(Hex)

Description

Bits

Data

Comments

Recorder Y/CVBS Output
Selection

X
X
X
X
X
X
X
X

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Mute
YIN_ENC
CVBSIN_ENC
Y/CVBSIN_AUX
Y/CVBSIN_TV
YCVBSIN_TUN
Not allowed
Not allowed

TV Y/CVBS Output
Selection

X
X
X
X

0
0
1
1

0
1
0
1

X
X
X
X

Y/CVBS_AUX
YIN_ENC
CVBSIN_ENC
Mute

DigOUT6 Control

0
1

X
X

0 = Low Level
1 = High Level

AUX (SCART2) Y/CVBS
Output Selection

X
X
X
X
X
X
X
X

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Y/CVBSin_TV
YIN_ENC
CVBSIN_ENC
YCVBSIN_TUN
Mute
Not allowed
Not allowed
Not allowed

AUX (SCART2) Chroma
Output Selection

X
X
X
X

0
0
1
1

0
1
0
1

X
X
X
X

Mute
CIN_ENC
CIN_TV
CIN_TUN

DigOUT5 Control

0
1

X
X

0 = Low Level
1 = High Level

Reg

Addr

(Hex)

Data

I²C BUS SELECTION

STV6618

14/24

Reg.

Addr

(Hex)

Description

Bits

Data

Comments

Fast Blanking Output Control

X
X
X
X

0
0
1
1

0
1
0
1

FBIN_AUX
FB forced to Low Level
FB forced to High Level
Not allowed

RGB/YPrPb Output Selection

X
X
X

0
0
1

0
1
0

X
X
X

RGB/YPrPb_AUX
RGB/YPrPb_ENC
CIN_ENC (pin 6) at R/Pr/COUT_TV,
B/PbOUT & G/YOUT muted
RGB/YPrPb mute

RGB or YPrPb or C Selection

RGB mode selection, bottom clamp at
RGB inputs, AUX. input selected

RGB mode selection, bottom clamp at
RGB inputs, ENC. input selected

CIN_AUX (pin 17)selected, average
clamp at R/Pr/CIN_AUX input,
GIN_AUX (bottom clamp) selected,
BIN_AUX (bottom clamp) selected

CIN_ENC (pin 9)selected, average
clamp at R/Pr/CIN_ENC input,
GIN_ENC (bottom clamp) selected,
BIN_ENC (bottom clamp) selected

YPrPb mode selection, sync pulse
clamp at Pr Pb inputs, black clamp at Y
input, AUX. input selected

YPrPb mode selection, sync pulse
clamp at Pr Pb inputs, black clamp at Y
input, ENC. input selected

YPrPb mode selection, delayed sync
pulse clamp at Pr Pb inputs, black
clamp at Y input, AUX. input select

YPrPb mode selection, delayed sync
pulse clamp at Pr Pb inputs, black
clamp at Y input, ENC. input select

RGB/YPrPb Control

0
0
1

0
1

X
X
X

RGB/YPrPb outputs active
RGB/YPrPb outputs high imp state
Red output active, Green and Blue
high imp. state

15/24

STV6618

I²C BUS SELECTION

3.2

Power-on Reset: Bus Register Initial Conditions

Power-on Reset is active when supply V

< 3.5 V. Non-significant bits (X) are pre-set to "0".

Reg.

Addr

(Hex)

Description

Bits

Data

Comments

C_Gate Output Control

X
X

0
1

Low Level
High Level

DIGOUT1

X
X
X

0
1
1

0
1

X
X
X

Low Level
Mid Level
High Level

DIGOUT2

X
X
X

0
1
1

0
1

X
X
X

Low Level
Mid Level
High Level

DIGOUT3

X
X
X

0
1
1

0
1

X
X
X

Low Level
Mid Level
High Level

DIGOUT4 Control

0
1

X
X

0 = Low Level
1 = High Level

ENC Inputs

X
X

0
1

Inputs Active
Inputs Disabled

TUN Inputs

X
X

0
1

X
X

Inputs Active
Inputs Disabled

TV Inputs

X
X

0
1

X
X

Inputs Active
Inputs Disabled

AUX Inputs

X
X

0
1

X
X

Inputs Active
Inputs Disabled

REC Outputs

X
X

0
1

X
X

Y/CVBSOUT_REC Outputs ON
Y/CVBSOUT_REC Outputs OFF

AUX Outputs

X
X

0
1

X
X

Y/CVBSOUT_AUX Outputs ON
Y/CVBSOUT_AUX Outputs OFF

COUT_AUX Output

X
X

0
1

X
X

COUT_AUX Outputs ON
COUT_AUX Outputs OFF (high imped.)

TV Outputs

0
1

X
X

TV Video Outputs ON
TV Video Outputs OFF

Full Stop

Only I²C bus supplied, and digital outputs

Reg.

Addr

(Hex)

Data

Comments

Rec. CVBS output muted, TV CVBS output to Aux. CVBS input, Digital output
low level

Aux. CVBS output to TV CVBS input, Aux. Chroma output muted, Digital
output low level

FB output to Aux. FB input, TV RGB output to Aux. RGB inputs, RGB outputs
active

C_gate output low level, DIGOUT outputs low level

All inputs outputs active

INPUT/OUTPUT GROUPS

STV6618

16/24

INPUT/OUTPUT GROUPS

Figure 5: C_Gate Logic Output (Pin 28)

Figure 6: Video Outputs (Pins 23, 25, 27, 29, 31 and 33)

Figure 7: YCVBSOUT_REC Recorder Output (Pin 21)

5 V

18 k

5 V

Protected Pad

CCB1,2,3

Protected Pad

CCB1,2,3

CCB_REC

5 V

Protected Pad

CCB_REC

5 V

Figure 8: Fast Blanking Inputs (Pin 35)

Figure 9: I²C Bus SCL I/O (Pin 37)

Figure 10: Fast Blanking Output (Pin 34)

CCB3

Protected Pad

5 V

tri

VDD_FLOAT

10 k

5 V

Protected Pad

CCB3

Protected Pad

17/24

STV6618 INPUT/OUTPUT

GROUPS

Figure 11: Bottom Clamped Video Inputs

(Pins 1, 4, 7, 19 and 41)

Figure 12: DIGOUT 1, 2 and 3 (Pins 42, 44 and 2)

Figure 13: DIGOUT 4, 5 and 6 (Pins 14, 16 and 18)

15 k

5 V

tri

5 V

Protected Pad

5 k

2V + V

Float_Bus

5 V

Float_DigOUT

5 V

Figure 14: Average Clamped Video Inputs

(Pins 6, 40 and 43)

Figure 15: DECV (Pin 5)

Figure 16: I²C Bus SDA I/O (Pin 38)

25 k

5 V

Protected Pad

5 k

25 k

tri

Protected Pad

5 V

Protected Pad

10 k

40 k

5 V

VDD_FLOAT

Acknowledge

10 k

5 V

Protected Pad

APPLICATION DIAGRAMS

STV6618

20/24

APPLICATION DIAGRAMS

Figure 21: YPrPb Application

R55

R40
75

J5
Y

J6
Pb

R46

10K

R41

AUX INPUTS

S-VHS

R56

12V

VCC

R53

C46

100n

C41

100n

NPN

C44

100n

J12
Pb

R30 to R35: expected loads
on Decoder outputs

R35
75

Y/CVBS

C25

100n

R32

R34
75

J2
C

Tuner Y/CVBS

J11
Y

Y/CVBS

ENC Y

R47

10K

R50

10K

ENC Pr

C48

100n

C29

100n

C30
100n

R49

10K

C28

10µ

R36
75

ENC Pb

DOut 2

Y/CVBS

C32

100n

C42

10µ

C39

100n

R43 75

C36

1µ

ENC CVBS

C26

100n

R54

R39
75

R51

J8
C

C43

100n

SCL

DOut 6

VDD

J10
Pr

VCC

REC Y/CVBS

VCCB

C40

47n

Tuner C

Y/CVBS

R37
75

ENC C

J4
Pr

DOut 4

C35

100n

R44

DOut 1

AUX OUTPUTS

VCCB

C33

100n

ENC Y

TV OUTPUTS

R30
75

R48

10K

C37

100n

C27

100n

VCCB

R33
75

C34

100n

R38

R45

10K

SDA

C38

100n

REC C

TV INPUTS

R31
75

R42
470

C31

10µ

DOut 5

DOut 3

C47

1µ

All grounds must be linked un der the IC

R52

C45

100n

STV6618

CVBSI

ENC

VCC

ENC

DECV

/
P

r
/C

/
YI

ENC

I
N

GND1

Y/CVBSIN_TV

CIN_TV

GND2

Y/CVBSIN_AUX

DigOUT4

R/Pr/CIN_AUX

DigOUT5

G/YIN_AUX

DigOUT6

B/PbIN_AUX

VCCB_REC

Y/CVBSOUT_REC

GNDB_REC

CVBSO

UT_

VCCB1

COUT

VCCB2

CVBSO

UT_

/
Pr

/
C

T_TV

VCCB3

GAT

/
P

b_O

_TV

FBOUT_TV

FBIN_AUX

VDD

SCL

SDA

GNDD

DigOUT1

CVBSI

TUN

DigOUT2

CIN_TUN

GNDB

21/24

STV6618 APPLICATION

DIAGRAMS

Figure 22: 2 SCART / RGB Signal Application

ENC C

C24

100n

R8
75

C14

100n

Tuner C

R10
75

R28

C17

100n

DOut 1

100n

R25

VCC

ENC B

DOut 4

R11
75

DOut 5

10µ

R19

10K

VCCB

ENC R

All grounds must be linked un der the IC

VCC

C22

100n

C12

100n

C13

100n

C23

100n

R23

10K

R9
75

C18

10µ

R24

R4
75

100n

SDA

R22

10K

R2
75

JFET N

AUX1
SCART

R13 to R18: expected loads
on Decoder outputs

SCL

VDD

C11

100n

C15

100n

C20

100n

R17

4K7

REC Y/CVBS

STV6618

CVBSI

N_ENC

VCC

N8ENC

DECV

/
C

I
N

_ENC

N_ENC

PbI

_ENC

GND1

Y/CVBSIN_TV

CIN_TV

GND2

Y/CVBSIN_AUX

DigOUT4

R/Pr/CIN_AUX

DigOUT5

G/YIN_AUX

DigOUT6

B/PbIN_AUX

VCCB_REC

Y/CVBSOUT_REC

GNDB_REC

CVBSOUT_AUX

VCCB1

COUT_AUX

VCCB2

CVBSOUT_TV

/
C

OUT_TV

VCCB3

YOUT_TV

C_GATE

Pb_OUT_TV

FBOUT_TV

FBIN_AUX

VDD

SCL

SDA

GNDD

DigOUT1

CVBSI

N_TUN

DigOUT2

CIN_TUN

gOUT3

GNDB

100n

R27

DOut 6

R3
75

R21

10K

C16

47n

C10

100n

12V

R20

10K

DOut 3

Tuner Y/CVBS

DOut 2

R26

100n

C21

100n

10µ

VCCB

R12
75

R29

ENC Y

TV1
SCART

R5
75

ENC G

C19

100n

R7
75

JFET N

ENC CVBS

100n

R18

10K

C6
100n

PACKAGE MECHANICAL DATA

STV6618

22/24

PACKAGE MECHANICAL DATA

Figure 23: 44-Pin Thin Quad Flat Package

1.60

0.063

0.05

0.15

0.002

0.006

1.35

1.40

1.45

0.053 0.055 0.057

0.30

0.37

0.45

0.012 0.015 0.018

0.09

0.20

0.004

0.008

12.00

0.472

10.00

0.394

8.00

0.315

12.00

0.472

10.00

0.394

8.00

0.315

0.80

0.031

0°

3.5°

7°

0.45

0.60

0.75

0.018 0.024 0.030

1.00

0.039

Number of Pins

0.10m

.004

seating plane

23/24

STV6618 REVISION

HISTORY

REVISION HISTORY

The following table summarizes the modifications applied to this document.

Revision

Description

Date

1.0

First Issue

24 April 2001

New pinout proposal, to improve connection to TV SCART. Slight correction of electrical
parameters (changed value in Bold). Correction of DigOUT1-2-3 I²C control specification
(changed value in bold)

27 April 2001

New pinout proposal, To improve connection to SCARTs. Application layout hypothesis: 1
layer PCB, IC on lower side (copper side), SCART on upper side

7 May 2001

Application diagrams added. VDCin chroma section: 3.0V instead of 2.3V previously.
VDCin , video section, PrPb: 3.0V instead of 2.3V previously

11 May 2001

Add Fast Blanking Section Electrical Characteristics. Update Application Schematic
Diagrams

7 June 2001

1.1

Addition of

Section 4: INPUT/OUTPUT GROUPS on page 16

21 June 2001

1.2

Document reformatted. Replaced

Figure 22: 2 SCART / RGB Signal Application

on page 21

6 July 2001

1.3

CIN = 1 VPP changed to "VIN = 1 VPP in CBW Parameter in

Section 2.6

. Symbols for a

PNP, NPN and current source as well as their connections added to

Figure 17

2 Oct 2001

1.4

Update of Crosstalk and DC Output voltage data in

Section 2.4

and

Section 2.6

Modification of Register 2 data in

Section 3.1

. Replaced

Figure 21

and

Figure 22

10 Oct 2001

1.5

Update of Crosstalk data and Output Voltage values in

Section 2.4

and

Section 2.6

Updated

Figure 3

and

Figure 22

26 Oct 2001

1.6

Chroma Output Gain (G6C) parameters updated in

Section 2.6

14 Jan 2002

1.7

Addition of minimum/maximum values for certain parameters in

Section 2: ELECTRICAL

CHARACTERISTICS

. Document upgraded to Datasheet status.

24 May 2002

1.8

Modification of Bandwidth parameter (17 MHz) and

Figure 3

24 Sept. 2002

REVISION HISTORY

STV6618

24/24

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously

supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without

express written approval of STMicroelectronics.

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