STV9420
STV9421
MULTISYNC ON-SCREEN DISPLAY FOR MONITOR
October 1995
DIP20
(Plastic Package)
ORDER CODE : STV9421
.
CMOS SINGLE CHIP OSD FOR MONITOR
.
BUILT IN 1 KBYTE RAM HOLDING :
- PAGES' DESCRIPTORS
- CHARACTER CODES
- USER DEFINABLE CHARACTERS
.
128 ALPHANUMERIC CHARACTERS OR
GRAPHIC SYMBOLS IN INTERNAL ROM
(12 x 18 DOT MATRIX)
.
UP TO 26 USER DEFINABLE CHARACTERS
.
INTERNAL HORIZONTAL PLL (15 TO 120kHz)
.
PROGRAMMABLE VERTICAL HEIGHT OF
CHARACTER WITH A SLICE INTERPOLATOR
TO MEET MULTI-SYNCH REQUIREMENTS
.
PROGRAMMABLE VERTICAL AND HORI-
ZONTAL POSITIONING
.
FLEXIBLE SCREEN DESCRIPTION
.
CHARACTER BY CHARACTER COLOR SE-
LECTION (UP TO 8 DIFFERENT COLORS)
.
PROGRAMMABLE BACKGROUND (COLOR,
TRANSPARENT OR WITH SHADOWING)
.
CHARACTER BLINKING
.
2-WIRES ASYNCHRONOUS SERIAL MCU
INTERFACE (I
2
C PROTOCOL)
.
4 x 8 BITS PWM DAC OUTPUTS ON THE
STV9421
.
SINGLE POSITIVE 5V SUPPLY
DIP16
(Plastic Package)
ORDER CODE : STV9420
DESCRIPTION
The STV9420/21 is an ON SCREEN DISPLAY for
monitor. It is built as a slave peripheral connected
to a host MCU via a serial I
2
C bus. It includes a
display memory, controls all the display attributes
and generates pixels from the data read in its on
chip memory. The line PLL and a special slice
interpolator allow to have a display aspect which
does not depend on the line and frame frequencies.
I
2
C interface allows MCU to make transparent in-
ternal access to prepare the next pages during the
display of the current page. Toggle from one page
to another by programming only one register.
4 x 8 bits PWM DAC are available (STV9421) to
provide DC voltage control to other peripherals.
The STV9420/21 provides the user an easy to use
and cost effective solution to display alphanumeric
or graphic information on monitor screen.
1/16
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.3, +7.0
V
V
IN
Input Voltage
-0.3, +7.0
V
T
oper
Operating Ambient Temperature
0, +70
C
T
stg
Storage Temperature
-40, +125
C
9420-02.TBL
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V, V
SS
= 0V, T
A
= 0 to 70
C, F
XTAL
= 8 to 15MHz, TEST = 0 V, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
SUPPLY
V
DD
Supply Voltage
4.75
5
5.25
V
I
DD
Supply Current
-
-
50
mA
INPUTS
SCL, SDA, TEST, RESET, V-SYNC and H-SYNC
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
0.8 V
DD
V
I
IL
Input Leakage Current
-20
+20
A
OUTPUTS
R, G, B, FBLK, SDA, CKOUT, PXCK and PWMi (i = 1 to 4)
V
OL
Output Low Voltage (I
OL
= 1.6mA)
0
0.4
V
V
OH
Output High Voltage (I
OL
= -0.1mA)
0.8 V
DD
V
DD
V
9420-03.TBL
For R, G, B and FBLK outputs, see Figure 1.
5
2.5
0
10
-5
10
-4
10
-3
10
-2
10
-1
I (A)
(V)
,
V
OL
OH
V
V
OL
OH
V
9420-17.EPS
Figure 1 : Typical R, G, B Outputs Characteristics
STV9420 - STV9421
4/16
TIMINGS
Symbol
Parameter
Min.
Typ.
Max.
Unit
OSCILATOR INPUT : XTI (see Figure 2)
t
WH
Clock High Level
35
ns
t
WL
Clock Low Level
35
ns
f
XTAL
Clock Frequency
6
15
MHz
f
PXL
Pixel Frequency
30
MHz
RESET
t
RES
Reset High Level Pulse
4
s
R, G, B, FBLK (C
LOAD
= 30pF)
t
R
Rise Time (Note 1)
5
ns
t
F
Fall Time (Note 1)
5
ns
t
SKEW
Skew between R, G, B, FBLK (Note 1)
5
ns
I
2
C INTERFACE : SDA AND SCL (see Figure 3)
f
SCL
SCL Clock Frequency
0
1
MHz
t
BUF
Time the bus must be free between 2 access
500
ns
t
HDS
Hold Time for Start Condition
500
ns
t
SUP
Set up Time for Stop Condition
500
ns
t
LOW
The Low Period of Clock
400
ns
t
HIGH
The High Period of Clock
400
ns
t
HDAT
Hold Time Data
0
ns
t
SUDAT
Set up Time Data
375
ns
t
F
Fall Time of SDA
20
ns
t
R
Rise Time of Both SCL and SDA
Depend on the pull-up resistor
and the load capacitance
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches comming from corners of our processes and also temperature characterization.
9420-04.TBL
XTI
t
W H
t
WL
9420-03.EPS
Figure 2
S DA
t
BUF
S CL
t
HDAT
S T OP
S TART
DATA
S TOP
t
S UDAT
t
HDS
t
S UP
t
HIGH
t
LOW
9420-04.EPS
Figure 3
STV9420 - STV9421
5/16
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