STV9425 - STV9425B
STV9426
MULTISYNC ON-SCREEN DISPLAY FOR MONITOR
December 1997
.
CMOS SINGLE CHIP OSD FOR MONITOR
.
BUILT IN 1 KBYTE RAM HOLDING :
- PAGES' DESCRIPTORS
- CHARACTER CODES
- USER DEFINABLE CHARACTERS
.
128 ALPHANUMERIC CHARACTERS OR
GRAPHIC
SYMBOLS
IN INTERNAL ROM
(12 x 18 DOT MATRIX)
.
UP TO 26 USER DEFINABLE CHARACTERS
.
INTERNAL HORIZONTAL PLL (15 TO 120kHz)
.
PROGRAMMABLE VERTICAL HEIGHT OF
CHARACTER WITH A SLICE INTERPOLATOR
TO MEET MULTI-SYNCH REQUIREMENTS
.
PROGRAMMABLE VERTICAL AND HORI-
ZONTAL POSITIONING
.
FLEXIBLE SCREEN DESCRIPTION
.
CHARACTER BY CHARACTER COLOR SE-
LECTION (UP TO 8 DIFFERENT COLORS)
.
PROGRAMMABLE BACKGROUND (COLOR,
TRANSPARENT OR WITH SHADOWING)
.
50MHz MAXIMUM PIXEL CLOCK
.
2-WIRES ASYNCHRONOUS SERIAL MCU
INTERFACE (I
2
C PROTOCOL)
.
8 x 8 BITS PWM DAC OUTPUTS (STV9425)
4 x 8 BITS PWM DAC OUTPUTS (STV9425B)
.
SINGLE POSITIVE 5V SUPPLY
SHRINK24
(Plastic Package)
ORDER CODES : STV9425 - STV9425B
DESCRIPTION
The STV9425/25B/26is an ON SCREEN DISPLAY
for monitor. It is built as a slave peripheral con-
nected to a host MCU via a serial I
2
C bus. It
includes a display memory, controls all the display
attributes and generates pixels from the data read
in its on chip memory. The line PLL and a special
slice interpolator allow to have a display aspect
which does not depend on the line and frame
frequencies. I
2
C interface allows MCU to make
transparent internal access to prepare the next
pages during the display of the current page. Tog-
gle from one page to another by programming only
one register.
DIP16
(Plastic Package)
ORDER CODE : STV9426
8 x 8 bits or 4 x 8 bits PWM DAC are available to
provide DC voltage control to other peripherals.
The STV9425/25B/26provides the user an easy to
use and cost effective solution to display alphanu-
meric or graphic information on monitor screen.
1/15
PIN DESCRIPTION
Symbol
Pin Number
I/O
Description
SDIP24
DIP16
PWM0
1 *
-
O
DAC0 Output
PWM1
2
-
O
DAC1 Output
FBLK
3
1
O
Fast Blanking Output
V-SYNC
4
2
I
Vertical Sync Input
H-SYNC
5
3
I
Horizontal Sync Input
V
DD
6
4
S
+5V Supply
PXCK
7
5
O
Pixel Frequency Output
CKOUT
8
6
O
Clock Output
XTAL OUT
9
7
O
Crystal Output
XTAL IN
10
8
I
Crystal or Clock Input
PWM2
11
-
O
DAC2 Output
PWM3
12 *
-
O
DAC3 Output
PWM4
13 *
-
O
DAC4 Output
PWM5
14
-
O
DAC5 Output
SCL
15
9
I
Serial Clock
SDA
16
10
I/O
Serial Input/Output Data
RESET
17
11
I
Reset Input (Active Low)
GND
18
12
S
Ground
R
19
13
O
Red Output
G
20
14
O
Green Output
B
21
15
O
Blue Output
TEST
22
16
I
Reserved (grounded in Normal Operation)
PWM6
23
-
O
DAC6 Output
PWM7
24 *
-
O
DAC7 Output
* Reserved with STV 9425B (not to be connected)
94
25
-
0
1
.
T
B
L
9
425-
01.
E
P
S
/
9
4
2
5
B
-
01.
E
P
S
/
942
6-
0
1
.
E
P
S
PIN CONNECTIONS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
24
23
22
21
11
12
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
SDA
SCL
GND
FBLK
B
G
R
RESET
VSYNC
HSYNC
CKOUT
XTAL IN
XTAL OUT
TEST
V
DD
PXCK
SDIP24 (STV9425)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBLK
V-SYNC
H-SYNC
PXCK
CKOUT
XTAL OUT
XTAL IN
V
DD
TEST
B
G
R
GND
RESET
SDA
SCL
DIP16 (STV9426)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
24
23
22
21
11
12
RES ERVED
P WM6
P WM5
RES ERVED
RESERVED
P WM2
P WM1
RESERVED
S DA
S CL
GND
FBLK
B
G
R
RES ET
VSYNC
HS YNC
CKOUT
XTAL IN
XTAL OUT
TE S T
V
DD
P XCK
SDIP24 (STV9425B)
STV9425 - STV9425B - STV9426
2/15
P WM3 *
P WM2
P WM1
P WM0 *
12
11
2
1
P WM7 *
P WM6
P WM5
P WM4 *
24
23
14
13
CKOUT
HS YNC
VSYNC
RES ET
R
G
B
FBLK
GND
S CL
S DA
XTAL
IN
XTAL
OUT
P XCK
TES T
Addre ss/Data
HORIZONTAL
DIGITAL P LL
4K ROM
(128 chara cte rs)
1K RAM
P a ge De scriptors +
Use r De fined Cha r.
DISP LAY
CONTROLLER
I C BUS
INTERFACE
2
8
5
4
17
1 9
2 0
21
3
18
15
1 6
V
DD
1 0
9
7
6
22
PWM
S TV94 25/25B
* Re s e rve d with STV9425B
9
425-
02.
E
P
S
STV9425
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CKOUT
HS YNC
VSYNC
RESET
R
G
B
FBLK
GND
SCL
SDA
XTAL
IN
XTAL
OUT
P XCK
TEST
V
DD
Addre s s /Da ta
HOR IZONTAL
DIGITALP LL
4K ROM
(128 cha ra cte rs )
1K RAM
P a ge De s criptors +
Us e r De fine d Cha r.
DISP LAY
CONTROLLER
I C BUS
INTERFACE
2
S TV94 26
9
426-
02
.
E
P
S
STV9426
BLOCK DIAGRAMS
STV9425 - STV9425B - STV9426
3/15
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.3, +7.0
V
V
IN
Input Voltage
-0.3, +7.0
V
T
oper
Operating Ambient Temperature
0, +70
C
T
stg
Storage Temperature
-40, +125
C
942
5-
0
2
.
T
B
L
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V, V
SS
= 0V, T
A
= 0 to 70
C, F
XTAL
= 8 to 15MHz, TEST = 0 V, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
SUPPLY
V
DD
Supply Voltage
4.75
5
5.25
V
I
DD
Supply Current
-
50
70
mA
INPUTS
SCL, SDA, TEST, RESET, V-SYNC and H-SYNC
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
0.8V
DD
V
I
IL
Input Leakage Current
-20
+20
A
OUTPUTS
R, G, B, FBLK, SDA, CKOUT, PXCK and PWMi (i = 0 to 7)
V
OL
Output Low Voltage (I
OL
= 1.6mA)
0
0.4
V
V
OH
Output High Voltage (I
OL
= -0.1mA)
0.8V
DD
V
DD
V
9425
-
0
3
.
T
B
L
For R, G, B and FBLK outputs, see Figure 1.
5
2.5
0
10
-5
10
-4
10
-3
10
-2
10
-1
I (A)
(V)
,
V
OL
OH
V
V
OL
OH
V
942
5-
1
7
.
E
P
S
Figure 1 : Typical R, G, B Outputs Characteristics
STV9425 - STV9425B - STV9426
4/15
TIMINGS
Symbol
Parameter
Min.
Typ.
Max.
Unit
OSCILATOR INPUT : XTI (see Figure 2)
T
WH
Clock High Level
20
ns
T
WL
Clock Low Level
20
ns
F
XTAL
Clock Frequency
TBD
15
MHz
F
PXL
Pixel Frequency
50
MHz
RESET
T
RES
Reset Low Level Pulse
4
s
R, G, B, FBLK (C
LOAD
= 30pF)
T
RISE
Rise Time (Note 1)
5
ns
T
FALL
Fall Time (Note 1)
5
ns
T
SKEW
Skew between R, G, B, FBLK (Note 1)
5
ns
I
2
C INTERFACE : SDA AND SCL (see Figure 3)
F
SCL
SCL Clock Frequency
0
1
MHz
T
BUF
Time the bus must be free between 2 access
500
ns
T
HDS
Hold Time for Start Condition
500
ns
T
SUP
Set up Time for Stop Condition
500
ns
T
LOW
The Low Period of Clock
400
ns
T
HIGH
The High Period of Clock
400
ns
T
HDAT
Hold Time Data
0
ns
T
SUDAT
Set up Time Data
375
ns
T
F
Fall Time of SDA
20
ns
T
R
Rise Time of Both SCL and SDA
Depend on the pull-up resistor
and the load capacitance
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches comming from corners of our processes and also temperature characterizat ion.
942
5-
04.
T
B
L
XTI
TWH
TWL
94
25
-
0
3
.
A
I
Figure 2
SDA
T
BUF
T
HDS
T
SUDAT
T
HIGH
T
LOW
SCL
T
HDAT
T
SUP
STOP
START
DATA
STOP
942
5-
0
4
.
A
I
Figure 3
STV9425 - STV9425B - STV9426
5/15
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