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February 2005
STW54NK30Z
N-CHANNEL 300V - 0.052
- 54A TO-247
Zener-Protected SuperMESHTM MOSFET
Table 1: General Features
s
TYPICAL R
DS
(on) = 0.052
s
EXTREMELY HIGH dv/dt CAPABILITY
s
100% AVALANCHE TESTED
s
GATE CHARGE MINIMIZED
s
VERY LOW INTRINSIC CAPACITANCES
s
VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESHTM series is obtained through an
extreme optimization of ST's well established
strip-based PowerMESHTM layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmeshTM products.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
DC CHOPPERs
s
IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
Table 2: Order Codes
Figure 1: Package
Figure 2: Internal Schematic Diagram
TYPE
BV
DSS
R
DS(on)
I
D
Pw
STW54NK30Z
300 V
< 0.060
54 A
300 W
TO-247
1
2
3
SALES TYPE
MARKING
PACKAGE
PACKAGING
STW54NK30Z
W54NK30Z
TO-247
TUBE
Rev. 1
STW54NK30Z
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Table 3: Absolute Maximum ratings
( ) Pulse width limited by safe operating area
(1) I
SD
54A, di/dt
200A/s, V
DD
V
(BR)DSS
, T
j
T
JMAX.
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
Table 5: Avalanche Characteristics
Table 6: Gate-Source Zener Diode
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
300
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
300
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C
54
A
I
D
Drain Current (continuous) at T
C
= 100C
34
A
I
DM
( )
Drain Current (pulsed)
200
A
P
TOT
Total Dissipation at T
C
= 25C
300
W
Derating Factor
2.38
W/C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5K
)
6000
V
dv/dt (1)
Peak Diode Recovery voltage slope
4.5
V/ns
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
C
Rthj-case
Thermal Resistance Junction-case Max
0.42
C/W
Rthj-amb
T
l
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering
Purpose
30
300
C/W
C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
54
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
400
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BV
GSO
Gate-Source
Breakdown Voltage
Igs= 1mA (Open Drain)
30
V
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STW54NK30Z
ELECTRICAL CHARACTERISTICS (T
CASE
=25C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Table 8: Dynamic
Table 9: Source Drain Diode
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 1 mA, V
GS
= 0
300
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 C
1
50
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
10
A
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 150 A
3
3.75
4.5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 27 A
0.052
0.060
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
= 15 V
,
I
D
= 27 A
25
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
4960
745
186
pF
pF
pF
C
oss eq.
(3)
Equivalent Output
Capacitance
V
GS
= 0V, V
DS
= 0V to 240 V
550
pF
t
d(on)
t
r
t
d(off)
t
f
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
V
DD
= 150 V, I
D
= 27 A
R
G
= 4.7
V
GS
= 10 V
(Resistive Load see, Figure 3)
40
45
116
35
ns
ns
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 240V, I
D
= 54A,
V
GS
= 10V
158
30
90
221
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
54
200
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 54 A, V
GS
= 0
1.6
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 54 A, di/dt = 100A/s
V
DD
= 100 V, T
j
= 25C
(see test circuit, Figure 5)
328
2.8
17.2
ns
C
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 54 A, di/dt = 100A/s
V
DD
= 100 V, T
j
= 150C
(see test circuit, Figure 5)
416
4.2
20.2
ns
C
A
STW54NK30Z
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Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 5: Transconductance
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 8: Static Drain-source On Resistance
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STW54NK30Z
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 11: Source-Drain Diode Forward Char-
acteristics
Figure 12: Capacitance Variations
Figure 13: Normalized On Resistance vs Tem-
perature
Figure 14: Normalized BVdss vs Temperature
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