Preliminary Data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

March 2006

Rev 1

1/42

STW81101

Multi-band RF frequency synthesizer with integrated VCOs

Feature summary

Integer-N Frequency Synthesizer

Dual differential integrated VCOs with
automatic center frequency calibration:

3300 - 3900 MHz (Direct output)

3800 - 4400 MHz (Direct output)

1650 - 1950 MHz (Internal divider by 2)

1900 - 2200 MHz (Internal divider by 2)

825 - 975 MHz (Internal divider by 4)

950 - 1100 MHz (Internal divider by 4)

Excellent integrated phase noise

Fast lock time: 150µs

Dual modulus programmable prescaler (16/17
or 19/20)

2 programmable counters to achieve a
feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).

Programmable reference frequency divider (10
bits)

Phase frequency comparator and charge pump

Programmable charge pump current

Digital Lock Detector

Dual Digital Bus Interface: SPI and I

C bus with

3 bit programmable address (1100A

)

3.3V Power Supply

Power down mode (HW and SW)

Small size exposed pad VFQFPN28 package
5x5x1.0mm

Process: BICMOS 0.35µm SiGe

Applications

2.5G and 3G Cellular Infrastructure Equipment

CATV Equipment

Instrumentation and Test Equipment

Other Wireless Communication Systems

Description

The STMicroelectronics STW81101 is an
integrated RF synthesizer with voltage controlled
oscillators (VCOs). Showing high performance,
high integration, low power, and multi-band
performances, STW81101 is a low cost one chip
alternative to discrete PLL and VCOs solutions.

STW81101 includes an Integer-N frequency
synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
noise floor of -154dBc/Hz. The combination of
wide frequency range VCOs (thanks to center-
frequency calibration over 32 sub-bands) and
multiple output options (direct output, divided by 2
or divided by 4) allows to cover the 825MHz-
1100MHz, the 1650MHz-2200MHz and the
3300MHz-4400MHz bands.

The STW81101 is designed with
STMicroelectronics advanced 0.35µm SiGe
process.

Order codes

VFQFPN28

Part number

Temp range,

°C

Package

Packing

STW81101AT

-40 to 85

VFQFPN28

Tray

STW81101ATR

-40 to 85

VFQFPN28

Tape & Reel

www.st.com

Contents

STW81101

2/42

Contents

Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5

Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1

Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.1

Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.2

Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.3

Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.4

A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.5

Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.6

Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.7

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.8

Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VCO Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

VCO Frequency Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

VCO Voltage Amplitude Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1

General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.1

Power ON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.2

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.3

START condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.4

STOP condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.5

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STW81101

Contents

3/42

5.1.6

Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.7

Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.8

Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.9

Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2

Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.1

Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3

C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.1

FUNCTIONAL_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.2

B_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.3

A_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.4

REF_DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.5

CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.6

CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3.7

READ-ONLY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4

VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1

General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2

Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3

Bits table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4

VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1

Direct Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2

Divided by 2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3

Divided by 4 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4

Evaluation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

List of tables

STW81101

4/42

List of tables

Table 1.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3.

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4.

Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5.

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6.

Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7.

Current value vs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8.

Voltage level expected on the resonator nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9.

Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 10.

Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11.

Current Byte Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12.

Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13.

Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14.

Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15.

Write-only registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16.

Different functional mode of the FUNCTIONAL_MODE register . . . . . . . . . . . . . . . . . . . . 25

Table 17.

SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18.

Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19.

SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20.

Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21.

Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

STW81101

List of figures

5/42

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

VCO A (Direct output) closed loop phase noise at 3.6GHz with F

STEP

=400KHz

PFD

=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4.

VCO B (Direct output) closed loop phase noise at 4.0GHz with F

STEP

=400KHz

PFD

=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.

VCO A (Div. by 2 output) closed loop phase noise at 1.8GHz with F

STEP

=200KHz

PFD

=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

VCO B (Div. by 2 output) closed loop phase noise at 2.0GHz with F

STEP

=200KHz

PFD

=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

VCO A (Div. by 4 output) closed loop phase noise at 900MHz with F

STEP

=100KHz

PFD

=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8.

VCO B (Div. by 4 output) closed loop phase noise at 1.0GHz with F

STEP

=100KHz

PFD

=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

PFD Frequency Spurs (Div. by 2 Output; F

PFD

=400KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

PFD Frequency Spurs (Div. by 4 Output; F

PFD

=400KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.

Reference Frequency Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.

VCO Divider Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13.

PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.

Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.

VCO Sub-Bands Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16.

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17.

Start and Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18.

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19.

Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20.

Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 21.

Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 22.

SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 23.

SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24.

Differential/single ended output network in the 3.3 - 4.4GHz range
(MATCH_LC_LUMP_4G_DIFF.dsn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 25.

LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 35

Figure 26.

Microstrip line and lumped matching network (MATCH_4G_HYBRID.dsn) . . . . . . . . . . . . 35

Figure 27.

Differential/single ended output network in the 1.65 - 2.2GHz range
(MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 28.

LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 36

Figure 29.

Lumped output matching for divided by 2 output (MATCH_LC_BAL_2G.dsn) . . . . . . . . . 37

Figure 30.

LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . 37

Figure 31.

Lumped output matching for divided by 4 output (MATCH_LC_BAL_1G.dsn) . . . . . . . . . 38

Figure 32.

Application diiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 33.

VFQFPN28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

STW81101

Block diagram and pin configuration

7/42

1.2 Pin

configuration

Figure 2.

Pin connection (top view)

Table 1.

Pin description

Pin No

Name

Description

Observation

VDD_VCOA

VCOA power supply

VDD_DIV2

Divider by 2 power supply

VDD_OUTBUF

Output buffer power supply

OUTBUFP

LO buffer positive output

Open collector

OUTBUFN

LO buffer negative output

Open collector

VDD_DIV4

Divider by 4 power supply

VDD_VCOB

VCOB power supply

VDD_ESD

ESD positive rail power supply

VCTRL

VCO control voltage

ICP

PLL charge pump output

REXT

External resistance connection for
PLL charge pump

VDD_CP

Power supply for charge pump

TEST1

Test input 1

Test purpose only; must
be connected to GND

LOCK_DET

Lock detector

CMOS Output

VFQFPN28

OUTBUFN

VDD_DIV4

VDD_DIV2

VDD_OUTBUF

/
C

VDD_BUFVCO

EXTVCO_INN

VDD_PLL

TEST2

ESD

VDD_VCOB

REF_CLK

VDD_VCOA

DD_

EST

DBUS_SEL

/
LO

OUTBUFP

/
DA

EXTVCO_INP

STW81101

Electrical specifications

9/42

2 Electrical

specifications

2.1

Absolute maximum ratings

2.2 Operating

conditions

2.3 Digital

logic

levels

Table 2.

Absolute maximum ratings

Symbol

Parameter

Values

Unit

Analog Supply voltage

0 to 4.6

Digital Supply voltage

0 to 4.6

stg

Storage temperature

+150

°C

ESD

Electrical Static Discharge

- HBM

(1)

- CDM-JEDEC Standard

- MM

1.5

0.2

The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 1KV.

Table 3.

Operating conditions

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Analog Supply voltage

3.0

3.3

3.6

Digital

Supply

voltage

3.0

3.3

3.6

Current Consumption

100

amb

Operating ambient
temperature

-40

°C

Maximum junction
temperature

125

°C

th j-amb

Junction to ambient package
thermal resistance

Multilayer JEDEC board

°C/W

Table 4.

Digital logic levels

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Low level input voltage

0.2*Vdd

High level input voltage

0.8*Vdd

hyst

Schmitt trigger hysteresis

0.8

Low level output voltage

0.4

High level output voltage

0.85*Vdd

Electrical specifications

STW81101

10/42

2.4 Electrical

characteristics

Table 5.

Electrical characteristics
All the Electrical Specifications are intended at 3.3V supply Voltage.

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

OUTPUT FREQUENCY RANGE

OUTA

Output Frequency Range with
VCOA

Direct Output

3300

3900

MHz

Divider by 2

1650

1950

MHz

Divider by 4

825

975

MHz

OUTB

Output Frequency Range with
VCOB

Direct Output

3800

4400

MHz

Divider by 2

1900

2200

MHz

Divider by 4

950

1100

MHz

VCO DIVIDERS

VCO Divider Ratio

Prescaler 16/17

256

65551

Prescaler 19/20

361

77836

REFERENCE CLOCK and PHASE FREQUENCY DETECTOR

ref

Reference input frequency

200

MHz

Reference input sensitivity

0.35

1.5

Vpeak

Reference Divider Ratio

1023

PFD

PFD input frequency

MHz

step

Frequency step

(1)

Prescaler 16/17

OUT

65551

OUT

256

Prescaler 19/20

OUT

77836

OUT

361

CHARGE PUMP

ICP sink/source

(2)

3bit programmable

OCP

Output voltage compliance
range

0.4

-0.3

Spurious

(3)

Direct Output

-76

dBc

Divider by 2

-82

dBc

Divider by 4

-88

dBc

VCOs

VCOA

VCOA sensitivity

(4)

Sub-Band 00000

105

115

MHz/V

Sub-Band 01111

MHz/V

Sub-Band 11111

MHz/V

VCOB

VCOB sensitivity

(4)

Sub-Band 00000

105

115

MHz/V

Sub-Band 01111

MHz/V

Sub-Band 11111

MHz/V

VCO A Pushing

(4)

MHz/V

VCO B Pushing

(4)

MHz/V

STW81101

Electrical specifications

11/42

2.5

Phase noise specification

CTRL

VCO control voltage

(4)

0.4

LO Harmonic Spurious

(4)

-20

dBc

VCO current consumption

VCO buffer consumption

DIVIDER by 2 consumption

DIVIDER by 4 consumption

LO OUTPUT BUFFER

Output level

dBm

Return Loss

(4)

Matched to 50ohm

Current Consumption

DIV4 Buff

DIV2 Buff

Direct Output

EXTERNAL VCO (Test purpose only)

Frequency range

3.3

4.4

GHz

Input level

dBm

Current Consumption

VCO Internal Buffer

µA

PLL MISCELLANEOUS

Current Consumption

Input Buffer, Prescaler,
Digital Dividers, misc.

Lock up time

(4)

40 KHz PLL bandwidth;
within 1 ppm of
frequency error

150

µs

The frequency step is related to the PFD input frequency as follows:
- f

step

= f

PFD

for Direct Output

- f

step

= f

PFD

/2 for Divided by 2 Output

- f

step

= f

PFD

/4 for Divided by 4 Output

see relationship between ICP and REXT in the Circuit Description section (Charge Pump)

PFD frequency leakage (400KHz) and harmonics

Guaranteed by design and characterization.

Table 5.

Electrical characteristics (continued)
All the Electrical Specifications are intended at 3.3V supply Voltage.

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Table 6.

Phase noise specification

Parameter

Test conditions

Min

Typ

Max

Unit

PHASE NOISE PERFORMANCE

(1)

In Band Phase Noise Floor Closed Loop

(2)

Normalized In Band Phase Noise
Floor

ICP=4mA, PLL BW = 50KHz;

including reference clock
contribution

-220

dBc/Hz

Electrical specifications

STW81101

12/42

In Band Phase Noise Floor

Direct Output

ICP=4mA, PLL BW = 50KHz;

including reference clock
contribution

-220+20log(N)+10log(

PFD

)

dBc/Hz

In Band Phase Noise Floor

Divider by 2

226+20log(N)+10log(

PFD

)

dBc/Hz

In Band Phase Noise Floor

Divider by 4

232+20log(N)+10log(

PFD

)

dBc/Hz

PLL Integrated Phase Noise Direct Output

Integrated Phase Noise

100Hz to 40MHz

OUT

= 4 GHz,

PFD

= 400KHz, f

STEP

=400 KHz,

PLL BW = 35KHz, ICP=4mA

-38

dBc

1.0

° rms

PLL Integrated Phase Noise Divider by 2

Integrated Phase Noise

100Hz to 40MHz

OUT

= 2 GHz,

PFD

= 400KHz, f

STEP

=200 KHz,

PLL BW = 35KHz, ICP=4mA

-44

dBc

0.5

° rms

PLL Integrated Phase Noise Divider by 4

Integrated Phase Noise

100Hz to 40MHz

OUT

= 1 GHz,

PFD

= 400KHz, f

STEP

=100 KHz,

PLL BW = 35KHz, ICP=4mA

-50

dBc

0.25

° rms

VCO A Direct (3300MHz-3900MHz) Open Loop

(3)

Phase Noise @ 1 KHz

-56

dBc/Hz

Phase Noise @ 10 KHz

-83

dBc/Hz

Phase Noise @ 100 KHz

-105

dBc/Hz

Phase Noise @ 1 MHz

-128

dBc/Hz

Phase Noise @ 10 MHz

-148

dBc/Hz

Phase Noise @ 40 MHz

-156

dBc/Hz

VCO B Direct (3800MHz-4400MHz) Open Loop

(3)

Phase Noise @ 1 KHz

-55

dBc/Hz

Phase Noise @ 10 KHz

-82

dBc/Hz

Phase Noise @ 100 KHz

-104

dBc/Hz

Phase Noise @ 1 MHz

-127

dBc/Hz

Phase Noise @ 10 MHz

-147

dBc/Hz

Phase Noise @ 40 MHz

-155

dBc/Hz

VCO A with divider by 2 (1650MHz-1950MHz) Open Loop

(3)

Phase Noise @ 1 KHz

-62

dBc/Hz

Phase Noise @ 10 KHz

-89

dBc/Hz

Phase Noise @ 100 KHz

-111

dBc/Hz

Phase Noise @ 1 MHz

-134

dBc/Hz

Table 6.

Phase noise specification (continued)

Parameter

Test conditions

Min

Typ

Max

Unit

STW81101

Electrical specifications

13/42

Upon request an Evaluation Kit is available including a powerful simulation tool
(STWPLLSim) which allows to estimate very accurately the Phase Noise of the device
according to the desired project parameters (VCO Frequency, Selected Output Stage,
Reference Clock, Frequency Step, ...); refer to the Application Information (

Section 7

) for

more details.

Phase Noise @ 10 MHz

-150

dBc/Hz

Phase Noise @ 20 MHz

-152

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

VCO B with divider by 2 (1900MHz-2200MHz) Open Loop

(3)

Phase Noise @ 1 KHz

-61

dBc/Hz

Phase Noise @ 10 KHz

-88

dBc/Hz

Phase Noise @ 100 KHz

-110

dBc/Hz

Phase Noise @ 1 MHz

-133

dBc/Hz

Phase Noise @ 10 MHz

-150

dBc/Hz

Phase Noise @ 20 MHz

-152

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

VCO A with divider by 4 (825MHz-975MHz) Open Loop

(3)

Phase Noise @ 1 KHz

-68

dBc/Hz

Phase Noise @ 10 KHz

-95

dBc/Hz

Phase Noise @ 100 KHz

-117

dBc/Hz

Phase Noise @ 1 MHz

-139

dBc/Hz

Phase Noise @ 10 MHz

-151

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

VCO B with divider by 4 (950MHz-1100MHz) Open Loop

(3)

Phase Noise @ 1 KHz

-67

dBc/Hz

Phase Noise @ 10 KHz

-94

dBc/Hz

Phase Noise @ 100 KHz

-116

dBc/Hz

Phase Noise @ 1 MHz

-138

dBc/Hz

Phase Noise @ 10 MHz

-151

dBc/Hz

Phase Noise Floor @ 40

MHz

-154

dBc/Hz

Phase Noise SSB.
VCO amplitude setting to value [10].
All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of
-135dBc/Hz @1KHz offset, -145dBc/Hz @10KHz offset and -149.5dBc/Hz of noise floor.

Normalized PN = Measured PN 20log(N) 10log(f

PFD

) where N is the VCO divider ratio (N=B*P+A) and f

PFD

is the

comparison frequency at the PFD input

Typical Phase Noise at centre band frequency

Table 6.

Phase noise specification (continued)

Parameter

Test conditions

Min

Typ

Max

Unit

General description

STW81101

16/42

4 General

description

The block diagram of

Figure 1

shows the different blocks, which have been integrated to

achieve an integer-N PLL frequency synthesizer.

The STW81101 consists of 2 internal low-noise VCOs with buffer blocks, a divider by 2, a
divider by 4, a low-noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit
programmable reference divider, two programmable counters and a programmable dual-
modulus prescaler. The A-counter (5 bits) and B counter (12 bits) counters, in conjunction
with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider,
where N = B*P +A. The division ratio of both reference and VCO dividers is controlled
through the selected digital interface (I

C bus or SPI).

The selection of the digital interface type is done by the proper hardware connection of the
pin DBUS_SEL (0 V for I

C bus, 3.3 V for SPI).

All devices operate with a power supply of 3.3 V and can be powered down when not in use.

4.1 Circuit

description

4.1.1

Reference input stage

The reference input stage is shown in

Figure 11

. The resistor network feeds a DC bias at the

Fref input while the inverter used as the frequency reference buffer is AC coupled.

Figure 11.

Reference Frequency Input Buffer

4.1.2 Reference

divider

The 10-bit programmable reference counter allows the input reference frequency to be
divided to produce the input clock to the PFD. The division ratio is programmed through the
digital interface.

4.1.3 Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it
down to a manageable frequency for the CMOS A and B counters. The modulus (P) is
programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which
division ratio depends on the state of the modulus input.

INV

BUF

VDD

Fref

Power Down

STW81101

General description

17/42

4.1.4

A and B counters

The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17
or 19/20) prescaler make it possible to generate output frequencies which are spaced only
by the reference frequency divided by the reference division ratio. Thus, the division ratio
and the VCO output frequency are given by these formulas:

N = B · P + A

where:

vco

: output frequency of VCO.

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface).

B: division ratio of the main counter.

A: division ratio of the swallow counter.

ref

: input reference frequency.

R: division ratio of reference counter.

N: division ratio of PLL

For a correct work of the VCO divider, B must be strictly higher than A. A can take any value
ranging from 0 to 31. The range of the N number can vary from 256 to 65551 (P=16) or from
361 to 77836 (P=19).

Figure 12.

VCO Divider Diagram

4.1.5

Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output
proportional to the phase error. The PFD includes a delay gate that controls the width of the
anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer
function.

Figure 13

is a simplified schematic of the PFD.

vco

B P

(

) F

ref

------------------------------------------

5 bit

A counter

12 bit

B counter

To PFD

modulus

VCOBUF+

VCOBUF-

Prescaler

16/17 or 19/20

General description

STW81101

18/42

Figure 13.

PFD diagram

4.1.6 Lock

detect

This signal indicates that the difference between rising edges of both UP and DOWN PFD
signals is found to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high
when the PLL is locked. When Power Down is activated, Lock Detect is let to high level
(Lock Detect consumes current only during PLL transients).

4.1.7 Charge

pump

This block drives two matched current sources, Iup and Idown, which are controlled
respectively by UP and DOWN PFD outputs. The nominal value of the output current is
controlled by an external resistor (to be connected to the REXT input pin) and a selection
among 8 by a 3 bit word.

The minimum value of the output current is: I

MIN

= 2*VBG/REXT (VBG~1.17 V)

Note:

The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are
forced to VDD/2

D FF

Fref

VDD

D FF

Fref

VDD

Delay

Down

ABL

Table 7.

Current value vs selection

CPSEL2

CPSEL1

CPSEL0

Current

Value for REXT=4.7 K

MIN

0.5 mA

2*I

MIN

1.0 mA

3*I

MIN

1.5 mA

4*I

MIN

2.0 mA

5*I

MIN

2.5 mA

6*I

MIN

3.0 mA

7*I

MIN

3.5 mA

8*I

MIN

4.0 mA

STW81101

General description

19/42

Figure 14.

Loop filter connection

4.1.8

Voltage controlled oscillators

VCO Selection

Within STW81101 two low-noise VCOs are integrated to cover a wide band from 3300MHz
to 4400MHz (direct output), from 1650MHz to 2200MHz (selecting divider by 2) and from
825MHz to 1100MHz (selecting divider by 4).

VCO A frequency range 3300MHz-3900MHz
VCO B frequency range 3800MHz-4400MHz

VCO Frequency Calibration

Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting
capacitors to the resonator. These frequency ranges are intended to cover the wide band of
operation and compensate for process variation on the VCO center frequency.

An automatic selection of the range is performed when the bit SERCAL rises from "0" to "1".
The charge pump is inhibited and the pins ICP & VCTRL are at VDD/2 volts. Then the
ranges are tested to select the one which with this VCO input voltage is the nearest to the
desired output frequency (Fout = N*Fref/R). When this selection is achieved the signal
ENDCALB (which means End of Calibration) falls to "0", then the charge pump is enabled
again and SERCAL should be reset to "0" before the next channel step. The PLL has just to
perform fine adjustment around VDD/2 on the loop filter to reach Fout, which enables a fast
settle.

Figure 15.

VCO Sub-Bands Frequency Characteristics

Charge

Pump

ICP

VCTRL

BUF

VDD

BUF

Cal bit

General description

STW81101

20/42

The SERCAL bit should be set to "1" at each division ratio change. It should be noted that in
order to reset the autocalibrator State Machine after a power-up, and anyway before the first
calibration, the INITCAL bit should be set to "1" and back to "0" (this operation is
automatically performed by the Power On Reset circuitry). The calibration takes
approximately 7 periods of the PFD Frequency.

The maximum allowed f

PFD

to perform the calibration process is 1 MHz. Using an higher

PFD

the following procedure should be adopted:

Calibrate the VCO at the desired frequency with an f

PFD

less than 1 MHz

Set the A, B and R dividers ratio for the desired f

PFD

VCO Voltage Amplitude Control

The bits A0 and A1 control the voltage swing of the VCO. The following table gives the
voltage level expected on the resonator nodes.

Table 8.

Voltage level expected on the resonator nodes

Code A[1:0]

Differential output

voltage (Vp)

1.1

1.3

1.9

2.1

STW81101

C bus interface

21/42

5 I

C bus interface

The I

C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V.

Data transmission from microprocessor to the STW81101 takes place through the 2 wires
(SDA and SCL) I

C-BUS interface. The STW81101 is always a slave device.

The I

C-bus protocol defines any device that sends data on to the bus as a transmitter and

any device that reads the data as receiver. The device that controls the data transfer is
known as the Master and the others as the slave. The master will always initiate the transfer
and will provide the serial clock for synchronization.

5.1 General

features

5.1.1 Power

reset

The device at Power ON is able to configure itself to a fixed configuration, with all
programmable bits set to factory default setting.

5.1.2 Data

validity

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while
the clock is HIGH are used to identify START or STOP condition.

Figure 16.

Data validity

5.1.3 START

condition

A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the
clock signal SCL is stable in the HIGH state. A Start condition must precede any command
for data transfer.

5.1.4 STOP

condition

A LOW to HIGH transition of the data bus SDA identifies stop while the clock signal SCL is
stable in the HIGH state. A STOP condition terminates communications between the
STW81101 and the Bus Master.

SDA

SCL

CHANGE

DATA

ALLOWED

DATA LINE
STABLE DATA
VALID

SDA

SCL

CHANGE

DATA

ALLOWED

DATA LINE
STABLE DATA
VALID

C bus interface

STW81101

22/42

Figure 17.

Start and Stop condition

5.1.5

Byte format and acknowledge

Every byte transferred on the SDA line must contain bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock
pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits data.

Figure 18.

Byte format and acknowledge

5.1.6 Device

addressing

To start the communication between the Master and the STW81101, the master must
initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB
first) corresponding to the device select address and read or write mode.

The first 7 MSB's are the device address identifier, corresponding to the I

C-Bus definition.

For the STW81101 the address is set as "1100A

", 3bits programmable. The 8th bit

(LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode).

After a START condition the STW81101 identifies on the bus the device address and, if
matched, it will acknowledge the identification on SDA bus during the 9th clock pulse.

5.1.7

Single-byte write mode

Following a START condition the master sends a device select code with the RW bit set to 0.
The STW81101 gives an acknowledge and waits for the internal sub-address (1 byte). This
byte provides access to any of the internal registers.

After the reception of the sub-address internal byte the STW81101 again responds with an
acknowledge. A single-byte write to sub-address 00H will change the
"FUNCTIONAL_MODE" register, so a single-byte write with sub-address 04H will change
the "CONTROL" register and so on.

SDA

SCL

START

STOP

SDA

SCL

START

STOP

SDA

SCL

START

ACKNOWLEDGMENT

FROM RECEIVER

MSB

SDA

SCL

START

ACKNOWLEDGMENT

FROM RECEIVER

MSB

STW81101

C bus interface

23/42

5.1.8

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data
bytes and each one is acknowledged. The master terminates the transfer by generating a
STOP condition.

The sub-address decides the starting byte. A multi-byte with sub-address 01H and 2
DATA_IN bytes will change the "B_COUNTER" and "A_COUNTER" registers (01H,02H), so
a multi-byte with sub-address 00H and and 6 DATA_IN bytes will change all the STW81101
registers.

5.1.9

Current byte address read

In the current byte address read mode, following a START condition, the master sends the
device address with the rw bit set to 1 (No sub-address is needed as there is only 1 byte
read register). The STW81101 acknowledges this and outputs the data byte. The master
does not acknowledge the received byte, but terminates the transfer with a STOP condition.

5.2 Timing

specification

Figure 19.

Data and clock

Table 9.

Single-byte write mode

1100A

ack

sub-address byte

ack

DATA IN

ack

Table 10.

Multi-byte write mode

1100A

ack

sub-address byte

ack DATA IN

ack

....

DATA IN

ack

Table 11.

Current Byte Address Read

1100 A

ack

DATA OUT

No ack

Table 12.

Data and clock

Symbol

Parameter

Minimum time (ns)

Data to clock set up time

Data to clock hold time

cwh

Clock pulse width high

cwl

Clock pulse width low

cwh

cwl

SDA

SCL

cwh

cwl

SDA

SCL

STW81101

C bus interface

25/42

5.3 I

C registers

STW81101 has 6 write-only registers and 1 read-only register.

The following table gives a short description of the write-only registers list.

5.3.1 FUNCTIONAL_MODE

FUNCTIONAL_MODE register is used to select different functional mode for the STW81101
synthesizer according to the following table:

Table 15.

Write-only registers list

HEX CODE

DEC CODE

DESCRIPTION

0x00

FUNCTIONAL_MODE

0x01

B_COUNTER

0x02

A_COUNTER

0x03

REF_DIVIDER

0x04

CONTROL

0x05

CALIBRATION

MSB

LSB

PD6

PD5

PD4

PD3

PD2

PD1

PD0

B11

Table 16.

Different functional mode of the FUNCTIONAL_MODE register

Decimal value

Description

Power down mode

Enable VCO A, output frequency divided by 2

Enable VCO B, output frequency divided by 2

Enable external VCO, output frequency divided by 2

Enable VCO A, output frequency divided by 4

Enable VCO B, output frequency divided by 4

Enable external VCO, output frequency divided by 4

Enable VCO A, direct output

Enable VCO B, direct output

Enable external VCO, direct output

C bus interface

STW81101

26/42

5.3.2 B_COUNTER

B[10:3]. Counter value (bit B11 in the previous register, bits B[2:0] in the next register)

5.3.3 A_COUNTER

Bits B[2:0] for B Counter, A Counter value.

5.3.4 REF_DIVIDER

Reference Clock divider ratio R[9:1] (bits R1, R0 in the next register).

5.3.5 CONTROL

The CONTROL register is used to set the Charge Pump current, the VCO output voltage
amplitude and the Prescaler Modulus.

PLL_A[1:0]: VCO amplitude

CPSEL[2:0]: Charge Pump output current

PSC_SEL: Prescaler Modulus select ('0' for P=16, '1' for P=19)

The LO output frequency is programmed by setting the proper value for A,B and R
according to the following formula:

MSB

LSB

B10

MSB

LSB

MSB

LSB

MSB

LSB

PLL_

SEL2

SEL1

SEL0

PSC_

SEL

OUT

B P

(

)

REF_CLK

----------------------------

STW81101

C bus interface

27/42

and P is the selected Prescaler Modulus

5.3.6 CALIBRATION

This register controls VCO calibrator.

INITCAL: resets the auto-calibrator State Machine (writing to "1" and back to "0")

SERCAL: at "1" starts the VCO auto-calibration (should be reset to "0" at the end of
calibration)

SELEXTCAL: test purpose only; must be set to '0'

CAL[4:0]: test purpose only; must be set to '0'

5.3.7 READ-ONLY

register

This register is automatically addressed in the 'current byte address read mode'.

DEV_ID[1:0]: device identifier bits; returns '00'

LOCK_DET: "1" when PLL is locked

INTCAL[4:0]: internal value of the VCO control word

5.4

VCO calibration procedure

The calibration of the VCO center frequency is activated by a '0' to '1' transition of the
SERCAL bit (CALIBRATION Register bit[6]).

In order to program properly the device, ensuring the VCO calibration, the following
procedure is required before every channel change:

Program all the Registers using a multi-byte write sequence with the desired
settings (Functional Mode, B and A counters, R counter, VCO amplitude, Charge

for Direct Output

where D

equals

0.5

for Output Divided by 2

0.25

for Output Divided by 4

MSB

LSB

INIT

CAL

SER

CAL

SEL

EXT

CAL

CAL4

CAL3

CAL2

CAL1

CAL0

MSB

LSB

DEV_ID1

DEV_ID0

LOCK_

DET

INT

CAL4

INT

CAL3

INT

CAL2

INT

CAL1

INT

CAL0

{

SPI digital interface

STW81101

30/42

6.2 Timing

specification

Figure 23.

SPI Timing specification

Table 17.

SPI data structure (MSB is sent first)

MSB

LSB

Address

Data for Register (24 bits)

A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

Table 18.

Address decoder and outputs

Address

Outputs

DATABITS

D23-D0

Name

Function

ST1

Reference divider, VCO amplitude,
VCO Calibration, Charge Pump
current, Prescaler Modulus

ST2

Functional modes, VCO dividers

ST3

Reserved

ST4

Reserved

Table 19.

SPI Timing specification

Parameter

Description

Min.

Typ.

Max.

Unit

tsetup

DATA to CLOCK setup time

0.8

thold

DATA to clock hold time

0.2

tclk

CLOCK cycle period

tload

LOAD pulse width

tclk_loadr

CLOCK to LOAD rising edge

tclk_loadf

CLOCK to LOAD falling edge

0.5

SPI digital interface

STW81101

32/42

The LO output frequency is programmed by setting the proper value for A,B and R
according to the following formula:

and P is the selected Prescaler Modulus

[23]

PD6

DEVICE FUNCTIONAL MODES

0. Power down

1. Enable VCO A, output frequency divided by 2

2. Enable VCO B, output frequency divided by 2

3. Enable external VCO, output frequency divided by 2

4. Enable VCO A, output frequency divided by 4

5. Enable VCO B, output frequency divided by 4

6. Enable external VCO, output frequency divided by 4

7. Enable VCO A, direct output

8. Enable VCO B, direct output

9. Enable external VCO, direct output

[22]

PD5

[21]

PD4

[20]

PD3

[19]

PD2

[18]

PD1

[17]

PD0

[16]

B11

B Counter Bits

[15]

B10

[14]

[13]

[12]

[11]

[10]

[9]

[8]

[7]

[6]

[5]

[4]

A Counter Bits

[3]

[2]

[1]

[0]

for Direct Output

where D

equals

0.5

for Output Divided by 2

0.25

for Output Divided by 4

Table 20.

Bits (continued)

Serial Interface Address = 00h

Register name = ST1

Bit

Name

Description

OUT

B P

(

)

REF_CLK

----------------------------

{

STW81101

SPI digital interface

33/42

6.4

VCO calibration procedure

The calibration of the VCO center frequency is activated by a '0' to '1' transition of the
SERCAL bit (ST1 Register bit[6]).

In order to program properly the device, ensuring the VCO calibration, the following
procedure is required before every channel change:

Program the ST1 Register with the desired settings (R counter, VCO amplitude,
Charge Pump, Prescaler Modulus) and SERCAL bit set to '0'

Program the ST2 Register with the desired settings (Functional mode, B and A
counters)

Program the ST1 Register with the desired settings (R counter, VCO amplitude,
Charge Pump, Prescaler Modulus) and SERCAL bit set to '1'

The maximum allowed PFD frequency (f

PFD

) to perform the calibration process is 1 MHz; if

the desired f

PFD

is higher than 1MHz the following steps are needed:

Perform all the steps of the calibration procedure programming the desired VCO
frequency with a proper setting of R, B and A counter so that f

PFD

1MHz.

Program the device with the proper setting for the desired VCO and PFD
frequencies according to the above step a) and b) only.

Application information

STW81101

34/42

7 Application

information

The STW81101 features three different alternatively selectable bands: direct output (3.3 to
4.4GHz), divided by 2 (1.65 to 2.2GHz) and divided by 4 (850 to 1100MHz). In order to
achieve a suitable power level, a good matching network is needed to adapt the output
stage to a 50

load. Moreover, since most of commercial RF components have single

ended input and output terminations, a differential to single ended conversion could be
required.

Below different matching configurations for the three bands are suggested as a guideline for
the design of own application board.

The user can find in the Evaluation Kit the ADS Design for each matching configuration
suggested in this section. The name of the corresponding ADS Design is reported below
each figure.

7.1 Direct

Output

If a differential to single conversion is not needed it is possible to match the output buffer of
the STW81101 in the simple way shown in

Figure 24

Figure 24.

Differential/single ended output network in the 3.3 - 4.4GHz range
(MATCH_LC_LUMP_4G_DIFF.dsn)

Since most of discrete components for microwave applications are single ended, the user
can easily use one of the two outputs and terminate the other one to 50

with a 3dB power

loss.

Alternatively it is possible to combine the 2 outputs in different ways. A first topology for the
direct output (3.3GHz to 4.4GHz) is suggested in

Figure 25

. It basically consists of a simple

LC balun and a matching network to adapt the output to a 50

load. The two LC networks

shift output signal phase of -90° and +90° thus combining the 2 outputs. This topology,
designed for a center frequency of 4GHz, is intrinsically narrow band, since the LC balun is
tuned at a single frequency. If the application requires a different sub-band, the LC combiner
could be easily adjusted to be tuned at the frequency of interest.

R F

O U T P

R F

O U T N

C C

2nH

50 O hm

10pF

2nH

10pF

C C

50 O hm

STW81101

Application information

35/42

Figure 25.

LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn)

The 6.8nH shunt inductor works as a DC feed for one of the open collector terminal as well
as a matching element along with the other components. The 1.1nH series inductors are
used to resonate the parasitic capacitance of the chip.

For an optimum output matching it is recommended to use 0402 Murata or AVX capacitors
and 0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection
paths to minimize losses and undesired impedance shift.

An alternative topology, which allows for a more broadband matching and balanced to
unbalanced conversion, is shown it

Figure 26

Figure 26.

Microstrip line and lumped matching network (MATCH_4G_HYBRID.dsn)

Those results have been achieved on an FR4 substrate with a thickness of 350um.

By using this topology the STW81101 is capable to deliver an almost flat power to a 50

load with a return loss grater than 10dB over the whole frequency band (3.3 to 4.4GHz).

For the differential to single conversion the 50 to 100

Johanson balun is recommended

(3700BL15B100).

O UTP

O UTN

1.1nH

3.6nH

0.3pF

6.8nH

0.7pF

50 Ohm

3.6nH

0.3pF

1.1nH

0.7pF

3.5nH

2:1

W=16mil

L=400mil

C=0.7pF

L=1.5nH

VCC

RFOUTP

RFOUTN

50Ohm load

C=8pF

Application information

STW81101

36/42

7.2

Divided by 2 Output

If the user's application does not require a balanced to unbalanced conversion, the output
matching reduces to the simple circuit shown below (

Figure 27

This solution can be easily used to provide one single ended output just terminating the
other output at 50

with a 3dB power loss.

Figure 27.

Differential/single ended output network in the 1.65 - 2.2GHz range
(MATCH_LC_LUMP_2G_DIFF.dsn)

A first solution to combine the differential outputs is the lumped LC type balun tuned in the
2GHz band (

Figure 28

Figure 28.

LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn)

The same recommendation for the SMD components applies also for the divided by 2
output.

Another topology suitable to combine the two outputs for the divided by 2 frequencies is
represented in

Figure 29

OUTP

OUTN

22nH

50 Ohm

10pF

22nH

10pF

50 Ohm

OUTP

OUTN

3nH

5.5nH

1pF

1nH

2.8pF

50 Ohm

2nH

STW81101

Application information

37/42

Figure 29.

Lumped output matching for divided by 2 output
(MATCH_LC_BAL_2G.dsn)

For the differential to single conversion the 50 to 100

Johanson balun (1600BL15B100) is

recommended.

7.3

Divided by 4 Output

The same topology, components values and considerations of

Figure 27

, applies also for the

divided by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn).

As for the previous sections, a solution to combine the differential outputs is the lumped LC
type balun tuned in the 1GHz band (

Figure 30

Figure 30.

LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn)

If the user prefers to use an RF balun it is possible to adopt the same topology depicted in

Figure 29

, just changing the balun and the resistor value (

Figure 31

). The suggested balun

for the 0.8 - 1.1GHz frequency range is the 1:1 Johanson 900BL15C050.

OUTP

OUTN

22nH

50 Ohm

10pF

22nH

10pF

2:1

50 Ohm

OUTP

OUTN

5.5nH

4pF

6pF

50 Ohm

14nH

5.5nH

4pF

25 Ohm

Application information

STW81101

38/42

Figure 31.

Lumped output matching for divided by 4 output
(MATCH_LC_BAL_1G.dsn)

7.4 Evaluation

Kit

Upon request an Evaluation Kit can be delivered. It includes:

Evaluation Board

GUI (Graphical User Interface) to program the device

Measured S parameters of the RF output

ADS2005 schematics providing guidelines for application board design

STWPLLSim software for PLL loop filter design and noise simulation

Three different Evaluation Kits are available, one optimized for 1GHz frequency range, one
for 2GHz frequency range and the last one for 4GHz range.

While ordering please specify the following order codes:

The three Evaluation Kits differ only regarding the output balun and the choke inductors of
the related Evaluation Board; each Evaluation Kit is provided with the needed components
(baluns and inductors) in order to easily adapt the output stage to a different frequency
range.

OUTP

OUTN

22nH

50 Ohm

10pF

22nH

10pF

1:1

25 Ohm

Table 21.

Order code of the evaluation kit

Part Number

Description

STW81101-EVB1G

1GHz frequency range - Divider by 4 output optimized

STW81101-EVB2G

2GHz frequency range - Divider by 2 output optimized

STW81101-EVB4G

4GHz frequency range - Direct output optimized

STW81101

Application diagram

39/42

8 Application

diagram

Figure 32.

Application diiagram

Note:

See Application Information (

Section 7

) for further information on Output Matching topology.

EXT_PD, ADD2, ADD1 (and ADD0 when I

C Bus is selected) can be hard wired directly on

the board.

Loop Filter values are for f

PFD

= 400KHz and I

= 4mA.

ESD

VDD_VCOA

DBUS_SEL

/
C

/
D

DD1

/
L

DD2

DD_

VDD_DIV2

VDD_OUTBUF

OUTBUFP

OUTBUFN

VDD_DIV4

VDD_VCOB

EXT

VDD_BUFVCO

EXTVCO_INP

EXTVCO_INN

VDD_PLL

REF_CLK

TEST2

10µ

22p

10µ

22p

150p

220p

6.8n

10µ

22p

1.8n

STW81101

From/to µ-controller

µ-controller

loop filter

VDD

RF Out

ref clk

VDD

10µ

22p

I2C

SPI

1:2

100

15p

100

15p

4.7K

8.2K

2.2K

Package information

STW81101

40/42

9 Package

information

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: http://www.st.com.

Figure 33.

VFQFPN28 Mechanical Data & Package Dimensions

OUTLINE AND

MECHANICAL DATA

REF.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0.800

0.900

1.000

0.031

0.035

0.039

0.020

0.050

0.0008 0.0019

0.650

1.000

0.025

0.039

0.200

0.0078

0.180

0.250

0.300

0.007 0.0098 0.012

4.850

5.000

5.150

0.191

0.197

0.203

4.750

0.187

2.550

2.700

2.850

0.100

0.106

0.113

4.850

5.000

5.150

0.191

0.197

0.203

4.750

0.187

2.550

2.700

2.850

0.100

0.106

0.113

0.500

0.020

0.350

0.550

0.750

0.014

0.022

0.029

0.60

0.0236

14°

ddd

0.080

0.003

Notes: 1) VFQFPN stands for Thermally Enhanced Very thin Fine

pitch Quad Packages No lead.
Very thin: A = 1.00 Max.

2) The pin #1 identifier must be existed on the top surface

of the package by using indentation mark or other fea-
ture of package body.
Exact shape and size of this feature is optional.

VFQFPN-28 (5x5x1.0mm)

Very Fine Quad Flat Package No lead

7655832 A

STW81101

42/42

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