TDA7326
AM-FM RADIO FREQUENCY SYNTHESIZER
FM INPUT AND PRECOUNTER FOR UP TO
140MHz
AM INPUT FOR UP TO 40MHz
6-BIT SWALLOW COUNTER, 8-BIT PRO-
GRAMMABLE COUNTER FOR FM AND SW
14-BIT PROGRAMMABLE COUNTER FOR
LW AND MW
THREE WIRES 8-BIT SERIAL INTERFACE
ON-CHIP REFERENCE OSCILLATOR AND
COUNTER
PROGRAMMABLE SCANNING STEPS FOR
AM AND FM
DIGITAL PHASE DETECTOR AND LOOP FIL-
TER
TWO SEPARATE FREE PROGRAMMABLE
FILTER APPLICATIONS AVAILABLE
TUNING VOLTAGE OUTPUT 0.5 TO 9.5V
PROGRAMMABLE CURRENT SOURCES TO
SET THE LOOP GAIN
ON-CHIP POWER ON RESET
STANDBY MODE
DESCRIPTION
The TDA7326 is a PLL frequency synthesizer in
CMOS technology that performs all the function of
a PLL radio tuning system for FM and AM (LW,
MW, SW)
July 1994
BLOCK DIAGRAM
ORDERING NUMBERS: TDA7326 (DIP16)
TDA7326D (SO16W)
SO16W
DIP16
1/16
ELECTRICAL CHARACTERISTICS (T
amb
= 25
C ; V
DD1
= 5V; V
DD2
= 9V f
OSC
= 4MHz; R
ISET
= 68K
;
unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
DD1
Supply Voltage
4.5
5.0
5.5
V
V
DD2
Supply Voltage
9.0
10.0
V
I
DD1 FM
Supply Current
no output load, FM mode,
f
in
= 100MHz
10
18
25
mA
I
DD1 AM
Supply Current
no output load, AM mode,
fin = 1MHz
3
5
10
mA
I
DD1 STB
Supply Current
Standby mode
3
20
A
I
DD2
Supply Current
0.5
2
3
mA
V
REF
Voltage at pin 3
3.0
3.5
4.0
V
V
iSET
Voltage at pin 2
RiSET = 68K
7.0
8.0
9.0
V
RF INPUT (AMIN FMIN)
f
iAM
Input Frequency AM
Direct Mode, V
in
= 50mV
0.5
20
MHz
Swallow Mode, V
in
= 50mV
16
40
MHz
f
iFM
Input Frequency FM
Sinus, V
in
= 50mV
30
140
MHz
V
iAM
Input Voltage AM
Direct Mode
0.6 to 16MHz (Sinus)
40
600
mVrms
Swallow Mode
16 to 40MHz (Sinus)
40
600
mVrms
V
iFM
Input Voltage FM
70 to 120MHz (Sinus)
30
600
mVrms
Z
in
Input Impedance FM
fin = 120MHz
200
Z
in
Input Impedance AM
fin = 12MHz
1400
OSCILLATOR
f
OSC
Oscillator Frequency
4
MHz
t
bu
Built Up Time
Euro-Quartz ITT
100
ms
C
in
Internal Capacitance
9
pF
C
OUT
Internal Capacitance
9
pF
Z
in
Input Impedance
4
15
K
V
in
Input Voltage
0.5
V
DD1
Vpp
PLL CHARACTERISTICS
f
step
Step Width AM
1/2.5
KHz
f
step
Step Width FM
12.5/25
KHz
f
ref
Ref Frequency AM
1/2.5
KHz
f
ref
Ref Frequency FM
12.5/25
KHz
LOOP FILTER INPUT (LP
IN1
, LP
IN2
= PIN 15,16)
-I
in
Input Leakage Current
VIN = V
SS
; Phase Detector
Output = Tristate
-1
-0.1
A
I
in
Input Leakage Current
VIN = V
DD
; Phase Detector
Output = Tristate
0.1
+1
A
TDA7326
3/16
ELECTRICAL CHARACTERISTICS (continued)
LOOP FILTER OUTPUT (LP
OUT
= PIN 14)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
v
OL
Output Voltage Low
ILOAD = 0.2mA V
DD2
; = 10V
0.5
0.8
V
V
OH
Output Voltage High
-ILOAD = 0.2mA V
DD2
; = 10V
9
9.5
V
CHARGE PUMP CURRENT GENERATION (LP
IN1
, LP
IN2
= PIN 15, 16)
I
si
Sink Current LPIN1,2
CURR1 = 0, CURR2 = 0
2
5
7
A
CURR1 = 0, CURR2 = 1
120
200
280
A
CURR1 = 1, CURR2 = 1
180
300
420
A
CURR1 = 1, CURR2 = 0
370
500
630
A
-I
so
Source Current LPIN1,2
CURR1 = 0, CURR2 = 0
2
5
7
A
CURR1 = 0, CURR2 = 1
120
200
280
A
CURR1 = 1, CURR2 = 1
180
300
420
A
CURR1 = 1, CURR2 = 0
370
500
630
A
DOUT1 OPENDRAIN OUTPUT(PIN 9)
v
OL
Output Voltage Low
ILOAD = 1mA
0.2
0.5
V
BUS INTERFACE
-I
IL
Input Leakage Current
VIN = V
SS
-1
0.1
1
A
I
IH
Input Leakage Current
VIN = V
SS
-1
0.1
1
A
v
IH
Input Voltage High
Leading edge
3.4
4.0
V
V
IL
Input Voltage Low
Leading edge
1.0
1.6
V
BUS INTERFACE, WAITING TIME (see fig. 5) The Data is Acquired at the High
Low Clock Transition
t
1
CLK Low to DLEN L
H
0.2
s
t
3
DATA Transition to CLK H
L
0.1
s
t
5
CLK H
L to DATA Transition
0.4
s
BUS INTERFACE, DATA REPETITION TIME (see fig. 5)
t
r1
Release Time Between 2 bytes,
except byte 4
5
s
t
r2
Release Time after the
transmission of byte 4
FM mode
180
s
AM mode
2
ms
BUS INTERFACE, SETUP TIME (see fig. 5)
t
2
DLEN High to CLK L
H
0.1
s
BUS INTERFACE, HOLD TIME (see fig. 5)
t
4
DATA Transition to CKL L
H
0
s
t
6
CLK H
L to DLEN H
L
0.4
s
f
CLK
CLK Frequency
500
KHz
Duty Cycle
50
%
t
pl
Clock Pulse Low
1
s
t
ph
Clock Pulse High
1
s
TDA7326
4/16
2.0 GENERAL DESCRIPTION
This circuit contains a frequency synthesizer and
a loop filter for an FM and AM radio tuning sys-
tem. Only a V
CO
is required to build a complete
PLL system.
For FM and SW application, the counter works in
a two stages configuration.
The first stage is a swallow counter with a four
modulus (:32/33/64/65) precounter.
The second stage is an 8-bit programmable
counter.
For LW and MW application, a 14-bit programma-
ble counter is available.
The circuit receives the scaling factors for the pro-
grammable counters and the values of the refer-
ence frequencies via a three line serial bus inter-
face.
The reference frequency is generated by a 4MHz
XTAL oscillator followed by the reference divider.
An external oscillator (f = 4MHz) can be used in-
stead of the internal one; it must be connected to
OSCIN (pin 7).
The reference step-frequency is 1 or 2.5kHz for
AM. For FM mode a step frequency of 12.5 and
25kHz can be selected.
The circuit checks the format of the received data
words.
Valid data in the interface shift register are stored
automatically in buffer registers at the end of
transmission.
The output signals of the phase detector are
switching the programmable current sources.
Their currents are integrated in the loop filter to a
DC voltage.The values of the current sources are
programmable by two bits also received via the
serial bus.
The loop filter amplifier is supplied by a separate
positive power supply, to minimize the noise in-
duced by the digital part of the system.
The loop gain can be set for different conditions.
After a power on reset, all registers are reset to
zero and the standby mode is activated.
In standby mode, oscillator, reference counter,
AM input and FM input are stopped. The power
consumption is reduced to a minimum.
3.0 DETAILED DESCRIPTION OF THE PLL
FREQUENCY SYNTHESIZER
3.1 INPUT AMPLIFIERS
The signals applied on AM and FM input are am-
plified to get a logic level in order to drive the fre-
quency dividers.
3.1.1 Input Impedance
The typical input impedance: for the FM input
is 200
and for AM input is 1.4k
.
3.1.2 Input sensitivity
(see Figures 1a and 1b).
3.2 DATA AND CONTROL REGISTER
3.2.1 Register Location
The data registers (bit2...bit7) for the control
register and the data registers PC7...PC0,
SC5...SC0 for the counters are organized in
four words, identified by two address bits (bit 7
and bit 6), bit 7 is the first bit to be sent by the
controller, bit0 is the last one. The order and
the number of the bytes to be transmitted is
free of choice. The modification of the
PC7...PC0 registers is valid for the internal
counters only after transmission of byte 4
(SC5...SC0).
ADDRESS BITS
DATA BITS
BYTE
MSB-BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB BIT 0
Function
adr 0
adr 1
data 0
data 1
data 2
data 3
data 4
data 5
byte 1
0
0
test 0
test 1
test 2
SOUT
CURR2
f
REF
byte 2
0
1
PC7
PC6
LPF1/2
CURR 1
SWM/DIR
AM/FM
byte 3
1
0
PC5
PC4
PC3
PC2
PC1
PC0
byte 4
1
1
SC5
SC4
SC3
SC2
SC1
SC0
3.2.2 CONTROL AND STATUS REGISTERS
Register Configuration
REGISTER NAME
FUNCTION
SWM/DIR
Swallow direct-mode switch 1 = SWM, 0 = DIR
AM/FM
AM - FM band switch 1=AM, 0 = FM
f
REF
Selection of reference frequency (see table 3.4)
CURR1
Current select of change pump
CURR2
Current select of change pump
LPF1/LPF2
Loop filter input select 1= I
PF1
, 0 = I
PF2
SOUT
Switch output condition 1=output high, 0 = output low
TDA7326
5/16
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