TDA737
7
2 x 3
0
W DUAL/QUAD POWER AMPLIFIER FOR CAR RADIO
HIGH OUTPUT POWER CAPABILITY:
2 x
35
W max./4
2 x 3
0
W/4
EIAJ
2 x 3
0
W/4
EIAJ
2
x
2
0
W/4
@14.4V, 1KHz, 10%
4
x
6
W/4
@14.4V, 1KHz, 10%
4
x
1
0
W/2
@14.4V, 1KHz, 10%
MINIMUM
EXTERNAL
COMPONENTS
COUNT:
NO BOOTSTRAP CAPACITORS
NO BOUCHEROT CELLS
INTERNALLY FIXED GAIN (26dB BTL)
ST-BY FUNCTION (CMOS COMPATIBLE)
NOAUDIBLE POPDURING ST-BYOPERATIONS
DIAGNOSTICS FACILITY FOR:
CLIPPING
OUT TO GND SHORT
OUT TO V
S
SHORT
SOFT SHORT AT TURN-ON
THERMAL SHUTDOWN PROXIMITY
Protections:
OUPUT AC/DC SHORT CIRCUIT
TO GND
TO V
S
ACROSS THE LOAD
SOFT SHORT AT TURN-ON
OVERRATING CHIP TEMPERATURE WITH
SOFT THERMAL LIMITER
LOAD DUMP VOLTAGE SURGE
VERY INDUCTIVE LOADS
FORTUITOUS OPEN GND
REVERSED BATTERY
ESD
September 1998
BLOCK DIAGRAM
MULTIWATT15V
MULTIWATT15H
ORDERING NUMBERS:
TDA737
7
V
TDA737
7
H
DIAGNOSTICS
1/1
0
DESCRIPTION
The TDA737
7
is a new technology class AB car
radio amplifier able to work either in DUAL
BRIDGE or QUAD SINGLE ENDED configuration.
The exclusive fully complementary structure of the
output stage and the internally fixed gain guaran-
tees the highest possible power performances
with extremely reduced component count. The
on-board clip detector simplifies gain compression
operation. The fault diagnostics makes it possible
to detect mistakes during car radio set assembly
and wiring in the car.
GENERAL STRUCTURE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
op
Operating Supply Voltage
18
V
V
S
DC Supply Voltage
28
V
V
peak
Peak Supply Voltage (for t = 50ms)
50
V
I
O
Output Peak Current (not repetitive t = 100
s)
4.5
A
I
O
Output Peak Current (repetitive f > 10Hz)
3.5
A
P
tot
Power Dissipation (T
case
= 85
C)
36
W
T
stg
, T
j
Storage and Junction Temperature
-40 to 150
C
THERMAL DATA
Symbol
Description
Value
Unit
R
th j-case
Thermal Resistance Junction-case
Max
1.8
C/W
PIN CONNECTION (Top view)
DIAGNOSTICS
TDA737
7
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0
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, V
S
= 14.4V; R
L
= 4
; f = 1KHz;
T
amb
= 25
C, unless otherwise specified
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S
Supply Voltage Range
8
18
V
I
d
Total Quiescent Drain Current
R
L
=
150
mA
V
OS
Output Offset Voltage
150
mV
P
O
Output Power
THD = 10%; R
L
= 4
Bridge
Single Ended
Single Ended, R
L
= 2
18
5
.5
2
0
6
1
0
W
W
W
P
O max
Max. Output Power (***)
VS = 14.4V, Bridge
3
1 35
W
P
O EIAJ
EIAJ Output Power (***)
V
S
= 13.7V, Bridge
27
3
0
W
THD
Distortion
R
L
= 4
Single Ended, P
O
= 0.1 to 4W
Bridge, P
O
= 0.1 to 10W
0.02
0.03
0.3
%
%
CT
Cross Talk
f = 1KHz Single Ended
f = 10KHz Single Ended
70
60
dB
dB
f = 1KHz Bridge
f = 10KHz Bridge
55
60
dB
dB
R
IN
Input Impedance
Single Ended
Bridge
20
10
30
15
K
K
G
V
Voltage Gain
Single Ended
Bridge
19
25
20
26
21
27
dB
dB
G
V
Voltage Gain Match
0.5
dB
E
IN
Input Noise Voltage
R
g
= 0; "A" weighted, S.E.
Non Inverting Channels
Inverting Channels
2
5
V
V
Bridge
Rg = 0; 22Hz to 22KHz
3.5
V
SVR
Supply Voltage Rejection
R
g
= 0; f = 300Hz
50
dB
A
SB
Stand-by Attenuation
P
O
= 1W
80
90
dB
I
SB
ST-BY Current Consumption
V
ST-BY
= 0 to 1.5V
100
A
V
SB
ST-BY In Threshold Voltage
1.5
V
V
SB
ST-BY Out Threshold Voltage
3.5
V
I
pin7
ST-BY Pin Current
Play Mode V
pin7
= 5V
50
A
Max Driving Current Under
Fault (*)
5
mA
I
cd off
Clipping Detector
Output Average Current
d = 1% (**)
90
A
I
cd on
Clipping Detector
Output Average Current
d = 5% (**)
160
A
V
sat pin10
Voltage Saturation on pin 10
Sink Current at Pin 10 = 1mA
0.7
V
(*) See built-in S/C protection description
(**) Pin 10 Pulled-up to 5V with 10K
; R
L
= 4
(***) Saturated square wave output.
TDA737
7
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C1 0.22
F
1
DIAGNOSTICS
4
7
C10 2200
F
D94AU063A
C7
10
F
10K R1
ST-BY
IN FL
C2 0.22
F
IN FR
5
C4 0.22
F
12
IN RL
C3 0.22
F
IN RR
11
C8 47
F
6
13
C5
1000
F
C6
100nF
3
VS
C9 2200
F
2
15
C11 2200
F
C12 2200
F
14
OUT FL
OUT FR
OUT RL
OUT RR
8
9
10
STANDARD TEST AND APPLICATION CIRCUIT
Figure 1: Quad Stereo
C1 0.47
F
1
DIAGNOSTICS
4
7
D94AU064A
C5
10
F
10K R1
ST-BY
IN L
C2 0.47
F
5
12
IN R
11
C8 47
F
6
13
C3
1000
F
C4
100nF
3
VS
2
15
14
OUT L
8
9
10
OUT R
Figure 2: Double Bridge
0.22
F
1
DIAGNOSTICS
4
7
D94AU065A
10
F
10K
ST-BY
IN L
0.47
F
5
IN BRIDGE
12
47
F
6
13
1000
F
100nF
3
VS
2
15
14
OUT L
8
9
10
OUT
BRIDGE
11
0.22
F
IN L
OUT R
2200
F
2200
F
Figure 3: Stereo/Bridge
Note:
C9, C10, C11, C12 could be
reduced if the 2
operation is not
required.
TDA737
7
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High Application Flexibility
The availability of 4 independent channels makes
it possible to accomplish several kinds of applica-
tions ranging from 4 speakers stereo (F/R) to 2
speakers bridge solutions.
In case of working in single ended conditions the
polarity of the speakers driven by the inverting
amplifier must be reversed respect to those driven
by non inverting channels.
This is to avoid phase inconveniences causing
sound alterations especially during the reproduc-
tion of low frequencies.
Easy Single Ended to Bridge Transition
The change from single ended to bridge configu-
rations is made simply by means of a short circuit
across the inputs, that is no need of further exter-
nal components.
Gain Internally Fixed to 20dB in Single Ended,
26dB in Bridge
Advantages of this design choice are in terms of:
components and space saving
output noise, supply voltage rejection and dis-
tortion optimization.
Silent Turn On/Off and Muting/Stand-by Func-
tion
The stand-by can be easily activated by means of
a CMOS level applied to pin 7 through a RC filter.
Under stand-by condition the device is turned off
completely (supply current = 1
A typ.; output at-
tenuation= 80dB min.).
Every ON/OFF operation is virtually pop free.
Furthemore, at turn-on the device stays in muting
condition for a time determined by the value as-
signed to the SVR capacitor.
While in muting the device outputs becomes in-
sensitive to any kinds of signal that may be pre-
sent at the input terminals. In other words every
transient coming from previous stages produces
no unplesant acoustic effect to the speakers.
STAND-BY DRIVING (pin 7)
Some precautions have to be taken in the defini-
tion of stand-by driving networks: pin 7 cannot be
directly driven by a voltage source whose current
capability is higher than 5mA. In practical cases
a series resistance has always to be inserted,
having it the double purpose of limiting the cur-
rent at pin 7 and to smooth down the stand-by
ON/OFF transitions - in combination with a ca-
pacitor - for output pop prevention.
In any case, a capacitor of at least 100nF from
pin 7 to S-GND, with no resistance in between, is
necessary to ensure correct turn-on.
OUTPUT STAGE
The fully complementary output stage was made
possible by the development of a new compo-
nent: the ST exclusive power ICV PNP.
A novel design based upon the connection shown
in fig. 20 has then allowed the full exploitation of
its possibilities.
The clear advantages this new approach has over
classical output stages are as follows:
Rail-to-Rail Output Voltage Swing With No
Need of Bootstrap Capacitors.
The output swing is limited only by the VCEsat
of the output transistors, which is in the range
of 0.3
(R
sat
) each.
Classical solutions adopting composite PNP-
NPN for the upper output stage have higher
saturation loss on the top side of the waveform.
This unbalanced saturation causes a signifi-
cant power reduction. The only way to recover
power consists of the addition of expensive
bootstrap capacitors.
Absolute Stability Without Any External
Compensation.
Referring to the circuit of fig. 20 the gain
V
Out
/V
In
is greater than unity, approximately 1+
R2/R1. The DC output (V
CC
/2) is fixed by an
auxiliary amplifier common to all the channels.
By controlling the amount of this local feedback it
is possible to force the loop gain (A*
) to less
than unity at frequency for which the phase shift
is 180
. This means that the output buffer is in-
trinsically stable and not prone to oscillation.
Most remarkably, the above feature has been
achieved in spite of the very low closed loop
gain of the amplifier.
In contrast, with the classical PNP-NPN stage,
the solution adopted for reducing the gain at
high frequencies makes use of external RC
networks, namely the Boucherot cells.
BUILTIN SHORT CIRCUIT PROTECTION
Figure 20: The New Output Stage
TDA737
7
5
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