TDA7449
TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- 2 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE, AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7449 is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in TV systems.
Selectable input gain is provided. Control of all
the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
May 2003
0/30dB
2dB STEP
MUXOUTL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
BASS
BASS
MUXOUTR
TREBLE(R)
SPKR ATT
LEFT
LOUT
SCL
SDA
DIG_GND
ROUT
D98AU847A
I
2
CBUS DECODER + LATCHES
100K
100K
G
L-IN1
L-IN2
100K
100K
R-IN1
R-IN2
G
INPUT MULTIPLEXER
+ GAIN
BOUT(L)
SPKR ATT
RIGHT
BIN(R) BOUT(R)
SUPPLY
CREF
AGND
V
S
BIN(L)
5
8
9
7
6
19
20
18
4
2
3
11
17
12
13
1
10
16
15
14
R
B
R
B
V
REF
BLOCK DIAGRAM
ORDERING NUMBERS:
TDA7449 TDA7449D
DIP20
SO20
1/18
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
-10 to 85
C
T
stg
Storage Temperature Range
-55 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-pin
Thermal Resistance Junction-pins
85
C/W
CREF
V
S
PGND
ROUT
LOUT
R_IN1
R_IN2
L_IN1
L_IN2
1
3
2
4
5
6
7
8
9
BIN(R)
BOUT(R)
BOUT(L)
TREBLE(L)
BIN(L)
TREBLE(R)
DIG_GND
SCL
SDA
20
19
18
17
16
14
15
13
12
D98AU848
MUXOUT(L)
10
MUXOUT(R)
11
PIN CONNECTION
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10.2
V
V
CL
Max. input signal handling
2
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.1
%
S/N
Signal to Noise Ratio V
out
= 1Vrms (mode = OFF)
106
dB
S
C
Channel Separation f = 1KHz
90
dB
Input Gain in (2dB step)
0
30
dB
Volume Control (1dB step)
-47
0
dB
Treble Control (2dB step)
-14
+14
dB
Bass Control (2dB step)
-14
+14
dB
Balance Control 1dB step
-79
0
dB
Mute Attenuation
100
dB
TDA7449
2/18
ELECTRICAL CHARACTERISTICS (refer to the test circuit T
amb
= 25C, V
S
= 9V, R
L
= 10K
,
R
G
= 600
, all controls flat (G = 0dB), unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
V
S
Supply Voltage
6
9
10.2
V
I
S
Supply Current
7
mA
SVR
Ripple Rejection
60
90
dB
INPUT STAGE
R
IN
Input Resistance
100
K
V
CL
Clipping Level
THD = 0.3%
2
2.5
Vrms
S
IN
Input Separation
The selected input is grounded
through a 2.2
capacitor
80
100
dB
G
inmin
Minimum Input Gain
-1
0
1
dB
G
inman
Maximum Input Gain
30
dB
G
step
Step Resolution
2
dB
VOLUME CONTROL
C
RANGE
Control Range
45
47
49
dB
A
VMAX
Max. Attenuation
45
47
49
dB
A
STEP
Step Resolution
0.5
1
1.5
dB
E
A
Attenuation Set Error
A
V
= 0 to -24dB
-1.0
0
1.0
dB
A
V
= -24 to -47dB
-1.5
0
1.5
dB
E
T
Tracking Error
A
V
= 0 to -24dB
0
1
dB
A
V
= -24 to -47dB
0
2
dB
V
DC
DC Step
adjacent attenuation steps
from 0dB to A
V
max
0
0.5
3
mV
mV
A
mute
Mute Attenuation
80
100
dB
BASS CONTROL (1)
Gb
Control Range
Max. Boost/cut
+12.0
+14.0
+16.0
dB
B
STEP
Step Resolution
1
2
3
dB
R
B
Internal Feedback Resistance
18.75
25
31.25
K
TREBLE CONTROL (1)
Gt
Control Range
Max. Boost/cut
+13.0
+14.0
+15.0
dB
T
STEP
Step Resolution
1
2
3
dB
SPEAKER ATTENUATORS
C
RANGE
Control Range
76
dB
S
STEP
Step Resolution
0.5
1
1.5
dB
E
A
Attenuation Set Error
A
V
= 0 to -20dB
-1.5
0
1.5
dB
A
V
= -20 to -56dB
-2
0
2
dB
V
DC
DC Step
adjacent attenuation steps
0
3
mV
A
mute
Mute Attenuation
80
100
dB
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does't reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
TDA7449
3/18
ELECTRICAL CHARACTERISTICS (continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AUDIO OUTPUTS
V
CLIP
Clipping Level
d = 0.3%
2.1
2.6
V
RMS
R
L
Output Load Resistance
2
K
R
O
Output Impedance
10
40
70
V
DC
DC Voltage Level
3.8
V
GENERAL
E
NO
Output Noise
All gains = 0dB;
BW = 20Hz to 20KHz flat
5
15
V
E
t
Total Tracking Error
A
V
= 0 to -24dB
0
1
dB
A
V
= -24 to -47dB
0
2
dB
S/N
Signal to Noise Ratio
All gains 0dB; V
O
= 1V
RMS
;
106
dB
S
C
Channel Separation Left/Right
80
100
dB
d
Distortion
A
V
= 0; V
I
= 1V
RMS
;
0.01
0.08
%
BUS INPUT
V
IL
Input Low Voltage
1
V
V
IH
Input High Voltage
3
V
I
IN
Input Current
V
IN
= 0.4V
-5
5
A
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
0.8
V
TDA7449
4/18
0/30dB
2dB STEP
MUXOUTL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
BASS
BASS
MUXOUTR
TREBLE(R)
SPKR ATT
LEFT
LOUT
SCL
SDA
DIG_GND
ROUT
D98AU849A
I
2
CBUS DECODER + LATCHES
100K
100K
G
L-IN1
L-IN2
100K
100K
R-IN2
R-IN1
G
INPUT MULTIPLEXER
+ GAIN
BOUT(L)
SPKR ATT
RIGHT
BIN(R)
BOUT(R)
SUPPLY
CREF
AGND
V
S
BIN(L)
5
8
9
6
7
19
20
18
4
2
3
11
17
12
13
1
10
16
15
14
R
B
R
B
V
REF
C9
5.6nF
150nF
330nF
R2 2K
C10
5.6nF
150nF
330nF
R1
C3 0.47
F
C4 0.47
F
C1 0.47
F
C2 0.47
F
C11
10
F
1
2
3
4
5
RCA
J3
J4
CON3
IN2L
IN1L
GND
GND
GND
IN1L
RCA
J2
J1
CON
IN1R
IN2R
GND
GND
IN1R
1
2
3
4
1
2
3
4
MOUTR
GND
MOUTL
J5
J5
CON4
GND
C5
C6
2K
C8
C7
1
2
3
4
J6
CON4
R3 30
JP1
JUMPER
+9 V
1
2
3
4
J10
CON4
J8
J9
OUT_ R
OUT_L
OUT_R
OUT_L
1
2
+9V
J7
CON2
C13
100nF
C12
22
F
+V8
GND
TEST CIRCUIT
P.C.Board (Referred to DIP20 package only)
TDA7449
5/18
APPLICATION SUGGESTIONS
The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7449 audioprocessor provides 2 bands
tones control.
Bass, Stages
The Bass cell has an internal resistor Ri = 25K
typical.
Several filter types can be implemented, connect-
ing external components to the Bass IN and OUT
pins.
The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in-
ternal and R2,C1,C2 external) the centre fre-
quency Fc, the gain Av at max. boost and the fil-
ter Q factor are computed as follows:
F
C
=
1
2
Ri, R2, C1, C2
A
V
=
R2 C2
+
R2 C1
+
Ri C1
R2 C1
+
R2 C2
Q
=
Ri R2
+
C1 C2
R2 C1
+
R2 C2
Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:
C1
=
A
V
-
1
2
R
i
Q
C2
=
Q
2
C1
(
A
V
-
1
)
Q
2
R2
=
A
V
-
1
-
Q
2
2
C1
F
C
(
A
V
-
1
)
Q
Treble Stage
The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25K
typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
CREF
The suggested 10
F reference capacitor (CREF)
value can be reduced to 4.7
F if the application
requires faster power ON.
Ri internal
C
2
OUT
IN
C
1
R
2
D95AU313
Figure 1.
Figure 2: THD vs. frequency
Figure 3: THD vs. R
LOAD
TDA7449
6/18
Figure 4: Channel separation vs. frequency
Figure 6: Treble response
Figure 5: Bass response
R
i
= 25k
C1 = 150nF
C2 = 330nF
R2 = 2k
TDA7449
7/18
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7449 and vice versa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audio processor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audio processor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio
processor, the
P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I
2
CBUS
Figure 4: Timing Diagram of I
2
CBUS
Figure 5: Acknowledge on the I
2
CBUS
TDA7449
8/18
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7449
address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
S
1
0
0
0
1
0
0
0
ACK
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D96AU420
X
DATA
SUBADDRESS
DATA 1 to DATA n
X
X
B
EXAMPLES
No Incremental Bus
The TDA7449 receives a start condition, the cor-
rect chip address, a subaddress with the B = 0
(no incremental bus), N-data (all these data con-
cern the subaddress selected), a stop condition.
S
1
0
0
0
1
0
0
0
ACK
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D96AU421
X
D3
SUBADDRESS
DATA
X
X
0
D2 D1 D0
Incremental Bus
The TDA7449 receive a start conditions, the cor-
rect chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "XXX1000" to "XXX1111" of
DATA are ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
S
1
0
0
0
1
0
0
0
ACK
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D96AU422
X
D3
SUBADDRESS
DATA 1 to DATA n
X
X
1
D2 D1 D0
TDA7449
9/18
POWER ON RESET CONDITION
INPUT SELECTION
IN2
INPUT GAIN
28dB
VOLUME
MUTE
BASS
2dB
TREBLE
2dB
SPEAKER
MUTE
DATA BYTES
Address = 88 HEX (ADDR:OPEN).
FUNCTION SELECTION: First byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
INPUT SELECT
X
X
X
B
0
0
0
1
INPUT GAIN
X
X
X
B
0
0
1
0
VOLUME
X
X
X
B
0
0
1
1
NOT ALLOWED
X
X
X
B
0
1
0
0
BASS
X
X
X
B
0
1
0
1
TREBLE
X
X
X
B
0
1
1
0
SPEAKER ATTENUATE "R"
X
X
X
B
0
1
1
1
SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON'T CARE
INPUT SELECTION
MSB
LSB
INPUT MULTIPLEXER
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
0
NOT ALLOWED
X
X
X
X
X
X
0
1
NOT ALLOWED
X
X
X
X
X
X
1
0
IN2
X
X
X
X
X
X
1
1
IN1
TDA7449
10/18
DATA BYTES (continued)
INPUT GAIN SELECTION
MSB
LSB
INPUT GAIN
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
0dB
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
20dB
1
0
1
1
22dB
1
1
0
0
24dB
1
1
0
1
26dB
1
1
1
0
28dB
1
1
1
1
30dB
GAIN = 0 to 30dB
VOLUME SELECTION
MSB
LSB
VOLUME
D7
D6
D5
D4
D3
D2
D1
D0
1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
X
1
1
1
X
X
X
MUTE
VOLUME = 0 to 47dB/MUTE
TDA7449
11/18
DATA BYTES (continued)
BASS SELECTION
MSB
LSB
BASS
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
TREBLE SELECTION
MSB
LSB
TREBLE
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
TDA7449
12/18
DATA BYTES (continued)
SPEAKER ATTENUATE SELECTION
MSB
LSB
SPEAKER ATTENUATION
D7
D6
D5
D4
D3
D2
D1
D0
1dB
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
1
1
1
X
X
X
MUTE
SPEAKER ATTENUATION = 0 to -79dB/MUTE
20K
20K
CREF
V
S
D96AU430
V
S
PIN: 1
V
S
D96AU434
20
A
ROUT
24
LOUT
PINS: 4, 5
TDA7449
13/18
V
S
D96AU491
20
A
V
S
MUXOUT
GND
PINS: 10,11
20
A
V
S
100K
V
REF
D96AU425
IN
PINS: 6,7,8,9
44K
V
S
BOUT(R)
D96AU429
20
A
BOUT(L)
PINS: 13, 14
25K
V
S
BIN(R)
D98AU850
20
A
BIN(L)
PINS: 12, 15
50K
V
S
TREBLE(R)
D96AU433
20
A
TREBLE(L)
PINS: 16, 17
D96AU424
20
A
SCL
PIN: 19
TDA7449
14/18
D96AU423
20
A
SDA
PIN: 20
TDA7449
15/18
DIP20
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.254
0.010
B
1.39
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
3.3
0.130
Z
1.34
0.053
OUTLINE AND
MECHANICAL DATA
TDA7449
16/18
1
1
0
11
20
A
e
B
D
E
L
K
H
A1
C
SO20MEC
h x 45
SO20
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0 (min.)8 (max.)
OUTLINE AND
MECHANICAL DATA
TDA7449
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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TDA7449
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