FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
AM/FM PROCESSING
AUDIO-PROCESSING AND SOUND-PROC-
ESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE SAI
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
MULTIFUNCTION GENERAL PURPOSE I/O PORTS
DESCRIPTION
The TDA7500 is an integrated circuit implement-
ing a fully digital, integrated and advanced solu-
tion to perform the signal processing in front of
the power amplifier and behind the AM/FM tuner
or any other audio sources. The chip integrates
two 43 MIPs DSP cores: one for stereo decoding,
noise blanking, weak signal processing and multi-
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
September 1999
dig. aud. in
8+3
DSP1
X Register
Ram 512
Y Register
Ram 512
Program
Ram 1024
Rom 256
4
DSP0
Grp & blk
sync., error
correction
4
4
RDS
2
DSP Orpheus Core
FM processing,
AM processing,
Traffic mem., Dolby,
X bus 0
X bus 1
Exchange
Interface
Ext. Memory
Interface
IIC / SPI
Program
Ram 5632
Rom 256
Y Register
Ram 512
X Register
8.55MHz
CLK in
Int
Reset
5
VDD
GND
5
uP control
RDS
128k (4M) x 8
DSP Orpheus Core
Audio processing,
Sound processing
XTAL Osc.,
PLL
RDS
Filter
Debug, Test Interface
SPI
Serial Audio
Interface
4
dig. aud. out
Mux
Audio Bus 6 ch.
Audio Bus Synch.
Main micro
Error corrected RDS blocks
alternatively:
RDS clk, dat, qual, ARI
SPDIF
Interface
Sample Rate
Converter
Demod.
Modulator
Modulator
SC Filter
SC Filter
SC Filter
SC Filter
SC Filter
SC Filter
Noise
Shaper
Noise
Shaper
Noise
Shaper
Oversampling
Filter
Oversampling
Filter
Oversampling
Filter
Modulator
Modulator
Decimation
Filter
Decimation
Filter
Voltage
Ref.
Codec
Ctl Reg.
Test I/F
6
signal/line out
6
supply
2
3
clkt, wst, clkr, wsr
Input Multiplexer,
Analog Level Adjust
analog audio in
2
3
4
2
3
1
CC
CD
tel,navi
AM/FM lev.
AM/FM mpx
RDS mpx
AM-IF
1
Analog Volume Control,
Line Driver
IIC
3
AM
Noise
Detector
VDD GND
3
2
2
CDC input
4
4
SPI
Display uP
Spectrum Analyser
Debug, Test Interface
(3 I/O's)
4
(3 I/O's)
RDS bit/blk Int.
Mute
Cref
MD input
1 stereo channel
2
CODEC-ref
VS
SigGnd RefOut
Output
select.
(4 I/O's)
(1 I/O)
(2 I/O's)
(4 I/O's)
2 channel analog bypass
Ram 512
including 12 GPIO s
including 12 GPIO s
Speech synth., etc...
DAC-ref
Test
CD input
17
Data, ctl
Address
(4 I/O's)
(2 I/O's)
(1 I/O)
BLOCK DIAGRAM
TQFP100 Power with Slug Down
TDA7500
DIGITAL AM/FM SIGNAL PROCESSOR
PRODUCT PREVIEW
1/14
path detection and one for sound processing. An
I2C/SPI interface is implemented for control and
communication with the main micro.
A separate SPI is available to interface the dis-
play micro.
The DSP cores are integrated with their associ-
ated data and program memories. The peripher-
als and interfaces I
2
C, SPI, Serial Audio Interface
(SAI), PLL Oscillator, External Memory Interface,
(EMI), General Purpose I/O register (Port A) and
the D/A registers are connected to and controlled
by DSP0, whereas the A/D registers, the SPDIF
and the General Purpose I/O register (Port B) are
connected to and controlled by DSP1. The Debug
and Test Interface are connected to both DSP
cores.
The TDA7500 is supposed to be used in kit with
the TDA7501 or any other device of the same
family. Thanks to the serial audio interface also
digital sources can be processed and a direct
output to a digital bus is also available.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TESTEN
TESTSE
NRESET
SCKM
MOSIM
MISOM
SSM
SCKD
MOSID
MISOD
SSD
AVDD
XTI
XTO
CLKIN
AGND
RDSINT
RDSARI_SCLK
RDSDAT_SI
RDSQAL_SO
RDSCLK_SS
INT
SRCCD
SRCMD
GND1
V
DD1
CG
N
D
1
DS
RA
<
7
>
DS
RA
<
6
>
DS
RA
<
5
>
DS
RA
<
4
>
DS
RA
<
3
>
DS
RA
<
2
>
DS
RA
<
1
>
DS
RA
<
0
>
SR
A
<
0
>
SR
A
<
1
>
SR
A
<
2
>
SR
A<
3
>
SR
A
<
4
>
SR
A
<
5
>
SR
A
<
6
>
SR
A
<
7
>
SR
A
<
8
>
SR
A<
9
>
S
R
A
<
10>
S
R
A<
1
1
>
S
R
A
<
12>
CV
DD1
CG
N
D
2
DBCK0OS01
DBIN0OS00
DBOUT0
DBRQN1
DBCK1_OS11
DBIN1_OS10
DBOUT1
LRCKR
SCKR
LRCKT
SCKT
SDI0
SDI1 / SRA<21>
SDI2 / SRA<20>
SDO0 / SRA<19>
SDO1 / SRA<18>
SDO2 / SRA<17>
CASALE
DRD
DWR
SRA<15>
SRA<14>
SRA<13>
CVDD2
SRA<16>
CO
D
E
C0
CO
D
E
C1
CO
D
E
C2
CV
DD0
CG
N
D
0
CO
UT
<
5
>
CO
U
T
<
4
>
CO
U
T
<
3
>
CO
U
T
<
2
>
CO
U
T
<
1
>
CO
UT
<
0
>
V
R
EF
0
V
R
EF
1
V
R
EF
2
S
2DRE
F
CO
V
DD1
C
OIN
<
3
>
C
OIN
<
2
>
C
OIN
<
1
>
C
OIN
<
0
>
C
OGN
D
1
CO
V
DD2
GN
D
2
V
DD2
DB
RQ
N0
DSP0 GPIO0
DSP0 GPIO2
DSP0 GPIO1
DSP0 GPIO3
DSP0 GPIO4
DSP0 GPIO6
DSP0 GPIO5
DSP0 GPIO7
DSP1 GPIO4
DSP1 GPIO3
DSP1 GPIO1
DSP1 GPIO2
DSP1 GPIO0
DSP0 GPIO9
DSP0 GPIO11
DSP0 GPIO10
DSP0 GPIO8
DSP1 GPIO5
DSP1 GPIO6
DSP1 GPIO7
DSP1 GPIO8
DSP1 GPIO9
DSP1 GPIO11
DSP1 GPIO10
SRCCDC
CODEC
Test
IIC/SPI master
SPI display
PLL oscillator
RDS
SPDIF + Sample Rate Converter
EMI
SAI
Debug DSP1
Debug DSP0
Control Inputs
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD
VCC
Power supplies Digital
Analog
4.6
4.6
V
V
Analog Input Voltage
-0.5 to (VDD+0.5)
V
Digital Input Voltage
-0.5 to (VCC+0.5)
V
T
amb
Operating Temperature Range
-40 to 85
C
T
stg
Storage Temperature
-55 to 150
C
Warning: Operation at or beyond these limit may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
TDA7500
2/14
PIN DESCRIPTION
N
NAME
TYPE
DESCRIPTION
1
GND1
Ground pin dedicated to the digital periphery.
2
VDD1
Supply pin dedicated to the digital periphery.
3
TESTEN
I
Test Enable (Input). When active, puts the chip into test mode and
muxes the XTI clock to all flip-flops. When TEST_SE is also
active, the scan chain shifting is enabled.
4
TESTSE
I
SCAN Enable (Input). When active with TESTEN also active,
controls the shifting of the internal scan chains. When active with
TESTEN not active, sets all tri-state outputs into hi-impedance
mode
5
NRESET
I
System Reset (Input). A low level applied to NRESET input
initializes the IC.
6
SCKM/DSP0_GPIO0
I/O
I
2
C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/General
Purpose I/O (Input/Output). Clock line for I
2
C bus. Schmitt trigger
input. If SPI interface is enabled, behaves as SPI bit clock.
Optionally it can be used as general purpose I/O controlled by
DSP0.
7
MISOM/DSP0_GPIO1
I/O
I
2
C Serial Data Line (Input/Output)/SPI Master Input Slave Output
Serial Data (Input/Output)/General Purpose I/O (Input/Output).
Data line for I
2
C bus. Schmitt trigger input. If SPI is enabled,
behaves as Serial Data Input when in SPI Master Mode and Serial
Data Output when in SPI Slave Mode. Optionally it can be used as
general purpose I/O controlled by DSP0.
8
MOSIM/DSP0_GPIO2
I/O
SPI Master Output Slave Input Serial Data (Input/Output)/General
Purpose I/O (Input/Output). Serial Data Output when in SPI
Master Mode and Serial Data Input when in SPI Slave Mode.
Optionally it can be used as general purpose I/O controlled by
DSP0.
9
SSM/DSP0_GPIO3
I
SPI Slave Select (Input)/General Purpose I/O (Input/Output). If SPI
is enabled, behaves as Slave Select line for SPI bus. Optionally it
can be used as general purpose I/O controlled by DSP0.
10
SCKD/DSP0_GPIO4
I
SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit
clock. Schmitt trigger input. Optionally it can be used as general
purpose I/O controlled by DSP0.
11
MISOD/DSP0_GPIO5
I/O
SPI Master Input Slave Output Serial Data (Input/Output)/General
Purpose I/O (Input/Output). Schmitt trigger input. Behaves as
Serial Data Input when in SPI Master Mode and Serial Data
Output when in SPI Slave Mode. Optionally it can be used as
general purpose I/O controlled by DSP0.
12
MISOD/DSP0_GPIO6
I/O
SPI Master Output Slave Input Serial Data (Input/Output)/General
Purpose I/O (Input/Output). Serial Data Output when in SPI
Master Mode and Serial Data Input when in SPI Slave Mode.
Optionally it can be used as general purpose I/O controlled by
DSP0.
13
SSD/DSP0_GPIO7
I
SPI Slave Select (Input)/General Purpose I/O (Input/Output).
Behaves as Slave Select line for SPI bus. Optionally it can be
used as general purpose I/O controlled by DSP0.
14
CLKIN
I
Clock Input pin (Input). Clock from external digital audio source to
synchronize the internal PLL.
15
AVDD
audio source to synchronize the internal PLL.
16
XTI
I
Crystal Oscillator Input (Input). External Clock Input or crystal
Oscillator input.
17
XTO
O
Crystal Oscillator Output (Output). Crystal Oscillator output drive.
18
AGND
Ground pin dedicated to the PLL
19
RDSINT/DSP1_GPIO4
O
RDS bit/block interrupt (Output)/General Purpose I/O
(Input/Output). Provides an interrupt to the main micro. Optionally
it can be used as general purpose I/O controlled by DSP1.
TDA7500
3/14
N
NAME
TYPE
DESCRIPTION
20
RDSARI_SCK/DSP1_GPIO3
O
SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O
(Input/Output). Schmitt trigger input. If SPI interface is enabled,
behaves as SPI bit clock. Optionally it provides the ARI indication
bit. Optionally it can be used as general purpose I/O controlled by
DSP1.
21
RDSQAL_SO/DSP1_GPIO2
O
SPI Slave Output Serial Data (Output)/RDS Bit Quality
(Output)/General Purpose I/O (Input/Output). If SPI is enabled,
behaves as Serial Data Output. Optionally it provides the RDS
serial data quality information. Optionally it can be used as general
purpose I/O controlled by DSP1.
22
RDSDAT_SI/DSP1_GPIO1
I
SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/General
Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial
Data Input. Optionally it provides the RDS serial data stream.
Optionally it can be used as general purpose I/O controlled by
DSP1.
23
RDSCLK_SS/DSP1_GPIO0
I
SPI Chip Select (Input)/RDS Bit Clock (Output)/General Purpose
I/O (Input/Output). If SPI is enabled, behaves as Chip Select line
for SPI bus. Optionally it provides the 1187.5Hz RDS Bit Clock.
Optionally it can be used as general purpose I/O controlled by
DSP1.
24
INT
I
External interrupt line (Input). When this line is asserted low, the
DSP may be interrupted.
25
CGND1
Ground pin dedicated to the digital core part.
26
CVDD1
Supply pin dedicated to the digital core part.
27
SCRCCD
I
SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital
audio source like a CD.
28
SCRCMD
I
SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital
audio source like a MD.
29
DSRA<7>
I/O
DSP SRAM Data Lines<7> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 7.
30
DSRA<6>
I/O
DSP SRAM Data Lines<6> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 6.
31
DSRA<5>
I/O
DSP SRAM Data Lines<5> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 5.
32
DSRA<4>
I/O
DSP SRAM Data Lines<4> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 4.
33
DSRA<3>
I/O
DSP SRAM Data Line<3> (Input/Output)/DSP DRAM Data
Line<3> (Input/Output). This pin act as the EMI data line 3 in both
SRAM Mode and DRAM Mode.
34
DSRA<2>
I/O
DSP SRAM Data Line<2> (Input/Output)/DSP DRAM Data
Line<2> (Input/Output). This pin act as the EMI data line 2 in both
SRAM Mode and DRAM Mode.
35
DSRA<1>
I/O
DSP SRAM Data Line<1> (Input/Output)/DSP DRAM Data
Line<1> (Input/Output). This pin act as the EMI data line 1 in both
SRAM Mode and DRAM Mode.
36
DSRA<0>
I/O
DSP SRAM Data Line<0> (Input/Output)/DSP DRAM Data
Line<0> (Input/Output). This pin act as the EMI data line 0 in both
SRAM Mode and DRAM Mode.
37
SRA<0>
O
DSP SRAM Address Line<0> (Output)/DSP DRAM Address
Line<0> (Output). This pin act as the EMI address line 0 in both
SRAM Mode and DRAM Mode.
38
SRA<1>
O
DSP SRAM Address Line<1> (Output)/DSP DRAM Address
Line<1> (Output). This pin act as the EMI address line 1 in both
SRAM Mode and DRAM Mode.
PIN DESCRIPTION (continued)
TDA7500
4/14
N
NAME
TYPE
DESCRIPTION
39
SRA<2>
O
DSP SRAM Address Line<2> (Output)/DSP DRAM Address
Line<2> (Output). This pin act as the EMI address line 2 in both
SRAM Mode and DRAM Mode.
40
SRA<3>
O
DSP SRAM Address Line<3> (Output)/DSP DRAM Address
Line<3> (Output). This pin act as the EMI address line 3 in both
SRAM Mode and DRAM Mode.
41
SRA<4>
O
DSP SRAM Address Line<4> (Output)/DSP DRAM Address
Line<4> (Output). This pin act as the EMI address line 4 in both
SRAM Mode and DRAM Mode.
42
SRA<5>
O
DSP SRAM Address Line<5> (Output)/DSP DRAM Address
Line<5> (Output). This pin act as the EMI address line 5 in both
SRAM Mode and DRAM Mode.
43
SRA<6>
O
DSP SRAM Address Line<6> (Output)/DSP DRAM Address
Line<6> (Output). This pin act as the EMI address line 6 in both
SRAM Mode and DRAM Mode.
44
SRA<7>
O
DSP SRAM Address Line<7> (Output)/DSP DRAM Address
Line<7> (Output). This pin act as the EMI address line 7 in both
SRAM Mode and DRAM Mode.
45
SRA<8>
O
DSP SRAM Address Line<8> (Output)/DSP DRAM Address
Line<8> (Output). This pin act as the EMI address line 8 in both
SRAM Mode and DRAM Mode.
46
SRA<9>
O
DSP SRAM Address Line<9> (Output)/DSP DRAM Address
Line<9> (Output). This pin act as the EMI address line 9 in both
SRAM Mode and DRAM Mode.
47
SRA<10>
O
DSP SRAM Address Line<10> (Output)/DSP DRAM Address
Line<10> (Output). This pin act as the EMI address line 10 in both
SRAM Mode and DRAM Mode.
48
SRA<11>
O
DSP SRAM Address Line<11> (Output)/DSP DRAM Address
Line<11> (Output). This pin act as the EMI address line 11 in both
SRAM Mode and DRAM Mode.
49
SRA<12>
O
DSP SRAM Address Line<12> (Output)/DSP DRAM Address
Line<12> (Output). This pin act as the EMI address line 12 in both
SRAM Mode and DRAM Mode.
50
CGND2
Ground pin dedicated to the digital core part.
51
CVDD2
Supply pin dedicated to the digital core part.
52
SRA<13>
O
DSP SRAM Address Line<13> (Output)/DSP DRAM Address
Line<13> (Output). This pin act as the EMI address line 13in both
SRAM Mode and DRAM Mode.
53
SRA<14>
O
DSP SRAM Address Line<14> (Output)/DSP DRAM Address
Line<14> (Output). This pin act as the EMI address line 14 in both
SRAM Mode and DRAM Mode.
54
SRA<15>
O
DSP SRAM Address Line<15> (Output)/DSP DRAM Address
Line<15> (Output). This pin act as the EMI address line 15 in both
SRAM Mode and DRAM Mode.
55
SRA<16>/DSP0_GPIO8
O
DSP SRAM Address Line<16> (Output)/DSP DRAM Address
Line<16> (Output)/General Purpose I/O (Input/Output). This pin
acts as the EMI address line 16 in both SRAM Mode and DRAM
Mode. Optionally it can be used as general purpose I/O controlled
by DSP0.
56
DWR
O
DSP SRAM Write Enable (Output)/DRAM Write Enable (Output).
This pin serves as the write enable for the EMI in both DRAM and
SRAM Mode.
57
DRD
O
DSP SRAM Read Enable(Output)/DRAM Read Enable (Output).
This pin serves as the read enable for the EMI in both DRAM and
SRAM Mode.
PIN DESCRIPTION (continued)
TDA7500
5/14
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