24-BIT, FIXED POINT, 50 MIPS DSP CORE
LARGE ON-BOARD PROGRAM ROM AND
DATA RAM (UP TO 16Kw ROM/RAM AND
16Kw RAM)
INTEGRATED STEREO A/D AND D/A, 16-BIT
SIGMA-DELTA
PROGRAMMABLE CODEC SAMPLE RATE
FROM 4 TO 48 kHz
ON-BOARD PLL FOR CORE CLOCK AND
CONVERTERS
MANAGEMENT OF EXTERNAL
FLASH/SRAM/DRAM MEMORY BANK
I

C OR SPI SERIAL INTERFACE FOR EX-

TERNAL CONTROL
80-PIN TQFP, 0.65 mm PITCH
AUTOMOTIVE GRADE (FROM -40° C to
+85°C)

DESCRIPTION
The TDA755X family is a high performances, fully
programmable 24-bit, 50 MIPS Digital Signal

Processor (DSP), designed to support several
speech and audio applications, as Automatic
Speech Recognition, Speech Synthesis, Speaker
Verification, Echo and Noise Cancellation. Soft-
ware for these applications is licenced by Lernout
& Hauspie and NCTI.
It offers an effective solution for this kind of appli-
cations because of the A/D and D/A converters
and the big amount of memory integrated on chip.

This is preliminary information on a new product now in development. Details are subject to change without notice.

September 1999

C/SPI

PORT

FLAGS

FLASH

INTERFACE

SAI

ROM/RAM

DSP

CORE

PLL

RAM

ANALOG OUT

MULTIPLEXED BUS

ANALOG IN

D99AU1020A

DAC

ADC

BLOCK DIAGRAM

TQFP80

TDA7550/R TDA7551

TDA7552 TDA7553

DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND

AUDIO APPLICATIONS

PRODUCT PREVIEW

1/12

APPLICATIONS
Real time digital speech and audio processing:
speech recognition, speech synthesis, speech

compression, echo cancelling, noise cancelling,
speaker verification.

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

DDP

Pads DC Supply Voltage

0.3 to V

+0.3

, V

Digital or Analog Input Voltage

0.3 to V

DDP

+0.3

Operating Temperature Range

40 to +85

°C

stg

Storage Temperature Range

55 to +150

°C

tot

Total Maximum Power Dissipation

32 33 34 35 36

75 74 73 72

69 68 67 66 65

EMI_A8

EMI_AD7

GND

EMI_AD6

EMI_AD5

VDD

EMI_A13

EMI_A12

EMI_A11

EMI_A7

EMI_A10

MOSI

VDD

GND

TEST3

SCK

SDI

LRCK

VDD

GND

SDO

GPIO1

DRDN

GND

ALE

XTO

PGND

PVCC

XTI

CLKOUT

VDD

GPIO4

GPIO7

VOUTL

VOUTR

CVDD

GPIO3

GPIO6

CGND

CGNDA

VINL

VINR

VDD

GND

TQFP80

26 27 28 29 30

EMI_AD0

EMI_AD1

EMI_AD2

EMI_AD3

EMI_AD4

EMI_A21

DWRN

TEST1

TEST2

MISO

21 22 23 24 25

GPIO2

GND

SDA/SS

SCL/SCK

VDD

EMI_A16

GND

VDD

EMI_A14

EMI_A15

64 63 62 61

REFCAP

VREF

CVDDA

TEST4

37 38 39 40

GPIO0

GPIO5

DBCK

DBIN

INTN

DBRQN

DBOUT

NRESET

EMI_A20

EMI_A19

EMI_A18

EMI_A17

PIN CONNECTION

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PIN FUNCTIONS

Name

Type

Description

EMI_AD5

I/O

EMI Multiplexed Address/Data Line 5. these pin acts as the EMI multiplexed
address and data line 5

EMI_AD6

I/O

EMI Multiplexed Address/Data Line 6. these pin acts as the EMI multiplexed
address and data line 6

VDD

Digital power supply

GND

Ground

EMI_AD7

I/O

EMI Multiplexed Address/Data Line 7. these pin acts as the EMI multiplexed
address and data line 7

EMI_A8

EMI Address Line 8. these pin acts as the EMI address line 8. The interface is
designed to address up to 4 Mbytes of External Flash, EPROM or SRAM.

EMI_A9

EMI Address Line 9. these pin acts as the EMI address line 9.

EMI_A10

EMI Address Line 10. these pin acts as the EMI address line 10.

EMI_A11

EMI Address Line 11. these pin acts as the EMI address line 11.

EMI_A12

EMI Address Line 12. these pin acts as the EMI address line 12.

EMI_A13

EMI Address Line 13. these pin acts as the EMI address line 13.

EMI_A14

EMI Address Line 14. these pin acts as the EMI address line 14.

EMI_A15

EMI Address Line 15. these pin acts as the EMI address line 15.

VDD

Digital power supply

GND

Ground

EMI_A16

EMI Address Line 16. these pin acts as the EMI address line 16.

EMI_A17

EMI Address Line 17. these pin acts as the EMI address line 17.

EMI_A18

EMI Address Line 18. these pin acts as the EMI address line 18.

EMI_A19

EMI Address Line 19. these pin acts as the EMI address line 19.

EMI_A20

EMI Address Line 20. these pin acts as the EMI address line 20.

EMI_A21

EMI Address Line 21. these pin acts as the EMI address line 21.

DWRN

EMI Write Enable. This pin serves as the write enable for the EMI

TEST1

Test 1. Used for test: set to LOW for normal operation

TEST2

Test 2. Used for test: set to HIGH for normal operation

MISO

I/O

SPI Master Output Slave Input Serial Data. Serial Data Output for SPI type serial
Port when in SPI master Mode and Serial Data Input when in SPI Slave Mode

MOSI

I/O

SPI Master Input Slave Output Serial Data. Serial Data Input for SPI type serial
Port when in SPI master Mode and Serial Data Output when in SPI Slave Mode

VDD

Digital Power Supply

GND

Ground

TEST3

Test 3. Used for test: set to LOW for normal operation

SDI

SAI Data Input

SCK

I/O

SAI Bit Clock

LRCK

I/O

SAI Left/Right Clock

VDD

Digital power supply

GND

Ground

SDO

SAI Data Output

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

3/12

Name

Type

Description

GPIO1

I/O

General Purpose I/O

GPIO0

I/O

General Purpose I/O

GPIO5

I/O

General Purpose I/O

DBCK

I/O

Debug port Bit Clock/Chip Status 1. The serial clock for the Debug Port is
provided. May also be used as GPIO9.

DBIN

I/O

Debug port Serial Input/Chip Status 0. The serial data input for the Debug Port is
provided. May also be used as GPIO11.

DBOUT

I/O

Debug Port Serial Output. This pin is the serial Data output for the Debug port.
May also be used as GPIO10.

DBRQN

Debug Port Request Input. This pin is used to request Debug Mode operation to
Euterpe

NRESET

System Reset. A low level applied to RESET input initializes the IC.

INTN

External interrupt line. When this line is asserted low the DSP may be interrupted.

SCL/SCK

I/O

C Serial Clock Line. Clock line for I

C bus. Schmitt trigger input.

I/O

SPI Bit Clock. If SPI interface is enabled, it behaves as SPI bit clock.

SDA/SS

I/O

C Serial Data Line. Data line for I

C bus. Schmitt trigger input.

SPI Slave Select. If SPI interface is enabled, it behaves as Slave select line for
SPI bus.

VDD

Digital Power Supply

GND

Ground

GPIO2

I/O

General Purpose I/O

GPIO6

I/O

General Purpose I/O

GPIO3

I/O

General Purpose I/O

CGND

Ground for the internal CODEC cell

CVDD

Power Supply for the internal CODEC cell

VOUTR

Single-ended right channel analogue output from DAC

VOUTL

Single-ended left channel analogue output from DAC

VDD

Digital power supply

GND

Ground

VINR

Single-ended right channel analogue input to ADC

VINL

Single-ended left channel analogue input to ADC

CGNDA

Ground for the internal CODEC cell

TEST4

Connect a 22K pull-down resistor

CVDDA

Power Supply for the internal CODEC cell

VREF

Voltage Reference from the CODEC cell

REFCAP

Voltage Reference Capacitor Bypass

GPIO7

I/O

General Purpose I/O

GPIO4

I/O

General Purpose I/O

VDD

Digital power supply

CLKOUT

Clock Output. Output Clock divided down from PLL

PIN FUNCTIONS (continued)

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Name

Type

Description

XTI

Crystal Oscillator Input. Crystal Oscillator Input drive

PGND

PLL Ground Input. Ground connection for Oscillator circuit

PVCC

PLL Power Supply Positive. Supply for PLL Clock Oscillator

XTO

Crystal Oscillator Output. Crystal Oscillator Output drive

ALE

EMI Address Latch Enable. This pin acts as the EMI Address Latch Enable for the
External Memory Interface

GND

Ground

DRDN

EMI Read Enable. This pin serves as the read enable for the EMI

EMI_AD0

I/O

EMI Multiplexed Address/Data Line 0. these pin acts as the EMI multiplexed
address and data line 0

EMI_AD1

I/O

EMI Multiplexed Address/Data Line 1. these pin acts as the EMI multiplexed
address and data line 1

EMI_AD2

I/O

EMI Multiplexed Address/Data Line 2. these pin acts as the EMI multiplexed
address and data line 2

EMI_AD3

I/O

EMI Multiplexed Address/Data Line 3. these pin acts as the EMI multiplexed
address and data line 3

EMI_AD4

I/O

EMI Multiplexed Address/Data Line 4. these pin acts as the EMI multiplexed
address and data line 4

RECOMMENDED DC OPERATING CONDITIONS

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Power Supply Volrage Range

3.3

3.6

Operating Junction Temp.

125

°C

PIN FUNCTIONS (continued)

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

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24 BIT DSP CORE
The DSP Core is a general purpose 24-bit DSP.
The main feature of the DSP Core are listed be-
low:

50Mhz Operating Frequency (50 MIPS)
Single cycle multiply and accumulate
2x56-bit Accumulators
Double precision multiply
Convergent rounding
Scaling and saturation arithmetic
48-bit or 2x24-bit parallel moves
64 interrupt vector locations
Fast or long interrupts possible
Programmable interrupt priorities and masking
8 each Address Registers, Address Offset
Registers and Address Modulo Registers
Linear, Reverse Carry, Multiple Buffer Modulo,
Multiple Wrap-around Modulo address arith-
metic
Post-increment or decrement by 1 or by offset,
Index by offset, predecrement address
Repeat instruction and zero overhead DO
loops
Hardware stackcapable of nesting 7 DO loops
or 15 interrupts/subroutines
Bit manipulation instructions possible on all
registers and memory locations. Also Jump on
bit test.
Data Arithmetic Logic Unit (DALU)
Address Generation Unit (AGU)
Program Control Unit (PCU)
Three Data Buses
Three Address Buses
Internal Data Bus Switch
bit Manipulation Unit
Debug Logic

Memories
16384x24-bit Program ROM used for storing the
program code.
16384x24-bit Data RAM used for storing Data.

DSP peripherals

Serial Audio Interface (SAI)
The SAI is used to deliver digital audio to the
DSP from an external source and to deliver
digital audio from the DSP to an external DAC.
It allows using an external CODEC. The main
features of this block are listed below:
One Data Transmission Line
One Data Reception Line

Master and Slave Operating Modes
Reference clock for transmission supplied
Transmit and Receive Interrupt Logic
modified to trigger on Left/Right data pairs
Receive and Transmit Data Registers have
two locations to hold left and right data

C interface/SPI

The inter integrated-circuit bus is a simple bi-
directional two-wire bus used for efficient inter
IC control. All I

C bus compatible devices in-

corporate an on-chip interface which allows
them communicate directly with each via the
I

C bus.

Every component hoocked up to the I

C bus

has it's own unique address whether it is a
CPU, memory or some other complex function
chip. Each of these chips can act as a receiver
and/or transmitter depending on it's functional-
ity.
The Serial Peripheral Interface (SPI) can be
enabled instead of the I

C interface. During an

SPI transfer, data is trasmitted and received
simulaneously. A serial clock line synchronizes
shifting and sampling of the information on the
two serial data lines. A slave select line allows
individual selection of a slve SPI device. When
an SPI transfer occurs an 8-bit word is shifted
out one data pin while another 8-bit character
is simultaneously shifted in a second data pin.
The central element in the SPI system is the
shift register and the read data buffer. The sys-
tem is single buffered in the trasmit direction
and double buffered in the receive direction.

EMI

The External Memory Interface is viewed as a
memory mapped peripheral. Data transfers are
performed by moving data into/from data regis-
ters and the control is exercised by polling
status flags in the control/status register or by
servicing interrupts. An external memory write
is executed by writing data into the Data Write
register. An external memory read operation is
executed by either writing to the Offset register
or reading the Data read register, depending
on the configuration.
The main features of the EMI are listed below:
Data bus width fixed at 4 bits for DRAM and
8 bits for SRAM
22 bit address bus multiplexed with an 8 bit
data bus
Three choices of data word lenghths, 8, 16 or
24 bits in SRAM mode
Two choices of data word lenght, 16 or 24
bits in DRAM mode
Thirteen address lines 2

= 256Mbits

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

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addressable DRAM
Refresh rate for DRAM can be chosen
among sixteen divide factors
SRAM or DRAM relative addressing modes
2

=4MBytes addressable SRAM

Four SRAM Timing choices
Two Read Offset Register

PLL
The Euterpe clock system generates the fol-
lowing clocks:
DCLK the DSP core clock
MCLK CODEC master clock
LRCLK left/right clock for the SAI and
the CODEC
SCLK shift serial clock for the SAI and
the CODEC
The output of the PLL operates from 70 to 140
MHz. The DSP core can operate with a clock
up to 50 MHz.

From the VCO output the audio clock are de-
rived.

CODEC
The main features of the CODEC are listed be-
low:
one 16-bit Delta Sigma Stereo ADC
80 dB Dynamic Range
Oversampling Ratio: 128
one 16-bit Delta Sigma Stereo DAC
80 dB Dynamic Range
Interpolating Ratio: 128
Sampling rates of 4kHz to 48kHz
Signal Noise Ratio: 80 dB Typ.
The analog interface is in the form of differen-
tial signals for each channel. The interface on
the digital side has the form of an SAI interface
and can interface directly to an SAI channel
and then to the DSP core.

DEVICE versions

Part No.

Internal

Program

Memory

Function

Serial I/F

External
Memory

Audio

Input

Audio

Output

Software

TDA7550R

RAM

One of the
below

Master or
Slave I

FLASH

or RAM

YES

(by appl.)

YES

(by appl.)

Custom
Specs.

TDA7550

ROM

Speech
Recognition

Slave I

FLASH

YES, 1

(voice in)

YES

(prompts)

ASR-311
Engine by
Lernout &
Hauspie

TDA7551

Speaker
Verification

Slave I

Optional

FLASH

YES, 1

(voice in)

YES

(prompts)

SV208
Engine by
Lernout &
Hauspie

TDA7552

Text-To-
Speech

Slave I

YES

(voice out)

TTS3000
Engine by
Lernout &
Hauspie

TDA7553

SF/FDE

Master

C or SPI

(RAM)

YES, 1

(voice in)

YES

(filtered)

Engine by
NCTI

Note: TDA7550 requires word databases on FLASH (cfr. Document words)

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TDA7550

ASR311 Automatic Speech Recognition solution

The TDA-7550 is a single-chip solution for isolated word speech recognition, featuring the Lernout &
Hauspie ASR311 Automatic Speech Recognition engine.

Word base recognition
Isolated word recognition

The words database is created from an extensive set of recordings,
with an equal distribution of speakers; the recordings are partially
taken in automotive conditions at low, medium and high speed.

Quasi-connected digit recognition

Minimum pause between two numbers 150ms.

Noise-robust recognition

The recognition is still very robust even in high noisy environment (as
automotive or industrial environments)

Speaker-independent recognition

Recognition is affected by selected language, no training is required

Speaker-dependent recognition

User words can be stored and mixed with speaker-independent words

Training phase

User words can be trained by repeating three times the selected word.
Recognition is guaranteed when the same speaker is talking.

Prompts

Voice prompts can be stored on FLASH for creating a voice-based
user interface

Control through I

Management of the recognition engine, user words and voice prompts
is accomplished through an I

C protocol: the TDA7550 appears as a

slave I

C device.

Many languages available

Vocabularies in the following languages are available:
US English, French, German, Italian, Spanish, Japanese.
All the vocabularies have a common subset of about 150 words. Other
words and languages are available on request.

The external FLASH is used to store:

Speaker Independent vocabulary (4 KB/word)

User Words (4 KB/word)

Voice prompts (11 KB/sec)

Sample rate:

11.025 kHz

Recognition rate:

> 95%

Maximum number of active words:

Maximum number of words:

450

Word memory requirements:

4 KB (speaker-independent)
4 KB (speaker-dependent)

Prompt memory requirements:

11 KB/s

audio amp

spkr

mic preamp

slave I

EMI

ADC

DAC

Up to

4 MB

service request

Figure 1.

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

8/12

audio amp (optional)

spkr

mic preamp

Controller

EMI

Pass-phrases can reside here

to external world

slave I

ADC

DAC

Up to

4 MB

service request

Figure 2.

TDA7551

SV208 Speaker Verification solution

The TDA7551 is a single-chip solution for speaker verification, featuring the Lernout & Hauspie SV208
verification engine. Pass-phrases can be stored by performing an enrollment (the pass-phrase must be
repeated three times), then the incoming prompt can be compared with the pre-stored pass-phrase to
verify the speaker identity.

Known password speaker recognition

Noise-robust recognition of isolated words

Enrollment phase

The speaker associates his identity to an utterance, which must last
from 1 to 2 seconds, and reapeat it three times; the algorithm performs
an analysis and accepts or rejects the enrollment phase.

Verification phase

The claimed identity of the speaker is compared with the result of the
verification phase, in which the input prompt is compared with the
selected pass-phrase.

Control through I

Management of the verification engine is accomplished through an I

protocol: the TDA7551 appears as a slave I

C device.

Sample rate:

8 kHz

Equal error rate:

> 94%

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

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TDA7552

TTS3000 Text-To-Speech solution

The TDA7551 is part of a two-chip solution for Text-To-Speech, featuring the Lernout & Hauspie
TTS3000 engine. Two devices are needed:

A 16-bit microcontroller (ST10) for string analysis and conversion

The TDA7552 DSP for voice synthesis.

An external application sends ASCII strings to the microcontroller, which perform an analysis of the entire
sentence; language-dependent data is needed on the FLASH accessed by the ST10. As a result of the
analysis, a data stream is sent through I

C to the TDS7552 DSP. No external memory is required by the

DSP. The software running on the TDA7552 DSP is independent from languages.

Control through I

Management of the DSP is accomplished through an I

C protocol: the

TDA7552 appears as a slave i

c device.

Many languages available

The following languages are available:
US English, French, German, Italian, Spanish, Japanese. Other
languages available on request.

Sample rate: 11.025 kHz

audio amp

language-independent code

language-

dependent

code

ASCII string

Figure 3.

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

10/12

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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