TDA8140
HORIZONTAL DEFLECTION POWER DRIVER
September 1993
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT
SENSE IN
SENSE GND
SPECIAL REMOTE STANDBY
CONTROL INPUT
PROTECTION AND REMOTE
STANDBY INPUT
V
CC
C
EXT
COMMON GND
8
1
4
0
-0
1
.
EPS
PIN CONNECTIONS
POWERDIP (8 + 8)
(Plastic Package)
ORDER CODE : TDA8140
.
CONTROLLED DRIVING OF THE POWER
TRANSISTOR DURING TURN ON AND OFF
PHASE FOR MINIMUM POWER DISSIPA-
TION AND HIGH RELIABILITY
.
HIGH SOURCE AND SINK CURRENT CAPA-
BILITY
.
DISCHARGE CURRENT DERIVED FROM
PEAK CHARGE CURRENT
.
CONTROLLED DISCHARGE TIMING
.
DISABLE FUNCTION FOR SUPPLY UNDER
VOLTAGE AND NONSYNCHRONOUS OP-
ERATION
.
PROTECTION FUNCTION WITH HYSTERE-
SIS FOR OVERTEMPERATURE
.
OUTPUT DIODE CLAMPING
.
LIMITING OF THE COLLECTOR PEAK CUR-
RENT OF THE DEFLECTION POWER TRAN-
SISTOR DURING TURN ON PERIOD
.
SPECIAL REMOTE FUNCTION WITH DELAY
TIME TO SWITCH THE OUTPUT ON
DESCRIPTION
The TDA 8140 is a monolithic integrated circuit de-
signed to drive the horizontal deflection power tran-
sistor.
The current source characteristic of this device is
adapted to the on-linear current gain behaviour of
the power transistor providing a minimum power
dissipation. The TDA8140 is internally protected
against short circuit and thermal overload.
1/10
6
7
SYNC. DET.
THERMAL
PROTECTION
I
B1
S
V
I
B2
C
V
8
2
1
3
4
5
9
10
11
12
13
14
15
16
SPECIAL
REMOTE
STANDBY
CONTROL
IN
PROTECTION AND
REMOTE STANBY INPUT
C
1nF
100k
OUT
SENSE
IN
GND
27
220
F
BU508
22nF
4.7
10
H
0.15
V
H
R
S
V
C C
+
&
TDA8140
8
1
4
0
-0
2
.
EP
S
BLOCK DIAGRAM
PIN FUNCTION
Pin
Name
Function
1
Output
Device Output
2
V
CC
Supply Voltage
3
Sense Input
Input voltage that determines output current.
4
Sense GND
Reference Ground for Input Voltage at Sense Input
5
C
EXT
Capacitor between this terminal and Sense Ground determines the
current slope dI
o
/d
t
during off phase.
6
Special Remote/Standby
Low level at this input sets the device after a delay time t
dr
in the
standby mode independent from control input (2nd priority) (in
standard applications pin 6 must be left unconnected).
7
Control Input
High level at this input switches the BU508 off, low level switches
the BU508 on.
8
Protection and Remote Standby
Input
A high level at this input switches the BU508 off independent from
all other inputs (1st priority).
9-16
Power Ground
Common Ground
81
40
-
0
1.
T
B
L
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
18
V
I
d
Output Current
Internally Limited
P
tot
Power Dissipation
Internally Limited
T
stg
, T
j
Storage and Junction Temperature
40, + 150
C
T
oper
Operating Temperature
0, + 70
C
81
40
-
0
2
.
T
B
L
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction-ambient
Max
70
C/W
R
th j-case
Thermal Resistance Junction-case
Max
15
C/W
81
40
-
0
3
.
T
B
L
TDA8140
2/10
ELECTRICAL CHARACTERISTICS (V
CC
= 12V, T
amb
= 25
o
C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
7
18
V
I
Q
Quiescent Current
All Inputs Open
10
15
25
mA
I
p0
Positive Output Current (source)
1.5
A
I
n0
Negative Output Current (sink)
2
A
I
o0
Positive quiescent output current forcing
the output to 6 V and the sense input to
ground, output externally forced to 6V
Remote Input 1
Remote Input 0
120
50
150
80
200
100
mA
mA
G
ON
Transconductance ON Phase (1)
See Figure 1
1.8
2.0
2.2
A/V
G
OFF
Transconductance OFF Phase (2)
See Figure 1
1.8
2.0
2.2
A/V
G
REMOTE
Transconductance Standby Mode
Remote Input 0
0.675
0.75
0.825
A/V
I
5
Current Source Pin 5
V
6
= 500mV
135
165
200
A
R
INS
Sense Input Resistance
V
S
> 0
V
S
< 0
0.7
0.35
1
0.5
1.3
0.7
k
k
I
INS
Sense Input Bias Current
V
S
= 0, Remote Input 1
200
300
400
A
R
SYN
Synchronous Detection Input Resistance
V
SYN
< 7V
V
SYN
> 7V
30
7
60
10
150
15
k
k
V
THS
Threshold Voltage of the Synchronous
Detection Input
1
1.8
2.8
V
V
SYN
Sync Detect Input Voltage
30
V
V
THA
Threshold Voltage of Control Input
1.5
2
2.5
V
I
INA
Pull up Current of Control Input
0 < V
IN
< V
THA
V
IN
> V
THA
+ 0.5V
50
- 1
100
0
160
+ 1
A
A
V
THB
Threshold Voltage Remote Input
1.5
2
2.5
V
I
INB
Pull up Current of the Remote Input
0 < V
IN
< V
THB
V
IN
> V
THB
+ 0.5V
50
1
100
0
160
+ 1
A
A
t
dr
Remote Delay Time (3)
190
250
300
s
t
don
On Delay Time
3
4.5
s
V
CC
V
OUT
Output Voltage Drop for I
p0
= 1 A
2
2.8
3
V
V
CC ON
Supply Voltage for Device "ON"
I
0
0
5.8
6.4
7.0
V
V
CC OFF
Supply Voltage for Device "OFF"
(output internally switched to ground)
5.6
V
CC ON
0.2 V
6.8
V
V
S limit
Sense Limit Voltage (4)
0.8
0.9
1
V
81
40
-
0
4
.
T
B
L
Notes : 1. G
ON
is measured with V
3
varying from 150mV to 350mV (Pin 5 is grounded)
2. G
OFF
is measured with V
5
varying from 150mV to 350mV (Pin 3 is grounded)
3. When the remote input goes from HIGH to LOW the BU508 is switched off and it remains in this condition for the time t
dr
.
4. The sense input voltage V
S
is internally limited and results in a limited positive output current I
p0
= g V
S
limit. Note that due to
the storage time t
S
of the BU508 limiting of V
S
leads to a reduced base current of the BU508 and the output current I
0
is going to
the positive quiescent current I
O0
.
TRUTH TABLE
Logic Inputs
Output I
o
Mode
Control Input
Remote/Standby
0
Floating or 1
Floating or 1
Floating or 1
I
o
> 0
I
o
< 0 (5)
BU508 ON
BU508 OFF
Normal Function
X
0
I
o
< 0 (5)
0 < t < t
dr
BU508 OFF
Remote/Standby
Function
X
0
I
o
> 0
t > td
r
BU508 ON
81
40-
05
.
T
B
L
Note :
5. I
O
< 0 means that the sink current flows into the output to ground.
TDA8140
3/10
2.2
1.8
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
G
G
or
ON
OFF
(A/V)
(A/V)
2.1
2.0
1.9
1.7
V
V
(mV) or
Pin3
Pin5
(mV)
8
1
4
0
-0
3
.
EP
S
Figure 1 :
G
ON
V
Pin3
and
|
G
OFF
|
V
Pin5
1
3
4
BU508
R
S
8
7
5
9
10
11
12
13
14
15
16
TDA8140
+12V
STANDBY
OUT
R
f
C
a
D1
L
O
R
O
C
O
R
b
C
b
C
S
2
8
1
4
0
-0
4
.
EPS
Figure 2 : Large Screen Application
TDA8140
4/10
OUT
+12V
TDA8
14
0
C
b
L
o
D1
BU
R
b
C
a
C
o
C
s
R
o
R
f
R
s
STANDBY
8
1
4
0
-0
5
.
EP
S
Figure 3 : P.C. Board and Components Layout of the Figure 2 (1 : 1 scale)
COMPONENTS LIST FOR TYPICAL APPLICATION
CRT
22"/26" 100
14"/20" 90
CRT
22"/26" 100
14"/20" 90
C
a
47
F
47
F
R
b
4.7
4.7
R
o
27
2W
27
1 W
C
b
47 nF
47 nF
C
o
220
F
220
F
R
s
0.15
0.1
L
o
10
H
10
H
C
s
1 nF
1 nF
81
40
-
0
6
.
T
B
L
APPLICATION INFORMATION
The conventional deflection system is shown in Figure 4. The driving circuit consists of a bipolar power
transistor driven by a transformer and a medium power element plus some passive components.
V
CC
+
V
IN
I
B
I
C
I
D
YOKE
DEFLECTION CIRCUIT
HORIZONTAL
TRANSFORMER
DRIVING CIRCUIT
8
1
4
0
-0
6
.
EPS
Figure 4 : Conventional Horizontal Deflection System for TVs
TDA8140
5/10
OFF PHASE
CONTROL
INPUT
t
I
0
ON PHASE
t
I
p0
I
0
t
don
I
n0
t
S
I
S0
t
S
dI
0
dt
=
I
S0
8
1
4
0
-0
8
.
EPS
Figure 6
During the active deflection phase the collector
current of the power transistor is linearly rising and
the driving circuitry must be adapted to the required
base current in order to ensure the power transistor
saturation.
According to the limited components number the
typical approach of the present TVs provides only
a rough approximation of this objective ; in Figure 5
we give a comparison between the typical real base
current and the ideal base current waveform and
the collector waveform.
The marked area represents a useless base cur-
rent which gives an additional power dissipation on
the power transistor.
Furthermore during the turn-ON and turn-OFF tran-
sient phase of the chassis the power transistor is
extremely stressed when the conventional network
cannot guarantee the saturation ; for this reason,
generally, the driving circuit must be carefully de-
signed and is different for each deflection system.
The new approach, using the TDA 8140, over-
comes these restrictions by means of a feedback
principle.
As shown in Figure 5, at each instant of time the
ideal base current of the power transistor results
from its collector current divided by such current
gain which ensure the saturation ; thus the required
base current I
b
can be easily generated by a feed-
back transconductance amplifier g
m
which senses
the deflection current across the resistor R
s
at the
emitter of the power transistor and delivers :
I
b
= R
S
.
g
m
.
I
e
The transconductance must only fulfill the condi-
tion :
1
1
+
min
1
R
S
<
gm
<
1
R
S
Where
min
is the minimum current gain of the
transistor. This method always ensures the correct
base current and acts time independent on princi-
ple.
For the turn-OFF, the base of the power transistor
must be discharged by a quasi linear time decreas-
ing current as given in Figure 6.
Conventional driver systems inherently result into
a stable condition with a constant peak current
magnitude.
This is due to the constant base charge in the
turn-ON phase independent from the collector cur-
rent ; hence a high peak current results into a low
storage time of the transistor because the excess
base charge is a minimum and vice versa. In the
active deflection the required function, high peak
current-fast switch-OFF and low peak current-slow
switch-OFF, is obtained by a controlled base dis-
charge current for the power transistor ; the nega-
tive slope of this ramp is proportional to the actual
sensed current.
As a result, the active driving system even im-
proves the sharpness of vertical lines on the screen
compared with the traditional solution due to the
increased stability factor of the loop represented as
the variation of the storage time versus the collector
peak current.
I
C
I
C
t
t
I
BIAS
D
I
t
S
Base Bias Current
Off Phase
On Phase
Off Phase
Real Base Current
Ideal Base Current
8
1
4
0
-0
7
.
EPS
Figure 5 : Waveforms of Collector and
Base Current
TDA8140
6/10
CIRCUIT DESCRIPTION
Figure 7 shows the block diagram of the TDA8140,
the circuit consists of an input transconductance
amplifier composed by Q1, Q2, Q3 and Q4.
The symmetrical output current is fed into the load
resistor R1 and R2 ; the two amplifiers V1 and V2
realize a floating voltage to current converter which
can drive 1.2A sink current and 2A source current
for a wide common output range.
So, the overall transconductance results into :
g
m
=
R1
+
R2
R3
1
R5
A current source I
1
generates a drop of 70mV
across the resistor R4 which provides an output
bias current of 140mA ; the control input determines
the turn ON/OFF function.
In the ON phase, Q5 shorts the external capacitor
C
t
. Within the input voltage range 0 < V
in
< 750mV
the element realizes the transconductance func-
tion ; lower voltages are clamped by the D1/Q6
configuration.
For input voltages higher than 750mV, Q7 limits the
maximum output current at 1.5A peak.
In the turn-OFF mode, C
t
will be charged by the
controlled source I
2
which is proportional to the
input voltage, by this way, the output current de-
creases quasi linearly and the system stability is
reached.
During the flyback phase, the IC is disabled via the
sync. detector input ; this function with the limited
sink and source current together with the undervol-
tage turn-OFF and a chip temperature sensor en-
sure a complete protection of the IC.
In Figure 8 is shown the application diagram of the
TDA 8140, the few external component and the
automatic handling possibility ensures a lower ap-
plication cost versus the conventional approach
shown in Figure 4.
In Figure 9 is shown the currents and voltages
waveforms of the driver circuit of Figure 8, as to be
seen, the driving charge Ib
t
on
has been reduced
at minimum.
&
C
VOLTAGE
CONTROL
V < 7V
j
OVERTEMP.
PROTECTION
T < 150C
&
8
7
6
5
4
3
1
2
9
10 11 12
13 14 15 16
Q9
V1
R2
R1
INPUT
TRANSCONDUCTANCE
AMPLIFIER
V2
Q10
Q11
R5
D2
Q7
Q6
R4
D1
Q1
Q4
Q3
R3
Q8
R6
Q2
Q5
I
1
I
2
REF
IN
V
V = 750mV
OUTPUT
I
B
SENSE
INPUT
V
+
C C
PROTECTION
AND REMOTE
STANDBY INPUT
CONTROL
INPUT
SPECIAL
REMOTE
STANDBY
POWER GROUND
SENSE
GROUND
C
EXT
C
T
8
1
4
0
-0
9
.
EPS
Figure 7 : Block Diagram of the Integrated Horizontal Driver
TDA8140
7/10
2
8
1
3
5
4
7
I
C
I
D
I
B
V
i
+
V
CC
9 to 16
R
2W
47nF
1nF
YOKE
HORIZONTAL
TRANSFORMER
DEFLECTION CIRCUIT
100
F
220
F
27
4.7
0.15
TDA8140
DRIVING CIRCUIT
8
1
4
0
-1
0
.
EPS
Figure 8 : Integrated Horizontal Driver
81
40
-
1
1
.
T
I
F
Figure 9 : Signal Diagrams of the Driver Circuits
81
40
-
1
2.
T
I
F
TDA8140
8/10
The power dissipation on this application condition
is about 1.3W and Figures 10 and 11 show two
ways of heatsinking.
In the first case, a PCB copper area is used as a
heatsink L= 65mm while in the second case, the
device is soldered to an external heatsink ; in both
examples, the thermal resistance junction ambient
is 35C/W.
The presence of thermal shut-down circuit does
mean that the heatsink can have a smaller factor
of safety compared with that of a conventional
circuit.
If for any reason, the junction temperature in-
creases up to 150C, the thermal shut-down simply
switches off the device.
L
Copper Area 35
Thickness
8
1
4
0
-1
3
.
EP
S
Figure 10 : Example of Heatsink using
P.C. Board Copper (L = 65mm)
30m
m
81
40
-
1
4
.
E
P
S
Figure 11 : Example of an External Heatsink
TDA8140
9/10
16
1
8
I
a1
L
B
e
D
b
Z
e3
F
b1
E
9
P
M
D
I
P1
6
W
.
E
PS
PACKAGE MECHANICAL DATA
16 PINS - PLASTIC POWERDIP
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I
2
C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I
2
C Patent. Rights to use these components in a I
2
C system, is granted provided that the system conforms to
the I
2
C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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Dimensions
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
a1
0.51
0.020
B
0.85
1.4
0.033
0.055
b
0.5
0.020
b1
0.38
0.5
0.015
0.020
D
20
0.787
E
8.8
0.346
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
i
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
DI
P
1
6
P
W
.
T
B
L
TDA8140
10/10
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