Version 4.2

June 2000

1/43

TDA9111

LOW-COST I

C CONTROLLED DEFLECTION PROCESSOR

FOR MULTISYNC MONITOR

FEATURES
General

SYNC PROCESSOR (separate or composite)

12V SUPPLY VOLTAGE

8V REFERENCE VOLTAGE

HOR. LOCK/UNLOCK OUTPUT

HOR. & VERT. LOCK/UNLOCK INDICATION

READ/WRITE I

C INTERFACE

HORIZONTAL AND VERTICAL MOIRE

B+ REGULATOR

- Internal PWM generator for B+ current mode

step-up converter

- Switchable to step-down converter
- I

C adjustable B+ reference voltage

- Output pulses synchronized on horizontal

frequency

- Internal maximum current limitation.

Horizontal

Self-adaptative

Dual PLL concept

150kHz maximum frequency

X-Ray protection input

C controls: Horizontal duty-cycle, H-position,

horizontal size amplitude

Vertical

Vertical ramp generator

50 to 185Hz AGC loop

Geometry tracking with VPOS & VAMP

C controls:

VAMP, VPOS, S-CORR, C-CORR

DC breathing compensation

C Geometry corrections

Vertical parabola generator (Pin Cushion - E/W,
Keystone, Corner Correction)

Horizontal dynamic phase (Side Pin Balance &
Parallelogram)

Horizontal

and

vertical

dynamic

focus

(Horizontal Focus Amplitude, Horizontal Focus
Symmetry, Vertical Focus Amplitude)

DESCRIPTION

The TDA9111 is a monolithic integrated circuit as-
sembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.

The internal sync processor, combined with the
powerful geometry correction block, makes the
TDA9111 suitable for very high performance mon-
itors, using few external components.

The horizontal jitter level is very low. It is particu-
larly well-suited to high-end 15" and 17" monitors.

Combined with the ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x (On-
Screen Display controller), the TDA9111 allows
fully-I

C bus-controlled computer display monitors

to be built with a reduced number of external com-
ponents.

PIN CONNECTIONS

SHRINK32 (Plastic Package)

ORDER CODE: TDA9111

H/HVIN

VSYNCIN

HMOIRE/HLOCK

PLL2C

C0
R0

PLL1F

HPOSITION

HFOCUSCAP

FOCUS-OUT

HGND

HFLY

HREF

COMP

REGIN

SENSE

5V
SDA
SCL

BOUT
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
V

REF

VAGCCAP
VGND
VBREATH
B + GND

TABLE OF CONTENTS

2/43

PIN CONNECTIONS

......................................................................3

QUICK REFERENCE DATA

......................................................................4

BLOCK DIAGRAM

......................................................................5

ABSOLUTE MAXIMUM RATINGS

......................................................................6

THERMAL DATA

......................................................................6

SUPPLY AND REFERENCE VOLTAGES

......................................................................6

I2C READ/WRITE

......................................................................7

SYNC PROCESSOR

......................................................................7

HORIZONTAL SECTION

......................................................................8

VERTICAL SECTION

......................................................................10

DYNAMIC FOCUS SECTION

......................................................................11

GEOMETRY CONTROL SECTION

......................................................................12

MOIRE CANCELLATION SECTION

......................................................................13

B+ SECTION

......................................................................14

TYPICAL OUTPUT WAVEFORMS

......................................................................16

I2C BUS ADDRESS TABLE

......................................................................20

OPERATING DESCRIPTION

......................................................................23

GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2

C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.3

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5

Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.6

Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.7

IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.8

Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.9

Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1

Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2

PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3

PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4

Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.5

X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.6

Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.7

Horizontal Moir� Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1

Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2

I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3

Vertical Moir� . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4

Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.5

Geometric Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.6

E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.7

Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1

Step-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2

Step-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3

Step-up and Step-down Mode Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

INTERNAL SCHEMATICS

......................................................................35

PACKAGE MECHANICAL DATA

......................................................................42

TDA9111

3/43

PIN CONNECTIONS

Pin

Name

Fun ction

H/HVIN

TTL compatible Horizontal sync Input (separate or composite)

VSYNCIN

TTL compatible Vertical sync Input (for separated H&V)

HMOIRE/
HLOCK

Horizontal Moir� Output (to be connected to PLL2C through a resistor divider), HLock
Output

PLL2C

Second PLL Loop Filter

Horizontal Oscillator Capacitor

Horizontal Oscillator Resistor

PLL1F

First PLL Loop Filter

HPOSITIO N

Horizontal Position Filter (capacitor to be connected to HGND)

HFOCUS-
CAP

Horizontal Dynamic Focus Oscillator Capacitor

FOCUS OUT

Mixed Horizontal and Vertical Dynamic Focus Output

HGND

Horizontal Section Ground

HFLY

Horizontal Flyback Input (positive polarity)

HREF

Horizontal Section Reference Voltage (to be filtered)

COMP

B+ Error Amplifier Output for frequency compensation and gain setting

REGIN

Feedback Input of B+ control loop

SENSE

Sensing of external B+ switching transistor current, or switch for step-down converter

B+GND

Ground (related to B+ reference)

VBREATH

V Breathing Input Control (compensation of vertical amplitude against EHV variation)

VGND

Vertical Section Ground

VAGCCAP

Memory Capacitor for Automatic Gain Control in Vertical Ramp Generator

REF

Vertical Section Reference Voltage (to be filtered)

VCAP

Vertical Sawtooth Generator Capacitor

VOUT

Vertical Ramp Output (with frequency-independent amplitude and S or C Corrections
if any). It is mixed with vertical position voltage and vertical moir�.

EWOUT

Pin Cushion (E/W) Correction Parabola Output

XRAY

X-RAY protection input (with internal latch function)

HOUT

Horizontal Drive Output (open collector)

GND

General Ground

BOUT

B+ PWM Regulator Output

Supply Voltage(12V typ) (referenced to Pin 27)

SCL

C Clock Input

SDA

C Data Input

5V Supply Voltage

TDA9111

4/43

QUICK REFERENCE DATA

Parameter

Value

Unit

Any polarity on H Sync & V Sync inputs

YES

TTL or composite Syncs

YES

Sync on Green

Horizontal Frequency

15 to 150

kHz

Horizontal Autosync Range (for given R0 and C0. Can be easily increased by application)

1 to 4.5 f0

Control of free-running frequency

Frequency Generator for Burn-in

Control of H-Position through I

YES

Control for H-Duty Cycle through I

30 to 65

PLL1 Inhibition Possibility

Output for Horizontal Lock/Unlock

YES

Dual Polarity H-Drive Outputs

Vertical Frequency

35 to 200

Vertical Autosync Range (for 150nF on Pin 22 and 470nF on Pin 20)

50 to 185

Vertical S-Correction (adapted to normal or super flat tube), controlled through I

YES

Vertical C-Correction, controlled through I

YES

Control of Vertical Amplitude through I

YES

Control of Vertical Position through I

YES

Input for Vertical Amplitude compensation versus EHV

YES

E/W Correction Output (also known as Pin Cushion Output)

YES

Horizontal Size Adjustment through I

C control of E/W Output DC level

YES

Control of E/W (Pincushion) Adjustment through I

YES

Control of Keystone (Trapezo�d) Adjustment through I

YES

Control of Corner Adjustment through I

YES

Fully integrated Dynamic Horizontal Phase Control

YES

Control of Side Pin Balance through I

YES

Control of Parallelogram through I

YES

H/V composite Dynamic Focus Output

YES

Control of Horizontal Dynamic Focus Amplitude through I

YES

Control of Horizontal Dynamic Focus Symmetry through I

YES

Control of Vertical Dynamic Focus Amplitude through I

YES

Tracking of Geometric Corrections and of Vertical focus with Vertical Amplitude and Position

YES

Control of Horizontal and Vertical Moir� cancellations through I

YES

Optimisation of HMoir� frequency through I

YES

B+ Regulation, adjustable through I

YES

Stand-by function, disabling H and V scanning and B+

YES

X-Ray protection, disabling H scanning and B+

YES

Blanking Outputs

Fast I

C Read/Write

400

kHz

C indication of the presence of Syncs (biased from 5V alone)

YES

C indication of the polarity and Type of Syncs

YES

C indication of Lock/Unlock, for both Horizontal and Vertical sections

YES

TDA9111

6/43

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

SUPPLY AND REFERENCE VOLTAGES

Electrical Characteristics (V

= 12V, T

amb

= 25

�

Symbol

Parameter

Value

Unit

Supply Voltage (Pin 29)

13.5

Supply Voltage (Pin 32)

5.7

Max Voltage on

Pin 4
Pin 9
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pins 3, 10, 18, 23, 24, 25, 26, 28
Pins 1, 2
Pins 30, 31

4.0
5.5
6.4
8.0

V
V
V
V
V
V
V

VESD

ESD susceptibility

Human Body Model, 100pF Discharge

through 1.5k

EIAJ Norm, 200pF Discharge through 0

300

stg

Storage Temperature

-40, +150

�

Junction Temperature

+150

�

oper

Operating Temperature

0, +70

�

Symbol

Parameter

Value

Unit

th(j-a)

Max. Junction-Ambient Thermal Resistance

�

C/W

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

Supply Voltage

Pin 29

10.8

13.2

Supply Voltage

Pin 32

4.5

5.5

Supply Current

Pin 29

Supply Current

Pin 32

REF-H

Horizontal Reference Voltage

Pin 13, I = -2mA

7.6

8.2

8.8

REF-V

Vertical Reference Voltage

Pin 21, I = -2mA

7.6

8.2

8.8

REF-H

Max. Sourced Current on V

REF-H

Pin 13

REF-V

Max. Sourced Current on V

REF-V

Pin 21

TDA9111

7/43

C READ/WRITE

Electrical Characteristics (V

= 5V, T

amb

= 25

�

Note: 1

See also I

C Sub Address Table.

SYNC PROCESSOR

Operating Conditions (V

= 5V, V

= 12V, T

amb

= 25

�

Electrical Characteristics (V

= 5V, V

= 12V, T

amb

= 25

�

Note: 2

is the horizontal period.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

C PROCESSOR

(1)

Fscl

Maximum Clock Frequency

Pin 30

400

kHz

Tlow

Low period of the SCL Clock

Pin 30

1.3

�

Thigh

High period of the SCL Clock

Pin 30

0.6

�

Vinth

SDA and SCL Input Threshold

Pins 30, 31

2.2

VACK

Acknowledged Output Voltage on SDA
input with 3mA

Pin 31

0.4

C leak

Leakage current into SDA and SCL with
no logic supply

= 0

Pins 30, 31 = 5 V

�

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

HSVR

Voltage on H/HVIN Input

Pin 1

MinD

Minimum Horizontal Input Pulses Dura-
tion

Pin 1

0.7

�

Mduty

Maximum Horizontal Input Signal Duty
Cycle

Pin 1

VSVR

Voltage on VSYNCIN

Pin 2

VSW

Minimum Vertical Sync Pulse Width

Pin 2

�

VSmD

Maximum Vertical Sync Input Duty Cycle Pin 2

VextM

Maximum Vertical Sync Width on TTL H/
Vcomposite

Pin 1

750

�

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

VINTH

Horizontal and Vertical Input Logic Level
(Pins 1, 2)

High Level
Low Level

2.2

0.8

V
V

RIN

Horizontal and Vertical Pull-Up Resistor

Pins 1, 2

250

VoutT

Extracted Vsync Integration Time (% of
T

) on H/VComposite

(2)

C0 = 820pF

TDA9111

8/43

HORIZONTAL SECTION

Operating Conditions

Electrical Characteristics (V

= 12V, T

amb

= 25

�

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

VCO

0max

Max Current from Pin 6

Pin 6

1.5

F(max.)

Maximum Oscillator Frequency

150

kHz

OUTPUT SECTION

I12m

Maximum Input Peak Current

Pin 12

HOI

Horizontal Drive Output Maximum Cur-
rent

Pin 26, Sunk current

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

1st PLL SECTION

HpoIT

Delay Time for detecting polarity
change

(3)

Pin 1

0.75

Vvco

VCO Control Voltage (Pin 7)

REF-H

= 8.2V

= f

(Max.)

1.4
6.4

V
V

Vcog

VCO Gain (Pin 7)

= 6.49k

= 820pF

Tbd

15.9

Tbd

kHz/V

Hph

Horizontal Phase Adjustment

(4)

% of Horizontal
Period

�

Vbmi

Vbtyp

Vbmax

Horizontal Phase Setting Value (Pin 8)

(4)

Minimum Value
Typical Value
Maximum Value

Sub-Address 01
Byte

x1111111

Byte

x1000000

Byte

x0000000

2.9
3.5
4.2

V
V
V

IPII1U

IPII1L

PLL1 Filter Charge Current

PLL1 is Unlocked
PLL1 is Locked

�

140

�

Free Running Frequency

= 6.49k

, C

= 820pF

Tbd

22.8

Tbd

kHz

dfo/dT

Free Running Frequency Thermal Drift

(5)

Not including external
componant drift

-150

ppm/C

PLL1 Capture Range

fH(Min.)
fH(Max.)

(6)

+0.5

4.5f

kHz
kHz

HUnlock

DC level pin 3 when PLL1 is
unlocked

Sub-address 02
1xxx xxxx
0000 0000
0111 1111

(7)

0.3

2.75

V
V
V

TDA9111

9/43

Note: 3

This delay is necessary to avoid a wrong detection of polarity change in the case of a composite sync.

See Figure 10 for explanation of reference phase.

These parameters are not tested on each unit. They are measured during our internal qualification.

A larger range may be obtained by application.

When at 0xxx xxxx, (HMoir�/HLock not selected), Pin 3 is a DAC with 0.3...2.75V range. When at 1xxx xxxx
(HMoir�/HLock selected) and PLL1 is locked, Pin 3 provides the waveform for HMoir�. See also Moir�
section.

Hjit = 10

x(Standard deviation/Horizontal period).

Duty Cycle is the ratio between the output transistor OFF time and the period. The scanning transistor is
controlled OFF when the output transistor is OFF.

10 Initial Condition for Safe Start Up.

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth

Flyback Input Threshold Voltage (Pin 12)

0.65

0.75

Hjit

Horizontal Jitter

(8)

At 31.4kHz

ppm

HDmin

HDmax

Horizontal Drive Output Duty-Cycle (Pin
26)

(9)

Sub-Address 00
Byte x1111111
Byte x0000000

(10)

30
65

%
%

XRAYth

X-RAY Protection Input Threshold Volt-
age,

Pin 25, (see fig. 14)

7.6

8.2

8.8

Vphi2

Internal Clamping Levels on 2nd PLL
Loop Filter (Pin 4)

Low Level
High Level

1.6
4.2

V
V

VSCinh

Inhibition threshold (The condition V

VSCinh will stop H-Out, V-Out, B-Out and
reset X-RAY)

Pin 29

7.5

HDvd

Horizontal Drive Output (low level)

Pin 26, I

OUT

= 30mA

0.4

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

TDA9111

10/43

VERTICAL SECTION

Operating Conditions

Electrical Characteristics (V

= 12V, T

amb

= 25

�

Note: 11 These parameters are not tested on each unit. They are measured during our internal qualification procedure.

Note: 12 Set Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction

inhibited), to obtain a vertical sawtooth with linear shape.

Note: 13 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single

capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude.

Note: 14 When not used, the DC breathing control pin must be connected to 12V.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

LOAD

Minimum Load for less than 1% Vertical
Amplitude Drift

Pin 20

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

VRB

Voltage at Ramp Bottom Point

Pin 22

2.1

VRT

Voltage at Ramp Top Point (with Sync)

Pin 22

5.1

VRTF

Voltage at Ramp Top Point (without
Sync)

Pin 22

VRT-

0.1

VSTD

Vertical Sawtooth Discharge Time

Pin 22, C

= 150nF

�

VFRF

Vertical Free Running Frequency

(12)

Pin 22, C

= 150nF

100

ASFR

AUTO-SYNC Frequency

(13)

= 150nF

�

185

RAFD

Ramp Amplitude Drift Versus Frequency
at Maximum Vertical Amplitude

(11)

= 150nF

50Hz< f < 185Hz

200

ppm/

Rlin

Ramp Linearity on Pin 22

(12)

2.5V < V

< 4.5V

0.5

VPOS

Vertical Position Adjustment Voltage (Pin
23 - VOUT mean value)

Sub Address 06
Byte 00000000
Byte 01000000
Byte 01111111

Tbd

3.2
3.6
4.0

Tbd

V
V
V

VOR

Vertical Output Voltage
(peak-to-peak on Pin 23)

Sub Address 05
Byte 10000000
Byte 11000000
Byte 11111111

Tbd

2.15

3.0
3.9

Tbd

V
V
V

VOI

Vertical Output Maximum Current
(Pin 23)

�

dVS

Max Vertical S-Correction Amplitude (TV
is the vertical period)
(0xxxxxxx inhibits S-CORR
11111111 gives max S-CORR)

Sub Address 07
Byte 11111111

V/V

at TV/4

V/V

at 3TV/4

-3.5

+3.5

%
%

Ccorr

Vertical C-Corr Amplitude
(0xxxxxxx inhibits C-CORR)

Sub Address 08

V/V

at TV/2

Byte 10000000
Byte 11000000
Byte 11111111

-3

%
%
%

BRRANG

DC Breathing Control Range

(14)

BRADj

Vertical Output Variation versus DC
Breathing Control (Pin 23)

> V

REF-V

1V<V

REF-V

-2.5

%/V
%/V

TDA9111

11/43

DYNAMIC FOCUS SECTION

Electrical Characteristics (V

= 12V, T

amb

= 25

�

Note: 15 S and C correction are inhibited to obtain a linear vertical sawtooth.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

HORIZONTAL DYNAMIC FOCUS FUNCTION (seeFigure 15 on page 29)

HDFst

Horizontal Dynamic Focus Sawtooth
Minimum Level
Maximum Level

Pin 9, capacitor on HFO-
CUSCAP and
C0 = 820pF, T

= 20

�

2.2
4.9

V
V

HDFdis

Horizontal Dynamic Focus Sawtooth Dis-
charge Width

Triggered by HDFstart

400

HDFstart

Internal Phase Advance versus HFLY
middle
(Independent of frequency)

�

HDFDC

Bottom DC Output Level

LOAD

= 10k

Pin 10

2.1

TDFHD

DC Output Voltage Thermal Drift

(11)

200

ppm/C

HDFamp

Horizontal Dynamic Focus
Amplitude

Max Byte
Typ Byte
Max Byte

Sub-Address 03,
Pin 10, fH = 50kHz,
Symmetric Wave Form
x1111111
x1000000
x0000000

1.5
3.5

HDFKeyst

Horizontal Dynamic FocusSymmetry
(For time reference, see Figure 15 )
Advance for Byte
Delay for Byte

Subaddress 04

x1111111 (decimal 127)
x0000000 (decimal 0)

16
16

%
%

VERTICAL DYNAMIC FOCUS FUNCTION (see Figu re 1)

AMPVDF

Vertical Dynamic Focus Parabola (added
to horizontal) Amplitude with VAMP and
VPOS Typical

Sub-Address 0F
Min Byte x0000000
Typ Byte x1000000
Max Byte x1111111

0.5

VDFAMP

Parabola Amplitude Function of VAMP
(tracking between VAMP and VDF) with
VPOS Typ. (seeFigure 1 on page 15 and

(15)

)

Sub-Address 05
Byte

x0000000

Byte

x1000000

Byte

x1111111

0.6

1.5

VHDFKeyt

Parabola Asymmetry Function of VPOS
Control (tracking between VPOS and
VDF) with VAMP Max.
B/A Ratio
A/B Ratio

Sub-Address 06

Byte

x0000000

Byte

x1111111

0.52
0.52

TDA9111

12/43

GEOMETRY CONTROL SECTION

Electrical Characteristics (V

= 12V, T

amb

= 25

�

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

SYMMETRIC CONTROL THROUGH E/W OUTPUT (see Figure 2 on page 15 and Figu re 4 on page 15)

VEWM

Maximum E/W Output Voltage

Pin 24

6.5

VEWm

Minimum E/W Output Voltage

Pin 24

1.8

For control of Horizontal size. DC Output
Voltage with E/W, corner and Keystone
inhibited

Pin 24, see Figure 2
Subaddress 11
Byte x0000000
Byte x1000000
Byte x1111111

3.25

4.2

V
V
V

TDEW

DC Output Voltage Thermal Drift

See

(16)

100

ppm/C

EWpara

Parabola Amplitude with Max. VAMP,
Typ. VPOS, Keystone and Corner inhibit-
ed

Subaddress 0A
Byte 11111111
Byte 11000000
Byte 10000000

1.4
0.7

EWtrack

Parabola Amplitude Function of VAMP
Control (tracking between VAMP and E/
W) with Typ. VPOS, Typ. E/W Amplitude,
corner and Keystone inhibited

(17)

Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111

0.2
0.4
0.7

KeyAdj

Keystone Adjustment Capability with
Typ. VPOS, E/W inhibited, Corner inhibit-
ed and Max. Vert. Amplitude (see

(17)

and

Figure 4)

Subaddress 09
Byte 10000000
Byte 11111111

0.4
0.4

EW Corner

Corner Adjustment Capability with Typ.
VPOS, E/W inhibited, Keystone inhibited
and Max. Vertical Amplitude

Subaddress 10
Byte 11111111
Byte 11000000
Byte 10000000

1.25

KeyTrack

Intrinsic Keystone Function of VPOS
Control (tracking between VPOS and E/
W) with Max. E/W Amplitude and Max.
Vertical Amplitude, Corner inhibited
B/A Ratio
A/B Ratio

Subaddress 06

Byte 00000000
Byte 01111111

0.52
0.52

ASYMMETRIC CONTROL THROUGH INTERNAL DYNAMIC HORIZONTAL PHASE MODULATION (see Figu re 3)

SPBpara

Side Pin Balance Parabola Amplitude
(Figure 3) with Max. VAMP, Typ. VPOS
and Parallelogram inhibited

(17 & 18)

Subaddress 0D
Byte 11111111
Byte 10000000

+2.8

-2.8

SPBtrack

Side Pin Balance Parabola Amplitude
function of VAMP Control (tracking be-
tween VAMP and SPB) with Max. SPB,
Typ. VPOS and Parallelogram inhibited

(17 & 18)

Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111

1.8
2.8

ParAdj

Parallelogram Adjustment Capability with
Max. VAMP, Typ. VPOS and SPB inhibit-
ed

(17 & 18)

Subaddress 0E
Byte 11111111
Byte 11000000

+2.8

-2.8

Partrack

Intrinsic Parallelogram Function of VPOS
Control (tracking between VPOS and
DHPC) with Max. VAMP, Max. SPB and
Parallelogram inhibited

(17 & 18)

B/A Ratio
A/B Ratio

Subaddress 06

Byte x0000000
Byte x1111111

0.52
0.52

TDA9111

13/43

Note: 16 These parameters are not tested on each unit. They are measured during our internal qualification procedure.

Note: 17 With Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction

inhibited), the sawtooth has a linear shape.

MOIRE CANCELLATION SECTION

Electrical Characteristics (

= 12V, T

amb

= 25

�

Note: 18 T

is the horizontal period.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

HORIZONTAL AND VERTICAL MOIRE

MOIRE

Minimum Output Resistor to GND

Pin 3

4.7

DacOut

DC Voltage pin 3
DAC configuration

MOIRE

= 4.7k

sub-address 02
Byte 00000000
Byte 01000000
Byte 01111111

0.3
1.1

2.75

V
V
V

HMOIRE

Moir� pulse (See also Hunlock in 1st PLL
section)
H Frequency: Locked

MOIRE

= 4.7k

Sub-address 02
Byte 10000000
Byte 11000000
Byte 11111111

0.8
2.2

HMOIRE

HMoir� pulse period pin 3
H Frequency: Locked

Sub-address II:
0xxx xxxx
1xxx xxxx

4.T

2.T

VMOIRE

Vertical Moir�
(measured on VOUT: Pin 23)

Sub-address 0C
Byte 11111111

TDA9111

14/43

B+ SECTION

Operating Conditions

Electrical Characteristics (V

= 12V, T

amb

= 25

�

Note: 19 These parameters are not tested on each unit. They are measured during our internal qualification procedure

which includes characterization on batches coming from corners of our process and also temperature
characterization.

Note: 20 To make soft start possible, 0.5mA are sunk when B+ is disabled.

Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

FeedRes

Minimum Feedback Resistor

Resistor between Pins 15
and 14

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

OLG

Error Amplifier Open Loop Gain

At low frequency

(19)

UGBW

Unity Gain Bandwidth

See

(19)

MHz

IRI

Feedback Input Bias Current

Current sourced by Pin 15
(PNP base)

0.2

�

EAOI

Error Amplifier Output Current

Current sourced by Pin 14
Current sunk by
Pin 14

(20)

1.4

CSG

Current Sense Input Voltage Gain

Pin 16

MCEth

Max Current Sense Input Threshold Volt-
age

Pin 16

1.3

ISI

Current Sense Input Bias Current

Current sunk by Pin 16
(PNP base)

�

Tonmax

Maximum ON Time of the external power
transistor

% of horizontal period,
f

= 27kHz)

(21)

100

B+OSV

B+Output Saturation Voltage

with I

= 10mA

0.25

REF

Internal Reference Voltage

On error amp (+)
input Subaddress OB:
Byte 1000000

REFADJ

Internal Reference Voltage Adjustment
Range

Byte 01111111
Byte 00000000

+20

-20

%
%

PWMSEL

Threshold for step-up/step-down selec-
tion (step-up configuration if V

< PWM-

SEL)

Pin 16

FB+

Fall Time

Pin 28

100

TDA9111

20/43

C BUS ADDRESS TABLE

Slave Address (8C): Write Mode

Sub Address Definition

Slave Address (8D): Read Mode: No sub address needed.

Horizontal Drive Selection/Horizontal Duty Cycle

X-ray Reset/Horizontal Position

Horizontal Moir�/H Lock

Sync. Priority/Horizontal Focus Amplitude

Refresh/Horizontal Focus Symmetry

Vertical Ramp Amplitude

Vertical Position Adjustment

S Correction

C Correction

E/W Keystone

E/W Amplitude

B+ Reference Adjustment

Vertical Moir�

Side Pin Balance

Parallelogram

Vertical Dynamic Focus Amplitude

E/W Corner

H. Moir� Frequency/Horizontal Size Amplitude

TDA9111

21/43

C BUS ADDRESS TABLE (continued)

WRITE MODE

HDrive

0, off

[1], on

Horizontal Duty Cycle

[0]

Xray

1, reset

[0]

Horizontal Phase Adjustment

[1]

[0]

HMoir�/HLock

1, on

[0], off

Horizontal Moir� Amplitude

[0]

Sync

0, Comp

[1], Sep

Horizon tal Focus Amplitude

[1]

[0]

Detect

Refresh

[0], off

Horizontal Focus Symmetry

[1]

[0]

Vramp

0, off

[1], on

Vertical Ramp Amplitu de Adjustment

[1]

[0]

Test V

1, on

[0], off

Vertical Position Adjustment

[1]

[0]

S Select

1, on

[0]

S Correction

[1]

[0]

C Select

1, on

[0]

C Correction

[1]

[0]

E/W Key

0, off

[1]

E/W Keystone

[1]

[0]

E/W Sel

0, off

[1]

E/W Amplitude

[1]

[0]

Test H

1, on

[0], off

B + Reference Adjustment

[1]

[0]

V. Moir�

1, on

[0]

Vertical Moir� Amplitude

[0]

SPB Sel

0, off

[1]

Side Pin Balance

[1]

[0]

Parallelo

0, off

[1]

Parallelogram

[1]

[0]

TDA9111

23/43

OPERATING DESCRIPTION

1 GENERAL CONSIDERATIONS

1.1 Power Supply

The typical values of the power supply voltages
V

and V

are 12 V and 5 V respectively. Opti-

mum operation is obtained for V

between 10.8

and 13.2 V and V

between 4.5 and 5.5 V.

In order to avoid erratic operation of the circuit dur-
ing the transient phase of VCC switching on, or off,
the value of V

is monitored: if V

is less than

7.5 V typ., the outputs of the circuit are inhibited.

Similarly, before V

reaches 4 V, all the I

C reg-

ister are reset to their default value (see I

C Con-

trol Table).

In order to have very good power supply rejection,
the circuit is internally supplied by several voltage
references (typ. value: 8.2 V). Two of these volt-
age references are externally accessible, one for
the vertical and one for the horizontal part. They
can be used to bias external circuitry (if I

LOAD

less than 5 mA). It is necessary to filter the voltage
references by external capacitors connected to
ground, in order to minimize the noise and conse-
quently the "jitter" on vertical and horizontal output
signals.

1.2 I

C Control

TDA9111 belongs to the I

C controlled device

family. Instead of being controlled by DC voltages
on dedicated control pins, each adjustment can be
done via the I

C Interface.

The I

C bus is a serial bus with a clock and a data

input. The general function and the bus protocol
are specified in the Philips-bus data sheets.

The inputs (Data and Clock) are comparators with
a 2.2 V threshold at 5 V supply. Spikes of up to 50
ns are filtered by an integrator and the maximum
clock speed is limited to 400 kHz.

The data line (SDA) can be used bidirectionally. In
read-mode the IC sends reply information
(1 byte) to the micro-processor.

The bus protocol prescribes a full-byte transmis-
sion in all cases. The first byte after the start con-
dition is used to transmit the IC-address (hexa 8C
for write, 8D for read).

1.3 Write Mode

In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controls to affect) and the third byte the corre-
sponding data byte. It is possible to send more
than one data byte to the IC. If after the third byte

no stop or start condition is detected, the circuit in-
crements automatically by one the momentary
subaddress in the subaddress counter (auto-incre-
ment mode). So it is possible to transmit immedi-
ately the following data bytes without sending the
IC address or subaddress. This can be useful to
reinitialize all the controls very quickly (flash man-
ner). This procedure can be finished by a stop con-
dition.

The circuit has 18 adjustment capabilities: 3 for the
horizontal part, 4 for the vertical, 3 for the
E/W correction, 2 for the dynamic horizontal phase
control, 2 for the vertical and horizontal Moir� op-
tions, 3 for the horizontal and the vertical dynamic
focus and 1 for the B+ reference adjustment.

18 bits are also dedicated to several controls (ON/
OFF, Horizontal Forced Frequency, Sync Priority,
Detection Refresh and XRAY reset).

1.4 Read Mode

During the read mode the second byte transmits
the reply information.

The reply byte contains the horizontal and vertical
lock/unlock status, the XRAY activation status,
and the horizontal and vertical polarity detection. It
also contains the sync detection status which is
used by the MCU to assign the sync priority. A
stop condition always stops all the activities of the
bus decoder and switches to high impedance both
the data and clock line (SDA and SCL).

See I

C subaddress and control tables.

1.5 Sync Processor

The internal sync processor allows the TDA9111
to accept:

� separated horizontal & vertical TTL-compatible

sync signal

� composite horizontal & vertical TTL-compatible

sync signal

1.6 Sync Identification Status

The MCU can read (address read mode: 8D) the
status register via the I

C bus, and then select the

sync priority depending on this status.

Among other data this register indicates the pres-
ence of sync pulses on H/HVIN, VSYNCIN and
(when 12 V is supplied) whether a Vext has been
extracted from H/HVIN. Both horizontal and verti-
cal sync are detected even if only 5 V is supplied.

TDA9111

24/43

In order to choose the right sync priority the MCU
may proceed as follows (see I

C Address Table):

� refresh the status register,

� wait at least for 20ms (Max. vertical period),

� read this status register.

Sync priority choice should be :

Of course, when the choice is made, we can re-
fresh the sync detections and verify that the ex-
tracted Vsync is present and that no sync type
change has occurred. The sync processor also
gives sync polarity information.

1.7 IC status

The IC can inform the MCU about the 1st horizon-
tal PLL and vertical section status (locked or not)
and about the XRAY protection (activated or
not).Resetting the XRAY internal latch can be
done either by decreasing the V

supply or di-

rectly resetting it via the I

C interface.

1.8 Sync Inputs

Both H/HVIN and VSYNCIN inputs are TTL com-
patible triggers with hysteresis to avoid erratic de-
tection. Both inputs include a pull up resistor con-
nected to V

1.9 Sync Processor Output

The sync processor indicates on the D8 bit of the
status register whether 1st PLL is locked to an in-
coming horizontal sync. Its level goes to low when
locked. This information is also available on pin 3 if
sub-address 02 D8 is equal to 1. When PLL1 is un-
locked, pin 3 output voltage becomes greater than
6V. When it is locked, the HMoir� waveform is
available on pin 3 (max voltage: 3V).

2 HORIZONTAL PART

2.1 Internal Input Conditions

A digital signal (horizontal sync pulse or TTL com-
posite) is sent by the sync processor to the hori-
zontal input. It may be positive or negative (see
Figure 5).

Using internal integration, both signals are recog-
nized if Z/T < 25%. Synchronization occurs on the
leading edge of the internal sync signal.

The minimum value of Z is 0.7

�

Another integration is able to extract the vertical
pulse from composite sync if the duty cycle is high-
er than 25% (typically d = 35%),
(see Figure 6).

Figure 5.

Figure 6.

Vextd

H/V

det

Sync

priority

Subaddress

03 (D8)

Comment

Sync type

Yes

Separated H&V

Yes

Composite TTL

H&V

CSync

Integ.

VSyn

TDA9111

25/43

The last feature performed is the removal of these
equalization pulses which fall in the middle of a
line, to avoid parasitic pulses on the phase compa-
rator (which would be disturbed by missing or ex-
traneous pulses). This last feature is switched on/
off by sub-address 0F D8. By default [0], equaliza-
tion pulses will not be removed.

2.2 PLL1

The PLL1 consists of a phase comparator, an ex-
ternal filter and a voltage-controlled oscillator
(VCO).The phase comparator is a "phase/frequen-
cy" type designed in CMOS technology. This kind
of phase detector avoids locking on wrong fre-
quencies. It is followed by a "charge pump", com-
posed of two current sources : sunk and sourced
(typically I =1 mA when locked and I = 140

�

when unlocked). This difference between lock/un-
lock allows smooth catching of the horizontal fre-
quency by PLL1. This effect is reinforced by an in-
ternal original slow down system when PLL1 is
locked, avoiding the horizontal frequency chang-
ing too quickly. The dynamic behavior of PLL1 is
fixed by an external filter which integrates the cur-

rent of the charge pump. A "CRC" filter is generally
used (see Figure 7 on page 25).

Figure 7.

The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase compa-
rator. Inhibition is obtained by stopping high and
low signals at the input of the charge pump block
(see Figure 8 on page 25).

Figure 8.

PLL1F

1.8k

10nF

Extracted

Lock/Unlock
Status

VSync

PLL

INHIBITION

HPOSITION

PHASE
ADJUST

Low

High

LOCKDET

COMP1

CHARGE
PUMP

PLL1F

VCO

OSC

HPOS
Adj.

Extracted

VSync

INPUT

INTERFACE

H/HVIN

TDA9111

26/43

Figure 9.

The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current propor-
tional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6 V and 6.4 V.

The control voltage of the VCO is between 1.4 V
and 6.4 V (see Figure 9). The theoretical frequen-
cy range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on the filter lowest
value.

The sync frequency must always be higher than
the free running frequency. For example, when us-
ing a sync range between 25 kHz and 100 kHz,
the suggested free running frequency is 22 kHz.

PLL1 ensures the coincidence between the lead-
ing edge of the sync signal and a phase reference
REF1 obtained by comparison between the saw-
tooth of the VCO and an internal DC voltage Vb.
Vb is I

C adjustable between 2.9 V and 4.2 V (cor-

responding to

�

10 %) (see Figure 10).

The TDA9111 also includes a Lock/Unlock identi-
fication block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal. This information is available through

C, and also on pin 3 if HLock/Unlock option has

been set through Subaddress 02,D8.

Figure 10. PLL1 Timing Diagram

FLIP FLOP

0.875T

1.6V

6.4V

4 I

(1.4V<V

<6.4V)

PLL1F

(Loop Filter)

1.6V

6.4V

The PLL1 ensures the exact coincidence between the
signal phase REF and HSYNC. A

�

10% T

phase

adjustment is possible around the 3.5V point.

Phase REF1 is obtained by comparison between

the sawtooth and a DC voltage adjustable between
2.9 V and 4.2 V.

H O

Sawtooth

7/8 TH

1/8 TH

6.4V

Ref. for H Position

(2.9V<Vb<4.2V)

1.6V

REF1

HSync

TDA9111

27/43

2.3 PLL2

PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into account the saturation time
Ts (see Figure 11)

Figure 11. PLL2 Timing Diagram

The phase comparator of PLL2 is followed by a
charge pump (typical output current: 0.5 mA).

The flyback input consists of an NPN transistor.

The input current must be limited to less than 5 mA
(see Figure 12).

Figure 12. Flyback Input Electrical Diagram

The duty cycle is adjustable through I

C from 30 %

to 65 %. For a safe start-up operation, the initial
duty cycle (after power-on reset) is 65% in order to
avoid having too long a conduction period of the
horizontal scanning transistor.

The maximum storage time (Ts Max.) is (0.44T

FLY

/2). Typically, T

FLY

is around 20 %, at

maximum frequency, which means that Ts max is
around 34 % of T

2.4 Output Section

The H-drive signal is sent to the output through a
shaping stage which also controls the H-drive duty
cycle (I

C adjustable) (see Figure 11). In order to

secure the scanning power part operation, the out-
put is inhibited in the following cases:

� when V

or V

are too low

� when the XRAY protection is activated

� during the Horizontal flyback

� when the HDrive I

C bit control is off.

The output stage consists of a NPN bipolar tran-
sistor. Only the collector is accessible (see
Figure 13).

Figure 13.

This output stage is intended for "reverse" base
control, where setting the output NPN in off-state
will control the power scanning transistor in off-
state.

The maximum output current is 30mA, and the
corresponding voltage drop of the output V

CEsat

0.4V Max.

Obviously the power scanning transistor cannot be
directly driven by the integrated circuit. An inter-
face has to be added between the circuit and the
power transistor either of bipolar or MOS type.

2.5 X-RAY Protection

The X-Ray protection is activated by application of
a high level on the X-Ray input (more than 8.2V on
Pin 25). It inhibits the H-Drive and B+ outputs.

This activation is internally delayed by 2 lines to
avoid erratic detection when short parasitics are
present .

HOsc

Sawtooth

7/8T

1/8 T

Flyback

Internally
shaped Flyback

HDrive

Duty Cycle

1.6V

4.0V

6.4V

500

HFLY

GND 0V

20k

TDA9111

29/43

Figure 15. Phase of HFocus Parabola

2.7 Horizontal Moir� Output

The Horizontal Moir� output is intended to correct
a beat between the horizontal video pixel period
and the CRT pixel width.

The Moir� signal is a combination of the horizontal
and vertical frequency signals.

To achieve a Moir� cancellation, the Moir� output
has to be connected so as to modulate the hori-
zontal position. We recommend introducing this
"Horizontal Controlled Jitter" on the ground side of
PLL2 capacitor where this "controlled jitter" will di-
rectly affect the horizontal position.

The amplitude of the signal is I

C adjustable. The

H-Moir� frequency can be chosen via the I

When sub-address 11 D8=0, Fh is divided by 4.
This is recommended for separate scanning and
EHV. When D8=1, Fh is divided by 2, which gives
a better aspect in the case of common scanning
and EHV. The H-Moir� output is combined with the
PLL1 horizontal unlock output.

If HMoir�/HLock is selected:

� when PLL1 is unlocked, pin 3 output voltage

goes above 6V.

� when PLL1 is locked, the HMoir� signal (up to

2.2V peak) is present on pin 3.

If HMoir�/HLock is not selected, pin 3 can be used
as a 0....2.5V DAC.

127

0.16T

0.475T

127

C Code

(decimal)

0.6

�

0.6

�

0.4

�

Flyback pulse

H Focus sawtooth

H Focus parabola

TDA9111

30/43

3 VERTICAL PART

3.1 Function

When the synchronization pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor C

OSC

= 150nF,

the typical free running frequency is 100Hz.

The typical free running frequency can be calculat-
ed by:

fo(Hz) = 1.5

-5 .

A negative or positive TTL level pulse applied on
Pin 2 (VSYNC) as well as a TTL composite sync
on Pin 1 can synchronize the ramp in the range
[fmin, fmax] (See Figure 16 on page 31). This fre-
quency range depends on the external capacitor
connected on Pin 22. A 150nF (

�

5%) capacitor is

recommended for 50Hz to 185Hz applications.

If a synchronization pulse is applied, the internal
oscillator is synchronized immediately but with
wrong amplitude. An internal correction then ad-
justs it in less than half a second. The top value of
the ramp (Pin 22) is sampled on the AGC capaci-
tor (Pin 20) at each clock pulse and a transcon-
ductance amplifier modifies the charge current of
the capacitor so as to adjust the amplitude to the
right value.

The Read Status register provides the vertical
Lock-Unlock and the vertical sync polarity informa-
tion.

We recommend to use an AGC capacitor with low
leakage current. A value lower than 100nA is man-
datory.

A good stability of the internal closed loop is
reached with a 470nF

�

5% capacitor value on Pin

20 (VAGC).

3.2 I

C Control Adjustments

S and C correction shapes can then be added to
this ramp. These frequency-independent S and C
corrections are generated internally. Their ampli-
tudes are adjustable by their respective I

C regis-

ters. They can also be inhibited by their select bits.

Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.

The adjusted ramp is available on Pin 23 (V

OUT

) to

drive an external power stage.

The gain of this stage can be adjusted (

�

25%) de-

pending on its register value.

The mean value of this ramp is driven by its own
I

C register (vertical position). Its value is

VPOS = 7/16

REF-V

�

400mV.

Usually V

OUT

is sent through a resistive divider to

the inverting input of the booster. Since VPOS de-
rives from V

REF-V

, the bias voltage sent to the non-

inverting input of the booster should also derive
from V

REF-V

to optimize the accuracy (see Appli-

cation Diagram).

3.3 Vertical Moir�

By using the vertical Moir�, VPOS can be modulat-
ed from frame to frame. This function is intended
to cancel the fringes which appear when the line to
line interval is very close to the CRT vertical pitch.

The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D8.

OSC

TDA9111

31/43

Figure 16. AGC Loop Block Diagram

3.4 Basic Equations

In first approximation, the amplitude of the ramp
on Pin 23 (VOUT) is:

OUT

- VPOS = (V

OSC

- V

DCMID

)

(1 + 0.3 (V

AMP

))

where:

DCMID

= 7/16 V

REF

(middle value of the ramp

on Pin 22, typically 3.6V)

OSC

= V

(ramp with fixed amplitude)

AMP

= -1 for minimum vertical amplitude regis-

ter value and +1 for maximum

VPOS is calculated by:

VPOS = V

DCMID

+ 0.4 V

where V

= -1 for minimum vertical position reg-

ister value and +1 for maximum.

The current available on Pin 22 is:

OSC

REF

x C

OSC

x f

where C

OSC

= capacitor connected on Pin 22 and

f = synchronization frequency.

3.5 Geometric Corrections

The principle is represented in Figure 17 on
page 32.

Starting from the vertical ramp, a parabola-shaped
current is generated for E/W correction (also
known as Pin Cushion correction), dynamic hori-
zontal phase control correction, and vertical dy-
namic focus correction.

The parabola generator is made by an analog mul-
tiplier, the output current of which is equal to:

DI = k

OUT

- V

DCMID

)

where V

OUT

is the vertical output ramp (typically

between 2 and 5V) and V

DCMID

is 3.6V

(for V

REF-V

= 8.2V). The VOUT sawtooth is typical-

ly centered on 3.6V. By changing the vertical posi-
tion, the sawtooth shifts by

�

0.4V.

To provide good screen geometry for any end user
adjustment, the TDA9111 has the "geometry
tracking" feature which automatically adapts the
parabola shape, depending on the vertical position
and size.

3
8

TDA9111

32/43

Due to the large output stage voltage range (E/W
Pin Cushion, Keystone, E/W Corner), the combi-
nation of the tracking function, maximum

vertical amplitude, maximum or minimum vertical
position and maximum gain on the DAC control
may lead to output stage saturation. This must be
avoided by limiting the output voltage with appro-
priate I

C register values.

For the E/W part and the dynamic horizontal
phase control part, a sawtooth-shaped differential
current in the following form is generated:

I' = k'

(

OUT -

DCMID

)

Then

I and

I' are added and converted into volt-

age for the E/W part.

Each of the three E/W components or the two dy-
namic horizontal phase control components may
be inhibited by their own I

C select bit.

The E/W parabola is available on Pin 24 via an
emitter follower output stage which has to be bi-
ased by an external resistor (10

to ground).

Since stable in temperature, the device can be DC
coupled with external circuitry (mandatory to ob-
tain H Size control).

The vertical dynamic focus is combined with the
horizontal focus on Pin 10.

The dynamic horizontal phase control drives inter-
nally the H-position, moving the HFLY position on
the horizontal sawtooth in the range of

�

2.8 %T

both for side pin balance and parallelogram.

Figure 17. Geometric Corrections Principle

3.6 E/W

EWOUT = EW

+ K1

(

OUT -

DCMID

) +

(

OUT -

DCMID

)

+ K3

(

OUT -

DCMID

)

K1 is adjustable by the keystone I

C register.

K2 is adjustable by the E/W amplitude I

C register.

K3 is adjustable by the E/W corner I

C register.

TDA9111

33/43

3.7 Dynamic Horizontal Phase Control

OUT

= K4 (V

OUT -

DCMID

) + K5 (V

OUT -

DCMID

)

K4 is adjustable by the parallelogram I

C register.

K5 is adjustable by the side pin balance I

C regis-

ter.

4 DC/DC CONVERTER PART

This unit controls the switch-mode DC/DC con-
verter. It converts a DC constant voltage into the
B+ voltage (roughly proportional to the horizontal
frequency) necessary for the horizontal scanning.

This DC/DC converter can be configured either in
step-up or step-down mode. In both cases it oper-
ates very similarly to the well known UC3842.

4.1 Step-up Mode

Operating Description

� The power MOS is switched ON during the fly-

back (at the beginning of the positive slope of the
horizontal focus sawtooth).

� The power MOS is switched OFF when its cur-

rent reaches a predetermined value. For this pur-
pose, a sense resistor is inserted in its source.
The voltage on this resistor is sent to Pin16
(I

SENSE

� The feedback (coming either from the EHV or

from the flyback) is divided to a voltage close to
5.0V and compared to the internal 5.0V refer-
ence (I

VREF

). The difference is amplified by an

error amplifier, the output of which controls the
power MOS switch-off current.

Main Features

� Switching synchronized on the horizontal fre-

quency,

� B+ voltage always higher than the DC source,

� Current limited on a pulse-by-pulse basis.

The DC/DC converter is disabled:

� when V

or V

are too low,

� when X-Ray protection is latched,

� directly through I

C bus.

When disabled, BOUT is driven to GND by a
0.5mA current source. This feature allows to im-
plement externally a soft start circuit.

4.2 Step-down Mode

In step-down mode, the I

SENSE

information is not

used any more and therefore not sent to the
Pin16. This mode is selected by connecting this
Pin16 to a DC voltage higher than 6V (for example
V

REF-V

Operating Description

� The power MOS is switched ON as for the step-

up mode.

� The feedback to the error amplifier is done as for

the step-up mode.

� The power MOS is switched OFF when the HFO-

CUSCAP voltage gets higher than the error am-
plifier output voltage.

Main Features

� Switching synchronized on the horizontal fre-

quency,

� B+ voltage always lower than the DC source,

� No current limitation.

4.3 Step-up and Step-down Mode Comparison

In step-down mode the control signal is inverted
compared with the step-up mode.This, for the fol-
lowing reason:

� In step-up mode, the switch is a N-channel MOS

referenced to ground and made conductive by a
high level on its gate.

� In step-down, a high-side switch is necessary. It

can be either a P- or a N-channel MOS.

�

For a P-channel MOS, the gate is controlled

directly from Pin 28 through a capacitor (this
allows to spare a Transformer). In this case,
a negative-going pulse is needed to make
the

MOS

conductive.

Therefore

necessary to invert the control signal.

�

For a N-channel MOS, a transformer is

needed to control the gate. The polarity of
the transformer can be easily adapted to the
negative-going control pulse.

TDA9111

39/43

Figure 40. Demonstration Board

H/HVIN

VSYNCIN

H Lock out

PLL2C

R 0

PLL1F

H FOCUS-
C AP

FOCUS
OUT

HGND

HFLY

HREF

COMP

R EGIN

SENSE

+5V

SDA

SCL

B+OUT

GND

HOUT

XRAY

EWOUT

VOUT

CAP

REF

VAGCCA P

VGND

BREATH

B+GND

POSITION

TP1

J11

TP13

TP17

J12

TP16

TP10

C7 22n F

C28

820pF 5%

R23
(***)

C13 10n F

C31 4.7

�

R36

C17 470 nF

C34

820 pF 5%

HREF

C33
100nF

C 27
4 7

�

C46
1nF

R5 0

C51

�

JP1

R 89

33k

R51
1k

SENSE

GND

B+OU T

REGIN

C47
100pF

R58

+12V

C60
100nF

R77

15k

R74
10k

R73

R 75
1 0k

TP8

EHT

COM P

R76
47k

10k

CON4

J19

DYN
FOCU S

R24
10k

47�

R25
1k

HFL Y

C 22

33pF

R8
10 k

HOUT

C25
33pF

R10

10k

R35
10k

+12V

PC2
47k

CC 4
47 pF

+12V

CC1
100nF

CC2
10

�

+12V

CC3
47pF

PC1
47k

-12V

TB1

TB2

CDB

TA1

TA2

CDA

GND

ICC1

MC1

4528

C50
10

�

L3
22

�

BC557

BC54 7

C2
100nF

C3
47

�

470nF

C15

C12

150nF

+12V

R52

3.9k

R4 5

C49

100nF

HOUT

C48
10

�

R53

+12V

R56

560k

D2
1N4 148

+12V

C5
100

�

C6
100nF

C30
100

�

C32
100n F

L1
22

�

+5V

J16 J15

+5V

R39
4.7k

R2 9
4.7k

R42
100

J14

C39

22pF

C40

22pF

R41
100

SCL

SDA

C38

33p F

C45

�

R49
22k

+5V

IC3-STV9422

TILT
J13

R43
10k

C42

�

R30
10k

+5V

C43

�

C37
33pF

8MH z

13 14 15 16 17 18 19 20 21 22 23 2 4

PWM4

PWM5

SCL

SDA

RST

GND

TEST

PWM6

PWM7

PWM3

PWM2

XTALIN

XTALOUT

CKOUT

PXCK

HSYNC

VSYNC

FBLK

PWM1

PWM0

E/W POWER STAGE

R38
2.2

E/W

R1 9
27 0k

C1 1220 pF

Q3
TIP122

R18
10k

R33
4.7k

R9
470

R34
1k

BC557

BC 557

R37
27k

R15
1k

R17
43k

C3 6

�

+12V

J18

VYOKE

R1 1
220

0.5 W

R4
1

0.5 W

R5
5.6

+12V

-12V

TP3

TP4

TP6

TP7

100n F

C14
470

�

C10

100

�

35V

D 1
1 n4004

-1 2V

C10

470

�

100nF

220nF

R3
1.5

100n F

R2
5.6k

IC1

TDA8172

R 40
3 6k

R 1
1 2k

C41

470pF

VER TICA L D EFLECTION STAGE

J17

HOUT

C16 (*)

IC4

TDA9111

TP14

D10
1N4 148

D 9
1 N4148

D8
1N41 48

R 90
1 0k

R78
10

()

R31
27k (**)

(**)

(**) see tabl e

9109A

91 11

R78

Short ed

Mou nted

R90

Remove d

Mou nted

R31

Mount ed

Removed

R17

270k

43k

R18

39k

10k

(*) o ptional

+12V

TP22

1.8 k

(***)
For R

=6.49k

=22.8 kHz typ

For R

=5.23k

=28.3 kHz typ

TDA9111

43/43

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responsib ility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of STMicroelectronics. Specification s mentioned in this public ation are subject to change
witho ut

notice.

This

publica tion

supersedes

and

replaces

all

information

previously

supplied.

STMicroelectronics products are not authorized for use as critical componen ts in life support devices or
systems without express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics.

�

Purchase of I

C Components of STMicroelectronics, conveys a license under the Philip s I

C Patent.

Rights to use these components in a I

C system, is granted provided that the system conforms to the I

Standard Specifications as defined by Philip s.

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Электронный компонент: TDA9111