TDA9203A

C BUS CONTROLLED 70MHz RGB PREAMPLIFIER

June 1998

SHRINK 24

(Plastic Package)

ORDER CODE : TDA9203A

70MHz TYPICAL BANDWIDTH AT 4V

OUT-

PUT WITH 12pF CAPACITIVE LOAD

5.5ns TYPICAL RISE/FALL TIME AT 4V

OUTPUT WITH 12pF CAPACITIVE LOAD

POWERFULL OUTPUT DRIVE CAPABILITY

BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I

C BUS CONTROLLED

INTERNAL

BACK-PORCH

CLAMPING

PULSE GENERATOR

OSD WHITE BALANCE TRACKING

INTERNAL OSD SWITCHES

BLANKING AND FAST-BLANKING INPUTS

VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)

SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE

ABL CONTROL

DESCRIPTION

The TDA9203A is a digitaly controlled wideband
video preamplifier intended for use in mid range
color monitor. All controls and adjustments are
digitaly performed thanks to I

C serial bus. Con-

trast, brightness and DC output level of RGB sig-
nals are common to the 3 channels and drive
adjustment is separate for each channel. Three I

gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamp-
ing of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9203A works for application using AC or
DC coupled CRT driver.
The ABL input provides a 12dB Max. attenuation
on the current contrast value according average
beam limitation voltage.
Because of its features and due to component
saving the TDA9203A leads to a very performant
and cost effective application.

HSYNC

CC1

OUT1

PGND1

CC2

OUT2

PGND2

CC3

OUT3

PGND3

BLK

FBLK

IN1

OSD1

IN2

OSD2

AGND

IN3

OSD3

ABL

LGND

SDA

SCL

920

-
01.

PIN CONNECTIONS

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Name

Pin

Type

Fun ction

IN1

Channel Main Picture Input

OSD1

Channel OSD Input

12V Analog V

IN2

Channel Main Picture Input

OSD2

Channel OSD Input

AGND

I/O

Analog Ground

IN3

Channel Main Picture Input

OSD3

Channel OSD Input

ABL

ABL Input

LGND

I/O

Logic Ground

SDA

I/O

Serial Data Line

SCL

Serial Clock Line

Name

Pin

Type

Function

FBLK

Fast Blanking Input

BLK

Blanking Input

PGND3

I/O

Channel Power Ground

OUT3

Channel Output

CC3

Channel Power V

PGND2

I/O

Channel Power Ground

OUT2

Channel Output

CC2

Channel Power V

PGND1

I/O

Channel Power Ground

OUT1

Channel Output

CC1

Channel Power V

HSYNC

Horizontal Synch Input

9203A

-
0

.
T

PIN DESCRIPTION

CLAMP

REF

IN1

AGND

IN2

BRIGHTNESS

IN3

OUTPUT

STAGE

DRIVE

8 bits

BPCP

CC1

FBLK

BLK

OUT1

PGND1

CC2

OUT2

PGND2

OUT3

PGND3

CC3

ABL

LGND

BUS

DECODER

D/A

LATCHES

BPCP

SCL

SDA

HSYNC

OSD

OSD1

OSD2

OSD3

GREEN CHANNEL

BLUE CHANNEL

REF

OUTPUT

DC LEVEL

ADJUST

TDA9203A

CONTRAST

CONT

03A

-
0

BLOCK DIAGRAM

TDA9203A

2/13

BLK

HSYNC

BPCP

Internal pulse width is controlled by I

03A

-
0

Figure 1

FUNCTIONAL DESCRIPTION

Input Stage
The R, G and B signals must be fed to the three
inputs through coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude
is 1V.
The input stage includes a clamping function. This
clamp is using the input serial capacitor as "mem-
ory capacitor" and is gated by an internally gener-
ated "Back-Porch-Clamping-Pulse (BPCP)".
The synchronization edge of the BPCP is selected
according bit 0 of register R8.
When B0R8 is set to 1, the BPCP is synchronized
on the leading edge of the blankingpulse BLKinputs
on Pin14 (seeFigure1). B7R8 allows to use positive
or negative blanking signal on Pin 14. At power on
reset TDA9203A use only positive blanking.

When B0R8 is clear to 0, the BPCP is synchronized
on the second edge of the horizontal pulse HSYNC
inputs on Pin 24. An automatic function allows to
use positive or negative horizontal pulse on Pin 24
(see Figure 2).

In both case BPCP width is adjustable by I

C, B1

and B2 of register R8 (see R8 Table P8).

Contrast Adjustment (8 bits)

The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I

C bus interface.

The contrast adjustment allows to cover a typical
range of 48dB.

ABL Control
The TDA9203A I

C preamplifier provides an ABL

input (automatic beam limitation) to attenuat e

R,G,B video signals according to beam intensity.
The operating range is 2.5V typicaly, from 5.3V to
2.8V. A typical 12dB Max. attenuation is applied to
the signal whatever the current gain is. Refer to
Figure 3 for ABL input attenuation range.
In case of software control, the ABL input must be
pulled to AV

through a resistor to limit power

consumption (see Figure 11).
ABL input voltage must not exceeed AV

. Input

resistor is 10k

and equivalent schematic given in

Figure 11.

HSYNC

BPCP

Internal pulse width is controlled by I

920

-
04.

Figure 2

Brightness Adjustment (8 bits)

As for the contrast adjustment, the brightness is
controlled by I

The brightness function consists to add the same
DC offset to the three R, G, B signals after contrast
amplification. This DC-Offset is present only out-
side the blanking pulse (see Figure 4).
The DC output level during the blanking pulse, is
forced to "INFRA-BLACK" level (V

Drive Adjustment (3 x 8 bits)

In order to adjust the white balance , the TDA9203A
offers the possibility to adjust separately the overall
gain of each complete video channel. The gain of
each channel is controlled by I

C (8bits each).

The very large drive adjustment range (48dB) allows
different standard or custom color temperature.
It can also be used to adjust the output voltages at
the optimum amplitude to drive the C.R.T drivers,
keepingthe whole contrast control for end-useronly.

The drive adjustment is located after the CON-
TRAST, BRIGHTNESS and OSD switch blocks, so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portion of the signal.

-2

-4

-6

-8

-10

-12

-14

Attenuation (dB)

(V)

9203

-
0

.
E

Figure 3

TDA9203A

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FUNCTIONAL DESCRIPTION (continued)

OSD Inputs
The TDA9203A includes all the circuitry necessary
to mix OSDsignals into the RGB main-picture. Four
pins are dedicated to this function as follow.
Three TTL RGB On Screen Display inputs (Pin 2,
5 and 8). These three inputs are connected to the
three outputs of the corresponding ON-SCREEN-
DISPLAY processor (ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAY processor.
When a high level is present on FBLK, the IC will
acts as follow :
- The three main picture RGB input signals are

internally switched to the internal input clamp
reference voltage.

- The three output signals are set to voltages cor-

respondingto the state (0 or 1) on the three OSD
inputs (see Figure 4).

Example :
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to V

OSD

BRT

, V

OSD

where : V

BRT

= V

BLACK

+ BRT, V

OSD

= V

BRT

+ OSD

BRT is the brightness DC level I

C adjustable.

OSD is the On-Screen Display signal value I

adjustable from 0V to 5.5V

by step of 0.36V.

Semi-transparent function is controlled thanks to
Bit 6 of R8 register (see Table 1).
When semi-transparent mode is activated, video
signal is divided by 2 (CONT).

Table 1

FBLK OSD1 OSD2 OSD3 B6R8

Output

Signal (OUTn)

Video

OSD (1)

Video

OSD

Semi-trans-

parent (2)

Notes : 1. All OSD colors are displayed.

2. One OSD color is displayed as semi-transparent video

without effect on brightness and DC level adjustment.

Output Stage

The three output stagesincorporate threefunctions
which are :
- The blanking stage : When high level is applied

to the BLK input (Pin 14), the three outputs are
switched to a voltage which is 400mV lower than
the BLACK level. The black level is the output
voltage with minimum brightness when input sig-
nal video amplitude is equal to "0".

- The output stage itself : It is a large bandwidth

output amplifier which allow to deliver up to 5V

on the three outputs (for 0.7V video signal on the
inputs).

- The output CLAMP : The IC also incorporates

three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I

C with 4 bits. Practicaly, the DC output

level allow to adjust the BLK level (V

= 400mV

under V

BLACK

) from 0.9V to 2.9V with 12 x 165mV.

The overall waveforms of the output signal accord-
ing to the different adjustment are shown in Fig-
ures 4 and 5.

Serial Interface

The 2-wires serial interface is an I

C interface.

The slave address of the TDA9203A is DC (in
hexadecimal).

Data Transfer

The host MCU can write data into the TDA9203A
registers. Read mode is not available.
To write data into the TDA9203A, after a start, the
MCU must send (see Figure 6) :
- The I

C addressslave byte with a low level for the

R/W bit.

- The byte of the internal register address where

the MCU wants to write data(s).

- The data.

All bytes are sent MSB bit first and the write data
transter is closed by a stop.

TDA9203A

4/13

HSYNC

CONT

(4)

BPCP

BLK

Video IN

FBLK

OSD IN

OSD

(5)

BRT

(3)

BLACK

(2)

(1)

CONT

OSD

BRT

0.4V fixed

OUT1

, V

OUT2

, V

OUT3

Notes : 1.

= 0.5 to 2.5V

BLACK

= V

+ 0.4V

BRT

= V

BLACK

+ BRT (with BRT = 0 to 2.5V)

CONT

= V

BRT

+ CONT with CONT = k x Video IN (CONT = 5V

P P

max. for V

= 0.7V

)

OSD

= V

BRT

+ OSD with OSD = k1 x OSDIN (OSD max. = 5.5V

, OSD min. = 360mV

)

9203

-
0

.
E

Figure 4 : Waveforms VOUT, BRT, CONT, OSD

HSYNC

CONT

BPCP

BLK

Video IN

FBLK

OSD IN

OSD

BRT

BLACK

OUT1

, V

OUT2

, V

OUT3

Note : 1. Drive adjustment modifies the following voltages : V

CONT

, V

BRT

and V

OSD

Drive adjustment do not modify the following voltages : V

and V

BLACK

Two exemples
of drive adjustment

(1)

9203

-
0

.
E

Figure 5 : Waveforms (DRIVE adjustment)

FUNCTIONAL DESCRIPTION (continued)

SCL

SDA

ACK

C Slave Address

Start

Data Byte

ACK

Stop

9203A

-
0

.
E

Figure 6 : I

C Write Operation

TDA9203A

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Электронный компонент: TDA9203A/B