TDA9206

C BUS CONTROLLED 130MHz RGB PREAMPLIFIER

September 1996

DIP24

(Plastic Package)

ORDER CODE : TDA9206

130MHz TYPICAL BANDWIDTH AT 2V

OUTPUT WITH 12pF CAPACITIVE LOAD

2.8ns TYPICAL RISE/FALL TIME AT 2V

OUTPUT WITH 12pF CAPACITIVE LOAD

POWERFULL OUTPUT DRIVE CAPABILITY

BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I

C BUS CONTROLLED

INTERNAL

BACK-PORCH

CLAMPING

PULSE GENERATOR

OSD WHITE BALANCE TRACKING

INTERNAL OSD SWITCHES

BLANKING AND FAST-BLANKING INPUTS

VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)

SEMI-TRANSPARENT BACKGROUND

OSD PICTURE

DESCRIPTION

The TDA9206 is a digitaly controlled wideband
video preamplifier intended for use in high resolu-
tion color monitor. All controls and adjustments are
digitaly performed thanks to I

C serial bus. Con-

trast, brightness and DC output level of RGB sig-
nals are common to the 3 channels and drive
adjustment is separate for each channel. Three I

gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamp-
ing of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9206 works for application usingAC or DC
coupled CRT driver.
Because of its features and due to component
saving the TDA9206 leads to a very performantand
cost effective application.

HSYNC

CC1

OUT1

PGND1

CC2

OUT2

PGND2

CC3

OUT3

PGND3

BLK

FBLK

IN1

OSD1

IN2

OSD2

AGND

IN3

OSD3

LGND

SDA

SCL

9206-01.EPS

PIN CONNECTIONS

1/12

Name

Pin

Type

Function

IN1

Channel Main Picture Input

OSD1

Channel OSD Input

12V Analog V

IN2

Channel Main Picture Input

OSD2

Channel OSD Input

AGND

I/O

Analog Ground

IN3

Channel Main Picture Input

OSD3

Channel OSD Input

12V Logic V

LGND

I/O

Logic Ground

SDA

I/O

Serial Data Line

SCL

Serial Clock Line

Name

Pin

Type

Function

FBLK

Fast Blanking Input

BLK

Blanking Input

PGND3

I/O

Channel Power Ground

OUT3

Channel Output

CC3

Channel Power V

PGND2

I/O

Channel Power Ground

OUT2

Channel Output

CC2

Channel Power V

PGND1

I/O

Channel Power Ground

OUT1

Channel Output

CC1

Channel Power V

HSYNC

Horizontal Synch Input

9206-01.TBL

PIN DESCRIPTION

CLAMP

REF

IN1

AGND

IN2

BR IGHTNESS

IN3

OUTPUT

STAGE

DR IVE

8 bits

BP C P

P V

CC1

FBLK

BLK

OUT1

PGND1

CC2

OUT2

PGND2

OUT3

PGND3

CC3

LGND

BUS

DECODER

D/A

LATCHES

BP CP

SCL

SDA

HS YNC

OSD

OSD1

OSD2

OSD3

GREEN C HANNEL

BLUE CHANNEL

REF

O UTPUT

DC LEVEL

ADJ US T

TDA92 06

CO NTRAST

CONT

9206-02.EPS

BLOCK DIAGRAM

TDA9206

2/12

BLK

HSYNC

BPCP

Internal pulse width is controlled by I

9206-04.EPS

Figure 1

HSYNC

BPCP

Internal pulse width is controlled by I

9206-05.EPS

Figure 2

FUNCTIONAL DESCRIPTION

Input Stage
The R, G and B signals must be fed to the three
inputs through coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude
is 1V.
The input stage includes a clamping function. This
clamp is using the input serial capacitor as "mem-
ory capacitor" and is gated by an internally gener-
ated "Back-Porch-Clamping-Pulse (BPCP)".
The synchronization edge of the BPCP is selected
according bit 0 of register R8.
When B0R8 is set to 1, the BPCP is synchronized
on the leading edge of the blanking pulse BLK
inputs on Pin 14 (see Figure 1).

When B0R8 is clear to 0, the BPCP is synchronized
on the second edge of the horizontal pulse HSYNC
inputs on Pin 24. An automatic function allows to
use positive or negative horizontal pulse on Pin 24
(see Figure 2).

In both case BPCP width is adjustable by I

C, B1

and B2 of register R8 (see R8 Table P8).

Contrast Adjustment (8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I

C bus interface.

The contrast adjustment allows to cover a typical
range of 48dB.

Brightness Adjustment (8 bits)
As for the contrast adjustment, the brightness is
controlled by I

The brightness function consists to add the same
DC offset to the three R, G, B signals after contrast
amplification.

This DC-Offset is present only outside the blanking
pulse (see Figure 3).
The DC output level during the blanking pulse, is
forced to "INFRA-BLACK" level (V

Drive Adjustment (3 x 8 bits)
In order to adjust the white balance , the TDA9206
offers the possibility to adjust separately the overall
gain of each complete video channel.
The gain of each channel is controlled by I

C (8bits

each).
The very large drive adjustment range (48dB) allows
different standard or custom color temperature.
It can also be used to adjust the output voltages at
the optimum amplitude to drive the C.R.T drivers,
keeping the whole contrast control for end-user only.
The drive adjustment is located after the CON-
TRAST, BRIGHTNESS and OSD switch blocks, so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portion of the signal.

OSD Inputs
The TDA9206 includes all the circuitry necessary
to mix OSD signals into the RGB main-picture. Four
pins are dedicated to this function as follow.
Three TTL RGB On Screen Display inputs
(Pin 2, 5 and 8). These three inputs are connected
to the three outputs of the corresponding ON-
SCREEN-DISPLAY processor (ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAY processor.
When a high level is present on FBLK, the IC will
acts as follow :
- The three main picture RGB input signals are

internally switched to the internal input clamp
reference voltage.

- The

three output signals are set to voltages

corresponding to the state (0 or 1) on the three
OSD inputs (see Figure 3).

Example :
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to V

OSD

BRT

, V

OSD

where : V

BRT

= V

BLACK

+ BRT

OSD

= V

BRT

+ OSD

BRT is the brightness DC level I

C adjustable.

OSD is the On-Screen Display signal value I

adjustable from 0V to 4.68V

by step of 0.312V.

Semi-transparent function is controlled thanks to
Bit 6 of R8 register (see Table 1).
When semi-transparent mode is activated, video
signal is divided by 2 (CONT).

TDA9206

3/12

FUNCTIONAL DESCRIPTION (continued)

Table 1

FBLK OSD1 OSD2 OSD3 B6R8

Output

Signal (OUTn)

Video

OSD (1)

Video

OSD

Semi-trans-

parent (2)

Notes : 1. All OSD colors are displayed.

2. One OSD color is displayed as semi-transparent video

without effect on brightness and DC level adjustment.

Output Stage

The three output stages incorporate three functions
which are :
- The blanking stage : When high level is applied

to the BLK input (Pin 14), the three outputs are
switched to a voltage which is 400mV lower than
the BLACK level. The black level is the output
voltage with minimum brightness when input
signal video amplitude is equal to "0".

- The output stage itself : It is a large bandwidth

output amplifier which allow to deliver up to 5V

on the three outputs (for 0.7V video signal on the
inputs). The typical bandwidth is 100MHz at -3dB
measured with 4V

output signal on 12pF load.

- The output CLAMP : The IC also incorporates

three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I

C with 4 bits. Practicaly, the DC output

level allow to adjust the BLK level
(V

= 400mV under V

BLACK

) from 0.9V to 2.9V

with 12 x 165mV.

The overall waveforms of the output signal ac-
cording to the different adjustment are shown in
Figures 3 and 4.

Serial Interface
The 2-wires serial interface is an I

C interface.

The slave address of the TDA9206 is DC (in hexa-
decimal).

Data Transfer
The host MCU can write data into the TDA9206
registers. Read mode is not available.
To write data into the TDA9206, after a start, the
MCU must send (see Figure 5) :
- The I

C address slave byte with a low level for the

R/W bit.

- The byte of the internal register address where

the MCU wants to write data(s).

- The data.

All bytes are sent MSB bit first and the write data
transter is closed by a stop.

HSYNC

CONT

(4)

BPCP

BLK

Video IN

FBLK

OSD IN

OSD

(5)

BRT

(3)

BLACK

(2)

(1)

CONT

OSD

BRT

0.4V fixed

OUT1

, V

OUT2

, V

OUT3

Notes : 1.

= 0.5 to 2.5V

BLACK

= V

+ 0.4V

BRT

= V

BLACK

+ BRT (with BRT = 0 to 2.5V)

CONT

= V

BRT

+ CONT with CONT = k x Video IN (CONT = 5V

max. for V

= 0.7V

)

OSD

= V

BRT

+ OSD with OSD = k1 x OSDIN (OSD max. = 5V

, OSD min. = 312mV

)

9206-06.EPS

Figure 3 : Waveforms VOUT, BRT, CONT, OSD

TDA9206

4/12

HS YNC

CONT

BP CP

BLK

Vide o IN

FBLK

OS D IN

OS D

BR T

BLACK

OUT1

, V

OUT2

, V

OUT3

No te :

1. Drive a djus tm e nt modifies the following voltage s : V

CONT

, V

BRT

a n d V

O S D

Drive a djus tm e nt do no t modify the following voltage s : V

a nd V

BLACK

Two e xamples
of drive a djus tme nt

(1)

9206-07.EPS

Figure 4 : Waveforms (DRIVE adjustment)

SCL

SDA

ACK

C Slave Address

Start

Data Byte

ACK

Stop

9206-08.EPS

Figure 5 : I

C Write Operation

FUNCTIONAL DESCRIPTION (continued)

QUICK REFERENCE DATA

Symbol

Parameter

Min.

Typ.

Max.

Unit

Signal Bandwidth (2V

/12pF load)

130

MHz

Rise and Fall Time (2V

/12pF load)

2.8

Drive Adjustment Range on the 3 Channels separately

Maximum Output Voltage (V

= 0.7 V

)

Output Voltage Range (AC + DC)

9206-02.TBL

TDA9206

5/12

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

Supply Voltage (Pins 3-9-17-20-23)

IN1

IN2

Voltage at any Input Pins (except SDA & SCL)
Voltage at any Input Pins (on SDA & SCL)

GND < V

IN1

< V

GND < V

IN2

< 5.5

V
V

ESD

ESD Susceptability (Human body model ; 100pF Discharge through 1.5k

)

stg

Storage Temperature

- 40, + 150

�

Junction Temperature

150

�

oper

Operating Temperature

0, + 70

�

9206-03.TBL

THERMAL DATA

Symbol

Parameter

Value

Unit

th (j-a)

Junction-ambient Thermal Resistance

C/W

9206-04.TBL

DC ELECTRICAL CHARACTERISTICS (T

amb

= 25

C, V

= 12V, unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Supply Voltage

Pins 3-9-17-20-23

11.4

12.6

Supply Current (All V

Pin current)

= 1k

Video Input Voltage Amplitude

Pins 1-4-7

0.7

Typical Output Voltage Range

Pins 16-19-22

0.5

IL OSD

Low Level Inputs OSD, FBLK, BLK, HSYNC

Pins 2, 5, 8, 13, 14, 24

0.8

IH OSD

High Level Inputs OSD, FBLK, BLK, HSYNC

Pins 2, 5, 8, 13, 14, 24

2.4

9206-05.TBL

AC ELECTRICAL CHARACTERISTICS

amb

= 25

C, V

= 12V, C

= 12pF, R

= 1k

, unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Maximum Gain (20 log x V

OUT AC

IN AC

)

Contrast & Drive at maximum

CAR

Contrast Attenuation Range

= 0.7V, BRT, Drive = POR

DAR

Drive Attenuation Range

= 0.7V, Contrast, Drive = POR

Gain Match

OUT

= 2.5V

, V

= 0.7V

Contrast = Drive = Maxi x 0.7 (POR)

�

0.1

Bandwidth Large Signal

Bandwidth Small Signal

At -3dB, V

= 0.7V

OUT

= 4V

Contrast = Drive = Maxi x 0.87
V

OUT

= 2V

Contrast = Drive = Maxi x 0.62

100

130

MHz

DIS

Video Output Distorsion (see Note)

f = 1MHz, V

OUT

= 1V

, V

= 1V

0.3

, t

Video Output Rise and Fall Time
(see Note)

= 0.7V

OUT

= 4V

Contrast = Drive = Maxi x 0.87
V

OUT

= 2V

Contrast = Drive = Maxi x 0.62

3.8

2.8

4.5

BRT

Brightness Maximum DC Level
Brightness Minimum DC Level

2.5

V
V

BRTM

Brightness Matching

BRT = 50%, Drive = POR

�

Note :

POR = Power-on Reset Value

9206-06.TBL

TDA9206

6/12

AC ELECTRICAL CHARACTERISTICS

amb

= 25

C, V

= 12V, C

= 12pF, R

= 1k

, unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

OSD

CAR

Contrast Attenuation Range
for OSD Input

Output Maximum DC Level
Output Minimum DC Level

2.5
0.5

V
V

Equivalent Load on Video Output

with T

j Max.

0.47

Croostalk between Video Channels
(see Note 1)

OUT

= 2.5V

, V

= 0.7V

Contrast = Drive = Maxi x 0.7 (POR)

= 1MHz

= 50MHz

44
34

dB
dB

Notes : 1.

These parameters are not tested on each unit. They are measured during an internal qualification procedure which includes
characterization on batches coming from corners of our processes and also from temperature characterization.

POR = Power-on Reset Value

9206-07.TBL

C INTERFACE TIMINGS REQUIREMENTS (See Figure 6)

Symbol

Parameter

Min.

Typ.

Max.

Unit

BUF

Time the bus must be free between 2 access

1300

HDS

Hold Time for Start Condition

600

SUP

Set-up Time for Stop Condition

600

LOW

The Low Period of Clock

1300

HIGH

The High Period of Clock

600

HDAT

Hold Time Data

300

SUDAT

Set-up Time Data

250

, t

Rise and Fall Time of both SDA and SCL

300

9206-09.TBL

HDAT

SUDAT

LOW

HIGH

HDS

SUP

BUF

SDA

SCL

9206-09.EPS

Figure 6

C ELECTRICAL CHARACTERISTICS (T

amb

= 25

C, V

= 12V, unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Low Level Input Voltage

On Pins SDA, SCL

1.5

High Level Input Voltage

Input Current

0.4V < V

< 4.5V

-10

+10

�

SCL(Max.)

SCL Maximum Clock Frequency

200

kHz

Low Level Output Voltage

SDA Pin when ACK
Sink Current = 6mA

0.6

9206-08.TBL

TDA9206

7/12

REGISTER DESCRIPTION

Registers Sub-address

Address (Hex)

Register Names

Function

POR Value

Contrast

DAC 8-bit

Brightness

DAC 8-bit

Drive 1

DAC 8-bit

Drive 2

DAC 8-bit

Drive 3

DAC 8-bit

Output DC Level

DAC 4-bit

OSD Contrast

DAC 4-bit

BP and Miscellaneous

See R8 Table

Contrast Register (R1) (Video IN = 0.5V

, Brightness at minimum,Drive at maximum)

Hex

CONT (V

)

G (dB)

POR Value

0.015

-30

0.031

-24

0.062

-18

0.125

-12

0.25

-6

0.5

2.812

Brightness Register (R2) (Drive at maximum)

Hex

BRT (V)

POR Value

0.010

0.020

0.040

0.080

0.160

0.320

0.640

1.28

1.8

2.56

TDA9206

8/12

REGISTER DESCRIPTION (continued)

Drive Registers (R3, R4, R5) (Video IN = 0.5V

, Brightness at minimum, Contrast at maximum)

Hex

CONT (V

)

G (dB)

POR Value

0.015

-30

0.031

-24

0.062

-18

0.125

-12

0.25

-6

0.5

2.812

Output DC Level Register (R6)

Hex

DC (V)

POR Value

0.52

0.69

1.35

2.5

Code 00Hex, 01Hex and 02Hex : not to be used

OSD Contrast Register (R7) (V

OSD IN

= 2.4V

Min

.., Drive at maximum)

Hex

OSD (V)

G (dB)

POR Value

0.312

-24

0.625

-18

1.25

-12

2.5

-6

4.68

BP and Miscellaneous Register (R8)

Function

POR Value

BP Source = HSYNC

BP Source = BLK

BP Pulse Width = 0.33

�

BP Pulse Width = 0.66

�

BP Pulse Width = 1

�

BP Pulse Width = 1.3

�

Test Purposes

Soft Blanking OFF

Soft Blanking ON

Semi Transparent OFF

Semi Transparent ON

Unused

TDA9206

9/12

IN1

OS D1

IN2

OS D2

AGND

IN3

OS D3

S CL

S DA

LGND

HS YNC

P V

C C 1

OUT1

P GND1

P V

C C 2

OUT2

P GND2

P V

C C 3

P GND3

OUT3

BLK

FBLK

D
A

9
2
0
6

+12V

GND

BLUE OUT

RED OUT

GR EEN OUT

100nF

GND B

GND R

GND G

100nF

FBLK

VSYNC

HS YNC

P XCK

CKOUT

XTAL OUT

XTAL IN

TEST

RES ET

SDA

SCL

S
T
V

9
4
2
6

GND

+5V

100nF

+5V

8MHz

33pF

�

16V

100

22pF

S DA

S CL

C BUS

2.7k

S YNCHR O

EXTRACTO R

BLK

HSYNC

VSYNC

9206-18.EPS

APPLICATION DIAGRAM

TDA9206

11/12

PM-DIP24.EPS

PACKAGE MECHANICAL DATA
24 PINS - PLASTIC DIP

Dimensions

Millimeters

Inches

Min.

Typ.

Max.

Min.

Typ.

Max.

0.63

0.025

0.45

0.018

0.23

0.31

0.009

0.012

1.27

0.050

32.2

1.268

15.2

16.68

0.598

0.657

2.54

0.100

27.94

1.100

14.1

0.555

4.445

0.175

3.3

0.130

DIP24.TBL

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.

�

Purchase of I

C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips

C Patent. Rights to use these components in a I

C system, is granted provided that the system confo rms to

the I

C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

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TDA9206

12/12

Электронный компонент: TDA9206