Document Outline

• FEATURES SUMMARY
  • Figure 1. Packages
  • Table 1. Device Summary
• SUMMARY DESCRIPTION
  • Figure 2. Block Diagram
  • Figure 3. TQFP52 Connections
  • Figure 4. TQFP80 Connections
  • Table 2. 80-Pin Package Pin Description
• 52-PIN PACKAGE I/O PORT
• ARCHITECTURE OVERVIEW
  • Memory Organization
    • Figure 5. Memory Map and Address Space
  • Registers
    • Figure 6. 8032 MCU Registers
    • Figure 7. Configuration of BA 16-bit Registers
    • Figure 8. Stack Pointer
    • Figure 9. PSW (Program Status Word) Register
  • Program Memory
  • Data memory
  • RAM
  • XRAM-PSD
    • Figure 10. Interrupt Location of Program Memory
  • SFR
    • Table 3. RAM Address
  • Addressing Modes
    • Figure 11. Direct Addressing
    • Figure 12. Indirect Addressing
    • Figure 13. Indexed Addressing
  • Arithmetic Instructions
    • Table 4. Arithmetic Instructions
  • Logical Instructions
    • Table 5. Logical Instructions
  • Data Transfers
    • Table 6. Data Transfer Instructions that Access Internal Data Memory Space
    • Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes)
    • Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes)
    • Table 9. Shifting a BCD Number One Digit to the Right
    • Table 10. Data Transfer Instruction that Access External Data Memory Space
    • Table 11. Lookup Table READ Instruction
  • Boolean Instructions
  • Relative Offset
    • Table 12. Boolean Instructions
  • Jump Instructions
    • Table 13. Unconditional Jump Instructions
  • Machine Cycles
    • Table 14. Conditional Jump Instructions
    • Figure 14. State Sequence in uPSD321x Devices
• uPSD3200 HARDWARE DESCRIPTION
  • Figure 15. uPSD321x Devices Functional Modules
• MCU MODULE DISCRIPTION
  • Special Function Registers
    • Table 15. SFR Memory Map
    • Table 16. List of all SFR
    • Table 17. PSD Module Register Address Offset
• INTERRUPT SYSTEM
  • External Int0
  • Timer 0 and 1 Interrupts
  • Timer 2 Interrupt
  • I2C Interrupt
  • External Int1
  • USB Interrupt
    • Figure 16. Interrupt System
  • USART Interrupt
  • Interrupt Priority Structure
  • Interrupts Enable Structure
    • Table 18. Priority Levels
    • Table 19. SFR Register
    • Table 20. Description of the IE Bits.
    • Table 21. Description of the IEA Bits
    • Table 22. Description of the IP Bits
    • Table 23. Description of the IPA Bits
  • How Interrupts are Handled
    • Table 24. Vector Addresses
• POWER-SAVING MODE
  • Idle Mode
  • Power-Down Mode
  • Power Control Register
  • Idle Mode
  • Power-Down Mode
    • Table 25. Power-Saving Mode Power Consumption
    • Table 26. Pin Status During Idle and Power-down Mode
    • Table 27. Description of the PCON Bits
• I/O PORTS (MCU Module)
  • Table 28. I/O Port Functions
  • Table 29. P1SFS (91H)
  • Table 30. P3SFS (93H)
  • Table 31. P4SFS (94H)
  • PORT Type and Description
    • Figure 17. PORT Type and Description (Part 1)
    • Figure 18. PORT Type and Description (Part 2)
• OSCILLATOR
  • Figure 19. Oscillator
• SUPERVISORY
  • External Reset
  • Low VDD Voltage Reset
  • Watchdog Timer Overflow
  • USB Reset
    • Figure 20. RESET Configuration
• WATCHDOG TIMER
  • Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)
  • Table 33. Description of the WDKEY Bits
  • Figure 21. RESET Pulse Width
  • Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)
  • Table 35. Description of the WDRST Bits
• TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)
  • Timer 0 and Timer 1
    • Table 36. Control Register (TCON)
    • Table 37. Description of the TCON Bits
    • Table 38. TMOD Register (TMOD)
    • Table 39. Description of the TMOD Bits
    • Figure 22. Timer/Counter Mode 0: 13-bit Counter
  • Timer 2
    • Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload
    • Table 40. Timer/Counter 2 Control Register (T2CON)
    • Table 41. Timer/Counter 2 Operating Modes
    • Table 42. Description of the T2CON Bits
    • Figure 24. Timer 2 in Capture Mode
    • Figure 25. Timer 2 in Auto-Reload Mode
    • Figure 26. Timer/Counter Mode 3: Two 8-bit Counters
• STANDARD SERIAL INTERFACE (UART)
  • Multiprocessor Communications
  • Serial Port Control Register
    • Figure 27. Serial Port Mode 0, Block Diagram
    • Table 43. Serial Port Control Register (SCON)
    • Table 44. Description of the SCON Bits
    • Table 45. Timer 1-Generated Commonly Used Baud Rates
    • Figure 28. Serial Port Mode 0, Waveforms
    • Figure 29. Serial Port Mode 1, Block Diagram
    • Figure 30. Serial Port Mode 1, Waveforms
    • Figure 31. Serial Port Mode 2, Block Diagram
    • Figure 32. Serial Port Mode 2, Waveforms
    • Figure 33. Serial Port Mode 3, Block Diagram
    • Figure 34. Serial Port Mode 3, Waveforms
• ANALOG-TO-DIGITAL CONVERTOR (ADC)
  • ADC Interrupt
    • Figure 35. A/D Block Diagram
    • Table 46. ADC SFR Memory Map
    • Table 47. Description of the ACON Bits
    • Table 48. ADC Clock Input
• PULSE WIDTH MODULATION (PWM)
  • 4-channel PWM Unit (PWM 0-3)
    • Figure 36. Four-Channel 8-bit PWM Block Diagram
    • Table 49. PWM SFR Memory Map
  • Programmable Period 8-bit PWM
    • Figure 37. Programmable PWM 4 Channel Block Diagram
  • PWM 4 Channel Operation
    • Figure 38. PWM 4 With Programmable Pulse Width and Frequency
• I2C INTERFACE
  • Figure 39. Block Diagram of the I2C Bus Serial I/O
  • Table 50. Serial Control Register (S2CON)
  • Table 51. Description of the S2CON Bits
  • Table 52. Selection of the Serial Clock Frequency SCL in Master Mode
  • Serial Status Register (S2STA)
  • Data Shift Register (S2DAT)
    • Table 53. Serial Status Register (S2STA)
    • Table 54. Description of the S2STA Bits
    • Table 55. Data Shift Register (S2DAT)
  • Address Register (S2ADR)
    • Table 56. Address Register (S2ADR)
    • Table 57. Start /Stop Hold Time Detection Register (S2SETUP)
    • Table 58. System Cock of 40MHz
    • Table 59. System Clock Setup Examples
• USB HARDWARE
  • USB related registers
    • Table 60. USB Address Register (UADR: 0EEh)
    • Table 61. Description of the UADR Bits
    • Table 62. USB Interrupt Enable Register (UIEN: 0E9h)
    • Table 63. Description of the UIEN Bits
    • Table 64. USB Interrupt Status Register (UISTA: 0E8h)
    • Table 65. Description of the UISTA Bits
    • Table 66. USB Endpoint0 Transmit Control Register (UCON0: 0EAh)
    • Table 67. Description of the UCON0 Bits
    • Table 68. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)
    • Table 69. Description of the UCON1 Bits
    • Table 70. USB Control Register (UCON2: 0ECh)
    • Table 71. Description of the UCON2 Bits
    • Table 72. USB Endpoint0 Status Register (USTA: 0EDh)
    • Table 73. Description of the USTA Bits
    • Table 74. USB Endpoint0 Data Receive Register (UDR0: 0EFh)
    • Table 75. USB Endpoint0 Data Transmit Register (UDT0: 0E7h)
    • Table 76. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)
    • Table 77. USB SFR Memory Map
  • Transceiver
    • Figure 40. Low Speed Driver Signal Waveforms
    • Table 78. Transceiver DC Characteristics
    • Table 79. Transceiver AC Characteristics
  • Receiver Characteristics
    • Figure 41. Differential Input Sensitivity Over Entire Common Mode Range
  • External USB Pull-Up Resistor
    • Figure 42. USB Data Signal Timing and Voltage Levels
    • Figure 43. Receiver Jitter Tolerance
    • Figure 44. Differential to EOP Transition Skew and EOP Width
    • Figure 45. Differential Data Jitter
• PSD MODULE
  • Functional Overview
    • Figure 46. PSD MODULE Block Diagram
  • In-System Programming (ISP)
    • Table 80. Methods of Programming Different Functional Blocks of the PSD MODULE
• DEVELOPMENT SYSTEM
  • Figure 47. PSDsoft Express Development Tool
• PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
  • Table 81. Register Address Offset
• PSD MODULE DETAILED OPERATION
• MEMORY BLOCKS
  • Primary Flash Memory and Secondary Flash memory Description
  • Memory Block Select Signals
  • Instructions
    • Table 82. Instructions
  • Power-down Instruction and Power-up Mode
  • READ
    • Table 83. Status Bit
  • Programming Flash Memory
    • Figure 48. Data Polling Flowchart
    • Figure 49. Data Toggle Flowchart
  • Erasing Flash Memory
  • Specific Features
    • Table 84. Sector Protection/Security Bit Definition � Flash Protection Register
    • Table 85. Sector Protection/Security Bit Definition � Secondary Flash Protection Register
  • SRAM
  • Sector Select and SRAM Select
    • Figure 50. Priority Level of Memory and I/O Components in the PSD MODULE
    • Table 86. VM Register
    • Figure 51. Separate Space Mode
    • Figure 52. Combined Space Mode
  • Page Register
    • Figure 53. Page Register
• PLDs
  • Table 87. DPLD and CPLD Inputs
  • The Turbo Bit in PSD MODULE
    • Figure 54. PLD Diagram
  • Decode PLD (DPLD)
    • Figure 55. DPLD Logic Array
  • Complex PLD (CPLD)
    • Figure 56. Macrocell and I/O Port
  • Output Macrocell (OMC)
    • Table 88. Output Macrocell Port and Data Bit Assignments
  • Product Term Allocator
    • Figure 57. CPLD Output Macrocell
  • Input Macrocells (IMC)
    • Figure 58. Input Macrocell
• I/O PORTS (PSD MODULE)
  • General Port Architecture
    • Figure 59. General I/O Port Architecture
  • Port Operating Modes
  • MCU I/O Mode
  • PLD I/O Mode
  • Address Out Mode
  • Peripheral I/O Mode
  • JTAG In-System Programming (ISP)
    • Figure 60. Peripheral I/O Mode
    • Table 89. Port Operating Modes
    • Table 90. Port Operating Mode Settings
    • Table 91. I/O Port Latched Address Output Assignments
  • Port Configuration Registers (PCR)
    • Table 92. Port Configuration Registers (PCR)
    • Table 93. Port Pin Direction Control, Output Enable P.T. Not Defined
    • Table 94. Port Pin Direction Control, Output Enable P.T. Defined
    • Table 95. Port Direction Assignment Example
  • Port Data Registers
    • Table 96. Drive Register Pin Assignment
    • Table 97. Port Data Registers
  • Ports A and B � Functionality and Structure
    • Figure 61. Port A and Port B Structure
  • Port C � Functionality and Structure
    • Figure 62. Port C Structure
  • Port D � Functionality and Structure
    • Figure 63. Port D Structure
  • External Chip Select
    • Figure 64. Port D External Chip Select Signals
• POWER MANAGEMENT
  • Figure 65. APD Unit
  • Figure 66. Enable Power-down Flow Chart
  • Table 98. Power-down Mode�s Effect on Ports
  • PLD Power Management
  • PSD Chip Select Input (CSI, PD2)
  • Input Clock
  • Input Control Signals
    • Table 99. Power Management Mode Registers PMMR0
    • Table 100. Power Management Mode Registers PMMR2
    • Table 101. APD Counter Operation
• RESET TIMING AND DEVICE STATUS AT RESET
  • Warm RESET
  • I/O Pin, Register and PLD Status at RESET
    • Figure 67. Reset (RESET) Timing
    • Table 102. Status During Power-on RESET, Warm RESET and Power-down Mode
• PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
  • Standard JTAG Signals
    • Table 103. JTAG Port Signals
  • JTAG Extensions
  • Security and Flash memory Protection
• INITIAL DELIVERY STATE
• AC/DC PARAMETERS
  • Figure 68. PLD ICC /Frequency Consumption (5V range)
  • Figure 69. PLD ICC /Frequency Consumption (3V range)
  • Table 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
• MAXIMUM RATING
  • Table 105. Absolute Maximum Ratings
• EMC CHARACTERISTICS
  • Functional EMS (Electromagnetic Susceptibility)
  • Designing Hardened Software To Avoid Noise Problems
  • Absolute Maximum Ratings (Electrical Sensitivity)
    • Table 106. EMS Test Results
    • Table 107. ESD Absolute Maximum Ratings
    • Table 108. Latch-up and Dynamic Latch-up Electrical Sensitivities
• DC AND AC PARAMETERS
  • Table 109. Operating Conditions (5V Devices)
  • Table 110. Operating Conditions (3V Devices)
  • Table 111. AC Signal Letter Symbols for Timing
  • Table 112. AC Signal Behavior Symbols for Timing
  • Figure 70. Switching Waveforms � Key
  • Table 113. Major Parameters
  • Table 114. DC Characteristics (5V Devices)
  • Table 115. DC Characteristics (3V Devices)
  • Figure 71. External Program Memory READ Cycle
  • Table 116. External Program Memory AC Characteristics (with the 5V MCU Module)
  • Table 117. External Program Memory AC Characteristics (with the 3V MCU Module)
  • Figure 72. External Data Memory READ Cycle
  • Table 118. External Clock Drive (with the 5V MCU Module)
  • Table 119. External Clock Drive (with the 3V MCU Module)
  • Figure 73. External Data Memory WRITE Cycle
  • Table 120. External Data Memory AC Characteristics (with the 5V MCU Module)
  • Table 121. External Data Memory AC Characteristics (with the 3V MCU Module)
  • Table 122. A/D Analog Specification
  • Figure 74. Input to Output Disable / Enable
  • Table 123. CPLD Combinatorial Timing (5V Devices)
  • Table 124. CPLD Combinatorial Timing (3V Devices)
  • Figure 75. Synchronous Clock Mode Timing � PLD
  • Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
  • Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
  • Figure 76. Asynchronous RESET / Preset
  • Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)
  • Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
  • Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
  • Figure 78. Input Macrocell Timing (Product Term Clock)
  • Table 129. Input Macrocell Timing (5V Devices)
  • Table 130. Input Macrocell Timing (3V Devices)
  • Table 131. Program, WRITE and Erase Times (5V Devices)
  • Table 132. Program, WRITE and Erase Times (3V Devices)
  • Figure 79. Peripheral I/O READ Timing
  • Table 133. Port A Peripheral Data Mode READ Timing (5V Devices)
  • Table 134. Port A Peripheral Data Mode READ Timing (3V Devices)
  • Figure 80. Peripheral I/O WRITE Timing
  • Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices)
  • Table 136. Port A Peripheral Data Mode WRITE Timing (3V Devices)
  • Figure 81. Reset (RESET) Timing
  • Table 137. Reset (RESET) Timing (5V Devices)
  • Table 138. Reset (RESET) Timing (3V Devices)
  • Table 139. VSTBYON Definitions Timing (5V Devices)
  • Table 140. VSTBYON Timing (3V Devices)
  • Figure 82. ISC Timing
  • Table 141. ISC Timing (5V Devices)
  • Table 142. ISC Timing (3V Devices)
  • Figure 83. MCU Module AC Measurement I/O Waveform
  • Figure 84. PSD MODULE AC Float I/O Waveform
  • Figure 85. External Clock Cycle
  • Figure 86. Recommended Oscillator Circuits
  • Figure 87. PSD MODULE AC Measurement I/O Waveform
  • Figure 88. PSD MODULEAC Measurement Load Circuit
  • Table 143. Capacitance
• PACKAGE MECHANICAL INFORMATION
  • Figure 89. TQFP52 � 52-lead Plastic Thin, Quad, Flat Package Outline
  • Table 144. TQFP52 � 52-lead Plastic Thin, Quad, Flat Package Mechanical Data
  • Figure 90. TQFP80 � 80-lead Plastic Thin, Quad, Flat Package Outline
  • Table 145. TQFP80 � 80-lead Plastic Thin, Quad, Flat Package Mechanical Data
• PART NUMBERING
  • Table 146. Ordering Information Scheme
• REVISION HISTORY
  • Table 147. Document Revision History