1/152

September 2003

Rev. 1.2

UPSD3212C

UPSD3212CV

Flash Programmable System Devices

with 8032 Microcontroller Core and 16Kbit SRAM

FEATURES SUMMARY

The uPSD321X Devices combine a Flash PSD
architecture with an 8032 microcontroller core.
The uPSD321X Devices of Flash PSDs feature
dual banks of Flash memory, SRAM, general
purpose I/O and programmable logic, supervi-
sory functions and access via I

C, ADC and

PWM channels, and an on-board 8032 micro-
controller core, with two UARTs, three 16-bit
Timer/Counters and two External Interrupts. As
with other Flash PSD families, the uPSD321X
Devices are also in-system programmable (ISP)
via a JTAG ISP interface.

Large 2KByte SRAM with battery back-up
option

Dual bank Flash memories

64KByte main Flash memory

16KByte secondary Flash memory

Content Security

Block access to Flash memory

Programmable Decode PLD for flexible address
mapping of all memories within 8032 space.

High-speed clock standard 8032 core (12-cycle)

C interface for peripheral connections

5 Pulse Width Modulator (PWM) channels

Analog-to-Digital Converter (ADC)

Six I/O ports with up to 46 I/O pins

3000 gate PLD with 16 macrocells

Supervisor functions with Watchdog Timer

In-System Programming (ISP) via JTAG

Zero-Power Technology

Single Supply Voltage

4.5 to 5.5V

3.0 to 3.6V

Figure 1. 52-lead, Thin, Quad, Flat Package

Figure 2. 80-lead, Thin, Quad, Flat Package

TQFP52 (T)

TQFP80 (U)

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TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

uPSD321X Devices Product Matrix (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

80-Pin Package Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Direct Addressing (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Indirect Addressing (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Indexed Addressing (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Arithmetic Instructions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logical Instructions (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data Transfer Instructions that Access Internal Data Memory Space (Table 6.) . . . . . . . . . . . . . . 24

Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.) . . . . . . . 25

Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.) . . . . . . . . 25

Shifting a BCD Number One Digit to the Right (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Transfer Instruction that Access External Data Memory Space (Table 10.) . . . . . . . . . . . . . . 26

Lookup Table READ Instruction (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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UPSD3212C, UPSD3212CV

Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Boolean Instructions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Unconditional Jump Instructions (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Conditional Jump Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

State Sequence in uPSD321X Devices (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

uPSD3200 HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

uPSD321X Devices Functional Modules (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SFR Memory Map (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

List of all SFR (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PSD Module Register Address Offset (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

External Int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

I2C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

External Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupt System (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Priority Levels (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SFR Register (Table 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Description of the IE Bits. (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IEA Bits (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IP Bits (Table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IPA Bits (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Vector Addresses (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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POWER-SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Saving Mode Power Consumption (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Pin Status During Idle and Power-down Mode (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Description of the PCON Bits (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I/O Port Functions (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

P1SFS (91H) (Table 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

P3SFS (93H) (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

P4SFS (94H) (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PORT Type and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PORT Type and Description (Part 1) (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PORT Type and Description (Part 2) (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Oscillator (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SUPERVISORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

RESET Configuration (Figure 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Low VDD Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Watchdog Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Watchdog Timer Key Register (WDKEY: 0AEH) (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Description of the WDKEY Bits (Table 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

RESET Pulse Width (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Watchdog Timer Clear Register (WDRST: 0A6H) (Table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Description of the WDRST Bits (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0

TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Control Register (TCON) (Table 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Description of the TCON Bits (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

TMOD Register (TMOD) (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Description of the TMOD Bits (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Timer/Counter Mode 0: 13-bit Counter (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter Mode 2: 8-bit Auto-reload (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter 2 Control Register (T2CON) (Table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter 2 Operating Modes (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Description of the T2CON Bits (Table 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Timer 2 in Capture Mode (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timer 2 in Auto-Reload Mode (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timer/Counter Mode 3: Two 8-bit Counters (Figure 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Port Mode 0, Block Diagram (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Port Control Register (SCON) (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Description of the SCON Bits (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Timer 1-Generated Commonly Used Baud Rates (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Serial Port Mode 0, Waveforms (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Serial Port Mode 1, Block Diagram (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Serial Port Mode 1, Waveforms (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Serial Port Mode 2, Block Diagram (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Serial Port Mode 2, Waveforms (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Serial Port Mode 3, Block Diagram (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Serial Port Mode 3, Waveforms (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

A/D Block Diagram (Figure 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

ADC SFR Memory Map (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Description of the ACON Bits (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

ADC Clock Input (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4-channel PWM Unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Four-Channel 8-bit PWM Block Diagram (Figure 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

PWM SFR Memory Map (Table 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Programmable PWM 4 Channel Block Diagram (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

PWM 4 With Programmable Pulse Width and Frequency (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . 74

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I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Block Diagram of the I2C Bus Serial I/O (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Serial Control Register (S2CON) (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Description of the S2CON Bits (Table 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Selection of the Serial Clock Frequency SCL in Master Mode (Table 52.) . . . . . . . . . . . . . . . . . . . 76

Serial Status Register (S2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Shift Register (S2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Serial Status Register (S2STA) (Table 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Description of the S2STA Bits (Table 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Shift Register (S2DAT) (Table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Address Register (S2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Address Register (S2ADR) (Table 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Start /Stop Hold Time Detection Register (S2SETUP) (Table 57.) . . . . . . . . . . . . . . . . . . . . . . . . . 78

System Cock of 40MHz (Table 58.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

System Clock Setup Examples (Table 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PSD MODULE Block Diagram (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Methods of Programming Different Functional Blocks of the PSD MODULE (Table 60.) . . . . . . . . 81

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

PSDsoft Express Development Tool (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 83

Register Address Offset (Table 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 84

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Instructions (Table 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Status Bit (Table 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Data Polling Flowchart (Figure 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Data Toggle Flowchart (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Sector Protection/Security Bit Definition Flash Protection Register (Table 64.) . . . . . . . . . . . . . . 92

Sector Protection/Security Bit Definition Secondary Flash Protection Register (Table 65.) . . . . . 92

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Priority Level of Memory and I/O Components in the PSD MODULE (Figure 44.) . . . . . . . . . . . . . 93

VM Register (Table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Separate Space Mode (Figure 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Combined Space Mode (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Page Register (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

DPLD and CPLD Inputs (Table 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

The Turbo Bit in PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

PLD Diagram (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

DPLD Logic Array (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Macrocell and I/O Port (Figure 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Output Macrocell Port and Data Bit Assignments (Table 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

CPLD Output Macrocell (Figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Input Macrocell (Figure 52.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

General I/O Port Architecture (Figure 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Peripheral I/O Mode (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Port Operating Modes (Table 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Port Operating Mode Settings (Table 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

I/O Port Latched Address Output Assignments (Table 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Port Configuration Registers (PCR) (Table 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Port Pin Direction Control, Output Enable P.T. Not Defined (Table 73.) . . . . . . . . . . . . . . . . . . . . 107

Port Pin Direction Control, Output Enable P.T. Defined (Table 74.) . . . . . . . . . . . . . . . . . . . . . . . 107

Port Direction Assignment Example (Table 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Drive Register Pin Assignment (Table 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Ports A and B Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Port A and Port B Structure (Figure 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Port C Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Port C Structure (Figure 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Port D Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Port D Structure (Figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Port D External Chip Select Signals (Figure 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

APD Unit (Figure 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Enable Power-down Flow Chart (Figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Power-down Mode's Effect on Ports (Table 78.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Power Management Mode Registers PMMR0 (Table 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Power Management Mode Registers PMMR2 (Table 80.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

APD Counter Operation (Table 81.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Reset (RESET) Timing (Figure 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Status During Power-on RESET, Warm RESET and Power-down Mode (Table 82.). . . . . . . . . . 117

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PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 118

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

JTAG Port Signals (Table 83.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Security and Flash memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PLD ICC /Frequency Consumption (5V range) (Figure 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PLD ICC /Frequency Consumption (3V range) (Figure 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PSD MODULE Example, Typ. Power Calculation at V

= 5.0V (Turbo Mode Off) (Table 84.) . . 120

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Absolute Maximum Ratings (Table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Operating Conditions (5V Devices) (Table 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Operating Conditions (3V Devices) (Table 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

AC Symbols for Timing (Table 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Switching Waveforms Key (Figure 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

DC Characteristics (5V Devices) (Table 89.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

DC Characteristics (3V Devices) (Table 90.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

External Program Memory READ Cycle (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

External Program Memory AC Characteristics (with the 5V MCU Module) (Table 91.) . . . . . . . . 128

External Program Memory AC Characteristics (with the 3V MCU Module) (Table 92.) . . . . . . . . 129

External Clock Drive (with the 5V MCU Module) (Table 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

External Clock Drive (with the 3V MCU Module) (Table 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

External Data Memory READ Cycle (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

External Data Memory WRITE Cycle (Figure 67.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

External Data Memory AC Characteristics (with the 5V MCU Module) (Table 95.). . . . . . . . . . . . 131

External Data Memory AC Characteristics (with the 3V MCU Module) (Table 96.). . . . . . . . . . . . 132

A/D Analog Specification (Table 97.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Input to Output Disable / Enable (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CPLD Combinatorial Timing (5V Devices) (Table 98.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CPLD Combinatorial Timing (3V Devices) (Table 99.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Synchronous Clock Mode Timing PLD (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) (Table 100.) . . . . . . . . . . . . . . . 134

CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) (Table 101.) . . . . . . . . . . . . . . . 135

Asynchronous RESET / Preset (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Asynchronous Clock Mode Timing (product term clock) (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . 136

CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) (Table 102.) . . . . . . . . . . . . . . 136

CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) (Table 103.) . . . . . . . . . . . . . . 137

UPSD3212C, UPSD3212CV

10/152

Input Macrocell Timing (product term clock) (Figure 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Input Macrocell Timing (5V Devices) (Table 104.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Input Macrocell Timing (3V Devices) (Table 105.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Program, WRITE and Erase Times (5V Devices) (Table 106.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Program, WRITE and Erase Times (3V Devices) (Table 107.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Peripheral I/O READ Timing (Figure 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Port A Peripheral Data Mode READ Timing (5V Devices) (Table 108.) . . . . . . . . . . . . . . . . . . . . 140

Port A Peripheral Data Mode READ Timing (3V Devices) (Table 109.) . . . . . . . . . . . . . . . . . . . . 140

Peripheral I/O WRITE Timing (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Port A Peripheral Data Mode WRITE Timing (5V Devices) (Table 110.) . . . . . . . . . . . . . . . . . . . 141

Port A Peripheral Data Mode WRITE Timing (3V Devices) (Table 111.) . . . . . . . . . . . . . . . . . . . 141

Reset (RESET) Timing (5V Devices) (Table 112.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Reset (RESET) Timing (3V Devices) (Table 113.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

STBYON

Definitions Timing (5V Devices) (Table 114.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

STBYON

Timing (3V Devices) (Table 115.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

ISC Timing (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

ISC Timing (5V Devices) (Table 116.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

ISC Timing (3V Devices) (Table 117.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

MCU Module AC Measurement I/O Waveform (Figure 77.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

PSD MODULE AC Float I/O Waveform (Figure 78.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

External Clock Cycle (Figure 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Recommended Oscillator Circuits (Figure 80.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

PSD MODULE AC Measurement I/O Waveform (Figure 81.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

PSD MODULEAC Measurement Load Circuit (Figure 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Capacitance (Table 118.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11/152

UPSD3212C, UPSD3212CV

SUMMARY DESCRIPTION

Dual bank Flash memories

Concurrent operation, read from memory

while erasing and writing the other. In-Appli-
cation Programming (IAP) for remote updates

Large 64KByte main Flash memory for appli-

cation code, operating systems, or bit maps
for graphic user interfaces

Large 16KByte secondary Flash memory di-

vided in small sectors. Eliminate external EE-
PROM with software EEPROM emulation

Secondary Flash memory is large enough for

sophisticated communication protocol during
IAP while continuing critical system tasks

Large SRAM with battery back-up option

2KByte SRAM for RTOS, high-level languag-

es, communication buffers, and stacks

Programmable Decode PLD for flexible address
mapping of all memories

Place individual Flash and SRAM sectors on

any address boundary

Built-in page register breaks restrictive 8032

limit of 64KByte address space

Special register swaps Flash memory seg-

ments between 8032 "program" space and
"data" space for efficient In-Application Pro-
gramming

High-speed clock standard 8032 core (12-cycle)

40MHz operation at 5V, 24MHz at 3.3V

2 UARTs with independent baud rate, three

16-bit Timer/Counters and two External Inter-
rupts

C interface for peripheral connections

Capable of master or slave operation

5 Pulse Width Modulator (PWM) channels

Four 8-bit PWM units

One 8-bit PWM unit with programmable peri-

4-channel, 8-bit Analog-to-Digital Converter
(ADC) with analog supply voltage (V

REF

)

Six I/O ports with up to 46 I/O pins

Multifunction I/O: GPIO, I

C, PWM, PLD I/O,

supervisor, and JTAG

Eliminates need for external latches and logic

3000 gate PLD with 16 macrocells

Create glue logic, state machines, delays,

etc.

Eliminate external PALs, PLDs, and 74HCxx

Simple PSDsoft Express software... Free

Supervisor functions

Generates reset upon low voltage or watch-

dog time-out. Eliminate external supervisor
device

RESET Input pin; Reset output via PLD

In-System Programming (ISP) via JTAG

Program entire chip in 10 - 25 seconds with

no involvement of 8032

Allows efficient manufacturing, easy product

testing, and Just-In-Time inventory

Eliminate sockets and pre-programmed parts

Program with FlashLINK

cable and any PC

Content Security

Programmable Security Bit blocks access of

device programmers and readers

Zero-Power Technology

Memories and PLD automatically reach

standby current between input changes

Packages

52-pin TQFP

80-pin TQFP: allows access to 8032 address/

data/control signals for connecting to external
peripherals

UPSD3212C, UPSD3212CV

12/152

Table 1. uPSD321X Devices Product Matrix

Figure 3. TQFP52 Connections

Note: 1. Pull-up resistor required on pin 5 (2k

for 3V devices, 7.5k

for 5V devices).

2. NC = Not Connected.

Part No.

Main

Flash

(bit)

Sec.

Flash

(bit)

SRAM

(bit)

Macro

-Cells

I/O

Pins

PWM

Ch.

Timer

/ Ctr

UART

Ch.

ADC

Ch.

MHz

Pins

uPSD3212C-40T6

512K

128K

16K

uPSD3212CV-24T6

512K

128K

16K

uPSD3212C-40U6

512K

128K

16K

uPSD3212CV-24U6

512K

128K

16K

39 P1.5 / ADC1

38 P1.4 / ADC0

37 P1.3 / TXD1

36 P1.2 / RXD1

35 P1.1 / T2X

34 P1.0 / T2

33 VCC
32 XTAL2

31 XTAL1

30 P3.7 / SCL1

29 P3.6 / SDA1

28 P3.5 / T1

27 P3.4 / T0

PD1

PC7

PC6

PC5

See note(1)

PC4

VCC

GND

PC3

PC2

PC1

PC0

PB0

PB1

PB2

PB3

PB4

PB5

VREF

GND

RESET

PB6

PB7

P1.7/ADC3

P1.6/ADC2

P4.7 / PWM4

P4.6 / PWM3

P4.5 / PWM2

P4.4 / PWM1

P4.3 / PWM0

GND

P4.2

P4.1

P4.0

P3.0 / RXD

P3.1 / TXD

P3.2 / EXINT0

P3.3 / EXINT1

AI07423

13/152

UPSD3212C, UPSD3212CV

Figure 4. TQFP80 Connections

Note: 1. Pull-up resistor required on pin 8 (2k

for 3V devices, 7.5k

for 5V devices).

2. NC = Not Connected.

60 P1.5 / ADC1

59 P1.4 / ADC0

58 P1.3 / TXD1

57 P2.3, A11

56 P1.2 / RXD1

55 P2.2, A10

54 P1.1 / T2X

53 P2.1, A9

52 P1.0 / T2

51 P2.0, A8

50 VCC
49 XTAL2

48 XTAL1

47 P0.7, AD7

46 P3.7 / SCL1

45 P0.6, AD6

44 P3.6 / SDA1

43 P0.5, AD5

42 P3.5 / T1

41 P0.4, AD4

PD2

P3.3 /EXINT1

PD1

PD0, ALE

PC7

PC6

PC5

See note(1)

PC4

VCC

GND

PC3

PC2

PC1

P4.7 / PWM4

P4.6 / PWM3

PC0

PB0

P3.2 / EXINT0

PB1

P3.1 / TXD

PB2

P3.0 / RXD

PB3

PB4

PB5

VREF

GND

RESET

PB6

PB7

RD, CNTL1

P1.7 / ADC3

PSEN, CNTL2

WR, CNTL0

P1.6 / ADC2

PA7

PA6

P4.5 / PWM2

PA5

P4.4 / PWM1

PA4

P4.3 / PWM0

PA3

GND

P4.2

P4.1

PA2

P4.0

PA1

PA0

AD0, P0.0

AD1, P0.1

AD2, P0.2

AD3, P0.3

P3.4 / T0

AI07424

UPSD3212C, UPSD3212CV

14/152

Table 2. 80-Pin Package Pin Description

Port Pin

Signal

Name

Pin No.

In/Out

Function

Basic

Alternate

P0.0

AD0

I/O

External Bus
Multiplexed Address/Data bus A1/D1

P0.1

AD1

I/O

Multiplexed Address/Data bus A0/D0

P0.2

AD2

I/O

Multiplexed Address/Data bus A2/D2

P0.3

AD3

I/O

Multiplexed Address/Data bus A3/D3

P0.4

AD4

I/O

Multiplexed Address/Data bus A4/D4

P0.5

AD5

I/O

Multiplexed Address/Data bus A5/D5

P0.6

AD6

I/O

Multiplexed Address/Data bus A6/D6

P0.7

AD7

I/O

Multiplexed Address/Data bus A7/D7

P1.0

I/O

General I/O port pin

Timer 2 Count input

P1.1

T2EX

I/O

General I/O port pin

Timer 2 Trigger input

P1.2

RxD2

I/O

General I/O port pin

2nd UART Receive

P1.3

TxD2

I/O

General I/O port pin

2nd UART Transmit

P1.4

ADC0

I/O

General I/O port pin

ADC Channel 0 input

P1.5

ADC1

I/O

General I/O port pin

ADC Channel 1 input

P1.6

ADC2

I/O

General I/O port pin

ADC Channel 2 input

P1.7

ADC3

I/O

General I/O port pin

ADC Channel 3 input

P2.0

External Bus, Address A8

P2.1

External Bus, Address A9

P2.2

A10

External Bus, Address A10

P2.3

A11

External Bus, Address A11

P3.0

RxD1

I/O

General I/O port pin

UART Receive

P3.1

TxD1

I/O

General I/O port pin

UART Transmit

P3.2

INTO

I/O

General I/O port pin

Interrupt 0 input / Timer 0 gate
control

P3.3

INT1

I/O

General I/O port pin

Interrupt 1 input / Timer 1 gate
control

P3.4

I/O

General I/O port pin

Counter 0 input

P3.5

I/O

General I/O port pin

Counter 1 input

P3.6

SDA1

I/O

General I/O port pin

C Bus serial data I/O

P3.7

SCL1

I/O

General I/O port pin

C Bus clock I/O

P4.0

I/O

General I/O port pin

P4.1

I/O

General I/O port pin

P4.2

I/O

General I/O port pin

P4.3

PWM0

I/O

General I/O port pin

8-bit Pulse Width Modulation
output 0

15/152

UPSD3212C, UPSD3212CV

P4.4

PWM1

I/O

General I/O port pin

8-bit Pulse Width Modulation
output 1

P4.5

PWM2

I/O

General I/O port pin

8-bit Pulse Width Modulation
output 2

P4.6

PWM3

I/O

General I/O port pin

8-bit Pulse Width Modulation
output 3

P4.7

PWM4

I/O

General I/O port pin

Programmable 8-bit Pulse Width
modulation output 4

PUP

I/O

Pull-up resistor required (2k

for 3V

devices, 7.5k

for 5V devices)

AVREF

Reference Voltage input for ADC

RD_

READ signal, external bus

WR_

WRITE signal, external bus

PSEN_

PSEN signal, external bus

ALE

Address Latch signal, external bus

RESET_

Active low RESET input

XTAL1

Oscillator input pin for system clock

XTAL2

Oscillator output pin for system clock

PA0

I/O

General I/O port pin

1. PLD Macro-cell outputs
2. PLD inputs
3. Latched Address Out (A0-A7)
4. Peripheral I/O Mode

PA1

I/O

General I/O port pin

PA2

I/O

General I/O port pin

PA3

I/O

General I/O port pin

PA4

I/O

General I/O port pin

PA5

I/O

General I/O port pin

PA6

I/O

General I/O port pin

PA7

I/O

General I/O port pin

PB0

I/O

General I/O port pin

1. PLD Macro-cell outputs
2. PLD inputs
3. Latched Address Out (A0-A7)

PB1

I/O

General I/O port pin

PB2

I/O

General I/O port pin

PB3

I/O

General I/O port pin

PB4

I/O

General I/O port pin

PB5

I/O

General I/O port pin

PB6

I/O

General I/O port pin

PB7

I/O

General I/O port pin

Port Pin

Signal

Name

Pin No.

In/Out

Function

Basic

Alternate

UPSD3212C, UPSD3212CV

16/152

52 PIN PACKAGE I/O PORT
The 52-pin package members of the uPSD321X
Devices have the same port pins as those of the
80-pin package except:

Port 0 (P0.0-P0.7, external address/data bus
AD0-AD7)

Port 2 (P2.0-P2.3, external address bus A8-
A11)

Port A (PA0-PA7)

Port D (PD2)

Bus control signal (RD,WR,PSEN,ALE)

Pin 5 requires a pull-up resistor (2k

for 3V de-

vices, 7.5k

for 5V devices) for all devices.

PC0

TMS

JTAG pin

1. PLD Macro-cell outputs
2. PLD inputs
3. SRAM stand by voltage input

STBY

)

4. SRAM battery-on indicator

(PC4)

5. JTAG pins are dedicated pins

PC1

TCK

JTAG pin

PC2

STBY

I/O

General I/O port pin

PC3

TSTAT

I/O

General I/O port pin

PC4

TERR

I/O

General I/O port pin

PC5

TDI

JTAG pin

PC6

TDO

JTAG pin

PC7

I/O

General I/O port pin

PD1

CLKIN

I/O

General I/O port pin

1. PLD I/O
2. Clock input to PLD and APD

PD2

CSI

I/O

General I/O port pin

1. PLD I/O
2. Chip select to PSD Module

Vcc

GND

Port Pin

Signal

Name

Pin No.

In/Out

Function

Basic

Alternate

17/152

UPSD3212C, UPSD3212CV

ARCHITECTURE OVERVIEW
Memory Organization
The uPSD321X Devices's standard 8032 Core
has separate 64KB address spaces for Program
memory and Data Memory. Program memory is
where the 8032 executes instructions from. Data
memory is used to hold data variables. Flash
memory can be mapped in either program or data
space. The Flash memory consists of two flash
memory blocks: the main Flash (512Kbit) and the
Secondary Flash (128Kbit). Except during flash
memory programming or update, Flash memory
can only be read, not written to. A Page Register
is used to access memory beyond the 64K bytes

address space. Refer to the PSD Module for de-
tails on mapping of the Flash memory.
The 8032 core has two types of data memory (in-
ternal and external) that can be read and written.
The internal SRAM consists of 256 bytes, and in-
cludes the stack area.
The SFR (Special Function Registers) occupies
the upper 128 bytes of the internal SRAM, the reg-
isters can be accessed by Direct addressing only.
Another 2K bytes resides in the PSD Module that
can be mapped to any address space defined by
the user.

Figure 5. Memory Map and Address Space

AI07425

SECONDARY
FLASH

FLASH

MAIN

16KB

64KB

2KB

INT. RAM

EXT. RAM

Addressing

Indirect

Direct

Addressing

Direct

SFR

Internal RAM Space
(256 Bytes)

External RAM Space

(MOVX)

Flash Memory Space

UPSD3212C, UPSD3212CV

18/152

Registers
The 8032 has several registers; these are the Pro-
gram Counter (PC), Accumulator (A), B Register
(B), the Stack Pointer (SP), the Program Status
Word (PSW), General purpose registers (R0 to
R7), and DPTR (Data Pointer register).
Accumulator. The Accumulator is the 8-bit gen-
eral purpose register, used for data operation such
as transfer, temporary saving, and conditional
tests. The Accumulator can be used as a 16-bit
register with B Register as shown in Figure 6.
B Register. The B Register is the 8-bit general
purpose register, used for an arithmetic operation
such as multiply, division with the Accumulator
(see Figure 7).

Stack Pointer. The Stack Pointer Register is 8
bits wide. It is incremented before data is stored
during PUSH and CALL executions. While the
stack may reside anywhere in on-chip RAM, the
Stack Pointer is initialized to 07h after reset. This
causes the stack to begin at location 08h (see Fig-
ure 8).
Program Counter. The Program Counter is a 16-
bit wide which consists of two 8-bit registers, PCH
and PCL. This counter indicates the address of the
next instruction to be executed. In RESET state,
the program counter has reset routine address
(PCH:00h, PCL:00h).
Program Status Word. The Program Status
Word (PSW) contains several bits that reflect the
current state of the CPU and select Internal RAM
(00h to 1Fh: Bank0 to Bank3). The PSW is de-
scribed in Figure 9, page 19. It contains the Carry
Flag, the Auxiliary Carry Flag, the Half Carry (for
BCD operation), the general purpose flag, the
Register Bank Select Flags, the Overflow Flag,
and Parity Flag.
[Carry Flag, CY]. This flag stores any carry or not
borrow from the ALU of CPU after an arithmetic
operation and is also changed by the Shift Instruc-
tion or Rotate Instruction.
[Auxiliary Carry Flag, AC]. After operation, this is
set when there is a carry from Bit 3 of ALU or there
is no borrow from Bit 4 of ALU.

[Register Bank Select Flags, RS0, RS1]. This flags
select one of four bank(00~07H:bank0,
08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in
Internal RAM.
[Overflow Flag, OV]. This flag is set to '1' when an
overflow occurs as the result of an arithmetic oper-
ation involving signs. An overflow occurs when the
result of an addition or subtraction exceeds +127
(7Fh) or -128 (80h). The CLRV instruction clears
the overflow flag. There is no set instruction. When

the BIT instruction is executed, Bit 6 of memory is
copied to this flag.
[Parity Flag, P]. This flag reflects on number of Ac-
cumulator's "1." If the number of Accumulator's 1
is odd, P=0. otherwise, P=1. The sum of adding
Accumulator's 1 to P is always even.

R0~R7. General purpose 8-bit registers that are
locked in the lower portion of internal data area.
Data Pointer Register. Data Pointer Register is
16-bit wide which consists of two-8bit registers,
DPH and DPL. This register is used as a data
pointer for the data transmission with external data
memory in the PSD Module.

Figure 6. 8032 MCU Registers

Figure 7. Configuration of BA 16-bit Registers

Figure 8. Stack Pointer

AI06636

Accumulator

B Register

Stack Pointer

Program Counter

Program Status Word
General Purpose
Register (Bank0-3)
Data Pointer Register

PCH

DPTR(DPH)

PCL

PSW

R0-R7

DPTR(DPL)

AI06637

Two 8-bit Registers can be used as a "BA" 16-bit Registers

AI06638

SP (Stack Pointer) could be in 00h-FFh

00h

Stack Area (30h-FFh)

00h-FFh

Hardware Fixed

Bit 15

Bit 0

Bit 8 Bit 7

19/152

UPSD3212C, UPSD3212CV

Figure 9. PSW (Program Status Word) Register

Program Memory
The program memory consists of two Flash mem-
ory: 64KByte Main Flash and 16KByte of Second-
ary Flash. The Flash memory can be mapped to
any address space as defined by the user in the
PSDsoft Tool. It can also be mapped to Data
memory space during Flash memory update or
programming.
After reset, the CPU begins execution from loca-
tion 0000h. As shown in Figure 10, each interrupt
is assigned a fixed location in Program Memory.
The interrupt causes the CPU to jump to that loca-
tion, where it commences execution of the service
routine. External Interrupt 0, for example, is as-
signed to location 0003h. If External Interrupt 0 is
going to be used, its service routine must begin at
location 0003h. If the interrupt is not going to be
used, its service location is available as general
purpose Program Memory.
The interrupt service locations are spaced at 8-
byte intervals: 0003h for External Interrupt 0,
000Bh for Timer 0, 0013h for External Interrupt 1,
001Bh for Timer 1 and so forth. If an interrupt ser-
vice routine is short enough (as is often the case
in control applications), it can reside entirely within
that 8-byte interval (see Figure 10). Longer service
routines can use a jump instruction to skip over
subsequent interrupt locations, if other interrupts
are in use.
Data memory
The internal data memory is divided into four phys-
ically separated blocks: 256 bytes of internal RAM,
128 bytes of Special Function Registers (SFRs)
areas and 2K bytes (XRAM-PSD) in the PSD Mod-
ule.

RAM
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area.
Only one of these banks may be enabled at a time.
The next 16 bytes, locations 32 through 47, con-
tain 128 directly addressable bit locations. The
stack depth is only limited by the available internal
RAM space of 256 bytes.
XRAM-PSD
The 2K bytes of XRAM-PSD resides in the PSD
Module and can be mapped to any address space
through the DPLD (Decoding PLD) as defined by
the user in PSDsoft Development tool. The XRAM-
PSD has a battery backup feature that allow the
data to be retained in the event of a power lost.
The battery is connected to the Port C PC2 pin.
This pin must be configured in PSDSoft to be bat-
tery back-up.

Figure 10. Interrupt Location of Program
Memory

AI06639

Reset Value 00h

Parity Flag

Bit not assigned

Overflow Flag

(to select Bank0-3)

Carry Flag

Auxillary Carry Flag

General Purpose Flag

AC FO RS1 RS0 OV

MSB

LSB

PSW

AI06640

0000h

Reset

8 Bytes

·
·
·
·
·

Interrupt

Location

0003h

000Bh

0013h

008Bh

·
·
·
·

UPSD3212C, UPSD3212CV

20/152

SFR
The SFRs can only be addressed directly in the
address range from 80h to FFh. Table 15, page 32
gives an overview of the Special Function Regis-
ters. Sixteen address in the SFRs space are both-
byte and bit-addressable. The bit-addressable
SFRs are those whose address ends in 0h and 8h.
The bit addresses in this area are 80h to FFh.

Table 3. RAM Address

Addressing Modes
The addressing modes in uPSD321X Devices in-
struction set are as follows

Direct addressing

Indirect addressing

Immediate constants addressing

Indexed addressing

(1) Direct addressing. In a direct addressing the
operand is specified by an 8-bit address field in the
instruction. Only internal Data RAM and SFRs
(80~FFH RAM) can be directly addressed.
Example:

mov A, 3EH ;A <----- RAM[3E]

Figure 11. Direct Addressing

(2) Indirect addressing. In indirect addressing
the instruction specifies a register which contains
the address of the operand. Both internal and ex-
ternal RAM can be indirectly addressed. The ad-
dress register for 8-bit addresses can be R0 or R1
of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only
be the 16-bit "data pointer" register, DPTR.
Example:

mov @R1, #40 H ;[R1] <-----40H

Figure 12. Indirect Addressing

Byte Address
(in Hexadecimal)

Byte Address

(in Decimal)

FFh

255

30h

msb

Bit Address (Hex)

lsb

2Fh

2Eh

2Dh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22h

21h

20h

1Fh

18h

17h

10h

0Fh

08h

07h

00h

AI06641

3Eh

Program Memory

AI06642

55h

Program Memory

40h

21/152

UPSD3212C, UPSD3212CV

(3) Register addressing. The register banks,
containing registers R0 through R7, can be ac-
cessed by certain instructions which carry a 3-bit
register specification within the opcode of the in-
struction. Instructions that access the registers
this way are code efficient, since this mode elimi-
nates an address byte. When the instruction is ex-
ecuted, one of four banks is selected at execution
time by the two bank select bits in the PSW.
Example:

mov PSW, #0001000B ; select Bank0
mov A, #30H
mov R1, A

(4) Register-specific addressing. Some in-
structions are specific to a certain register. For ex-
ample, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address
byte is needed to point it. The opcode itself does
that.
(5) Immediate constants addressing. The val-
ue of a constant can follow the opcode in Program
memory.
Example:

mov A, #10H.

(6) Indexed addressing. Only Program memory
can be accessed with indexed addressing, and it
can only be read. This addressing mode is intend-
ed for reading look-up tables in Program memory.
A 16-bit base register (either DPTR or PC) points
to the base of the table, and the Accumulator is set
up with the table entry number. The address of the
table entry in Program memory is formed by add-
ing the Accumulator data to the base pointer (see
Figure 13).
Example:

movc A, @A+DPTR

Figure 13. Indexed Addressing

Arithmetic Instructions
The arithmetic instructions is listed in Table 4,
page 22. The table indicates the addressing
modes that can be used with each instruction to
access the <byte> operand. For example, the
ADD A, <byte> instruction can be written as:

ADD a, 7FH (direct addressing)

ADD A, @R0 (indirect addressing)
ADD a, R7 (register addressing)
ADD A, #127 (immediate constant)

Note: Any byte in the internal Data Memory space
can be incremented without going through the Ac-
cumulator.
One of the INC instructions operates on the 16-bit
Data Pointer. The Data Pointer is used to generate
16-bit addresses for external memory, so being
able to increment it in one 16-bit operations is
a useful feature.
The MUL AB instruction multiplies the Accumula-
tor by the data in the B register and puts the 16-bit
product into the concatenated B and Accumulator
registers.
The DIV AB instruction divides the Accumulator by
the data in the B register and leaves the 8-bit quo-
tient in the Accumulator, and the 8-bit remainder in
the B register.
In shift operations, dividing a number by 2n shifts
its "n" bits to the right. Using DIV AB to perform the
division completes the shift in 4?s and leaves the
B register holding the bits that were shifted out.
The DAA instruction is for BCD arithmetic opera-
tions. In BCD arithmetic, ADD and ADDC instruc-
tions should always be followed by a DAA
operation, to ensure that the result is also in BCD.
Note: DAA will not convert a binary number to
BCD. The DAA operation produces a meaningful
result only as the second step in the addition of
two BCD bytes.

AI06643

3Eh

Program Memory

ACC

DPTR

3Ah

1E73h

UPSD3212C, UPSD3212CV

22/152

Table 4. Arithmetic Instructions

Logical Instructions
Table 5, page 23 shows list of uPSD321X Devices
logical instructions. The instructions that perform
Boolean operations (AND, OR, Exclusive OR,
NOT) on bytes perform the operation on a bit-by-
bit basis. That is, if the Accumulator contains
00110101B and byte contains 01010011B, then:

ANL A, <byte>

will leave the Accumulator holding 00010001B.
The addressing modes that can be used to access
the <byte> operand are listed in Table 5.
The ANL A, <byte> instruction may take any of the
forms:

ANL A,7FH(direct addressing)
ANL A, @R1 (indirect addressing)

ANL A,R6 (register addressing)
ANL A,#53H (immediate constant)

Note: Boolean operations can be performed on
any byte in the internal Data Memory space with-
out going through the Accumulator. The XRL
<byte>, #data instruction, for example, offers a
quick and easy way to invert port bits, as in

XRL P1, #0FFH.

If the operation is in response to an interrupt, not
using the Accumulator saves the time and effort to
push it onto the stack in the service routine.
The Rotate instructions (RL A, RLC A, etc.) shift
the Accumulator 1 bit to the left or right. For a left
rotation, the MSB rolls into the LSB position. For a
right rotation, the LSB rolls into the MSB position.
The SWAP A instruction interchanges the high
and low nibbles within the Accumulator. This is a
useful operation in BCD manipulations. For exam-
ple, if the Accumulator contains a binary number
which is known to be less than 100, it can be quick-
ly converted to BCD by the following code:

MOVE B,#10
DIV AB
SWAP A
ADD A,B

Dividing the number by 10 leaves the tens digit in
the low nibble of the Accumulator, and the ones
digit in the B register. The SWAP and ADD instruc-
tions move the tens digit to the high nibble of the
Accumulator, and the ones digit to the low nibble.

Mnemonic

Operation

Addressing Modes

Dir.

Ind.

Reg.

Imm

ADD A,<byte>

A = A + <byte>

ADDC A,<byte>

A = A + <byte> + C

SUBB A,<byte>

A = A <byte> C

INC

A = A + 1

Accumulator only

INC <byte>

<byte> = <byte> + 1

INC DPTR

DPTR = DPTR + 1

Data Pointer only

DEC

A = A 1

Accumulator only

DEC <byte>

<byte> = <byte> 1

MUL AB

B:A = B x A

Accumulator and B only

DIV AB

A = Int[ A / B ]

B = Mod[ A / B ]

Accumulator and B only

DA A

Decimal Adjust

Accumulator only

UPSD3212C, UPSD3212CV

24/152

Data Transfers
Internal RAM. Table 6 shows the menu of in-
structions that are available for moving data
around within the internal memory spaces, and the
addressing modes that can be used with each
one. The MOV <dest>, <src> instruction allows
data to be transferred between any two internal
RAM or SFR locations without going through the
Accumulator. Remember, the Upper 128 bytes of
data RAM can be accessed only by indirect ad-
dressing, and SFR space only by direct address-
ing.
Note: In uPSD321X Devices, the stack resides in
on-chip RAM, and grows upwards. The PUSH in-
struction first increments the Stack Pointer (SP),
then copies the byte into the stack. PUSH and
POP use only direct addressing to identify the byte
being saved or restored, but the stack itself is ac-
cessed by indirect addressing using the SP regis-
ter. This means the stack can go into the Upper
128 bytes of RAM, if they are implemented, but not
into SFR space.
The Data Transfer instructions include a 16-bit
MOV that can be used to initialize the Data Pointer
(DPTR) for look-up tables in Program Memory.

The XCH A, <byte> instruction causes the Accu-
mulator and ad-dressed byte to exchange data.
The XCHD A, @Ri instruction is similar, but only
the low nibbles are involved in the exchange. To
see how XCH and XCHD can be used to facilitate
data manipulations, consider first the problem of
shifting and 8-digit BCD number two digits to the
right. Table 8 shows how this can be done using
XCH instructions. To aid in understanding how the
code works, the contents of the registers that are
holding the BCD number and the content of the
Accumulator are shown alongside each instruction
to indicate their status after the instruction has
been executed.
After the routine has been executed, the Accumu-
lator contains the two digits that were shifted out
on the right. Doing the routine with direct MOVs
uses 14 code bytes. The same operation with
XCHs uses only 9 bytes and executes almost
twice as fast. To right-shift by an odd number of
digits, a one-digit must be executed. Table 9
shows a sample of code that will right-shift a BCD
number one digit, using the XCHD instruction.
Again, the contents of the registers holding the
number and of the accumulator are shown along-
side each instruction.

Table 6. Data Transfer Instructions that Access Internal Data Memory Space

Mnemonic

Operation

Addressing Modes

Dir.

Ind.

Reg.

Imm

MOV A,<src>

A = <src>

MOV <dest>,A

<dest> = A

MOV <dest>,<src>

MOV DPTR,#data16

DPTR = 16-bit immediate constant

PUSH <src>

INC SP; MOV "@SP",<src>

POP <dest>

MOV <dest>,"@SP"; DEC SP

XCH A,<byte>

Exchange contents of A and <byte>

XCHD A,@Ri

Exchange low nibbles of A and @Ri

25/152

UPSD3212C, UPSD3212CV

First, pointers R1 and R0 are set up to point to the
two bytes containing the last four BCD digits. Then
a loop is executed which leaves the last byte, loca-
tion 2EH, holding the last two digits of the shifted
number. The pointers are decremented, and the
loop is repeated for location 2DH. The CJNE in-
struction (Compare and Jump if Not equal) is a
loop control that will be described later. The loop
executed from LOOP to CJNE for R1 = 2EH, 2DH,
2CH, and 2BH. At that point the digit that was orig-
inally shifted out on the right has propagated to lo-
cation 2AH. Since that location should be left with
0s, the lost digit is moved to the Accumulator.

Table 7. Shifting a BCD Number Two Digits to
the Right (using direct MOVs: 14 bytes)

Table 8. Shifting a BCD Number Two Digits to
the Right (using direct XCHs: 9 bytes)

Table 9. Shifting a BCD Number One Digit to the Right

ACC

MOV

A,2Eh

MOV

2Eh,2Dh

MOV

2Dh,2Ch

MOV

2Ch,2Bh

MOV

2Bh,#0

ACC

CLR

XCH

A,2Bh

XCH

A,2Ch

XCH

A,2Dh

XCH

A,2Eh

ACC

MOV

R1,#2Eh

MOV

R0,#2Dh

; loop for R1 = 2Eh

LOOP:

MOV

A,@R1

XCHD

A,@R0

SWAP

MOV

@R1,A

DEC

CNJE

R1,#2Ah,LOOP

; loop for R1 = 2Dh

; loop for R1 = 2Ch

; loop for R1 = 2Bh

CLR

XCH

A,2Ah

UPSD3212C, UPSD3212CV

26/152

External RAM. Table 10 shows a list of the Data
Transfer instructions that access external Data
Memory. Only indirect addressing can be used.
The choice is whether to use a one-byte address,
@Ri, where Ri can be either R0 or R1 of the se-
lected register bank, or a two-byte
address, @DTPR.
Note: In all external Data RAM accesses, the Ac-
cumulator is always either the destination or
source of the data.

Lookup Tables. Table 11 shows the two instruc-
tions that are available for reading lookup tables in
Program Memory. Since these instructions access
only Program Memory, the lookup tables can only
be read, not updated.
The mnemonic is MOVC for "move constant." The
first MOVC instruction in Table 11 can accommo-
date a table of up to 256 entries numbered 0
through 255. The number of the desired entry is
loaded into the Accumulator, and the Data Pointer
is set up to point to the beginning of the table.
Then:

MOVC A, @A+DPTR

copies the desired table entry into the Accumula-
tor.

The other MOVC instruction works the same way,
except the Program Counter (PC) is used as the
table base, and the table is accessed through a
subroutine. First the number of the desired en-try
is loaded into the Accumulator, and the subroutine
is called:

MOV A , ENTRY NUMBER
CALL TABLE

The subroutine "TABLE" would look like this:

TABLE: MOVC A , @A+PC
RET

The table itself immediately follows the RET (re-
turn) instruction is Program Memory. This type of
table can have up to 255 entries, numbered 1
through 255. Number 0 cannot be used, because
at the time the MOVC instruction is executed, the
PC contains the address of the RET instruction.
An entry numbered 0 would be the RET opcode it-
self.

Table 10. Data Transfer Instruction that Access External Data Memory Space

Table 11. Lookup Table READ Instruction

Address Width

Mnemonic

Operation

8 bits

MOVX A,@Ri

READ external RAM @Ri

8 bits

MOVX @Ri,A

WRITE external RAM @Ri

16 bits

MOVX A,@DPTR

READ external RAM @DPTR

16 bits

MOVX @DPTR,a

WRITE external RAM @DPTR

Mnemonic

Operation

MOVC A,@A+DPTR

READ program memory at (A+DPTR)

MOVC A,@A+PC

READ program memory at (A+PC)

27/152

UPSD3212C, UPSD3212CV

Boolean Instructions
The uPSD323X Devices contain a complete Bool-
ean (single-bit) processor. One page of the inter-
nal RAM contains 128 addressable bits, and the
SFR space can support up to 128 addressable bits
as well. All of the port lines are bit-addressable,
and each one can be treated as a separate single-
bit port. The instructions that access these bits are
not just conditional branches, but a complete
menu of move, set, clear, complement, OR and
AND instructions. These kinds of bit operations
are not easily obtained in other architectures with
any amount of byte-oriented software.
The instruction set for the Boolean processor is
shown in Table 12. All bits accesses are by direct
addressing.
Bit addresses 00h through 7Fh are in the Lower
128, and bit addresses 80h through FFh are in
SFR space.
Note how easily an internal flag can be moved to
a port pin:

MOV C,FLAG
MOV P1.0,C

In this example, FLAG is the name of any addres-
sable bit in the Lower 128 or SFR space. An I/O
line (the LSB of Port 1, in this case) is set or
cleared depending on whether the Flag Bit is '1' or
'0.'
The Carry Bit in the PSW is used as the single-bit
Accumulator of the Boolean processor. Bit instruc-
tions that refer to the Carry Bit as C assemble as
Carry-specific instructions (CLR C, etc.). The Car-
ry Bit also has a direct address, since it resides in
the PSW register, which is bit-addressable.
Note: The Boolean instruction set includes ANL
and ORL operations, but not the XRL (Exclusive
OR) operation. An XRL operation is simple to im-
plement in software. Suppose, for example, it is re-
quired to form the Exclusive OR of two bits:

C = bit 1 .XRL. bit2

The software to do that could be as follows:

MOV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)

First, Bit 1 is moved to the Carry. If bit2 = 0, then
C now contains the correct result. That is, Bit 1
.XRL. bit2 = bit1 if bit2 = 0. On the other hand, if
bit2 = 1, C now contains the complement of the
correct result. It need only be inverted (CPL C) to
complete the operation.
This code uses the JNB instruction, one of a series
of bit-test instructions which execute a jump if the

addressed bit is set (JC, JB, JBC) or if the ad-
dressed bit is not set (JNC, JNB). In the above
case, Bit 2 is being tested, and if bit2 = 0, the CPL
C instruction is jumped over.
JBC executes the jump if the addressed bit is set,
and also clears the bit. Thus a flag can be tested
and cleared in one operation. All the PSW bits are
directly addressable, so the Parity Bit, or the gen-
eral-purpose flags, for example, are also available
to the bit-test instructions.

Relative Offset
The destination address for these jumps is speci-
fied to the assembler by a label or by an actual ad-
dress in Program memory. How-ever, the
destination address assembles to a relative offset
byte. This is a signed (two's complement) offset
byte which is added to the PC in two's complement
arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127
Program Memory bytes relative to the first byte fol-
lowing the instruction.

Table 12. Boolean Instructions

Mnemonic

Operation

ANL C,bit

C = A .AND. bit

ANL C,/bit

C = C .AND. .NOT. bit

ORL C,bit

C = A .OR. bit

ORL C,/bit

C = C .OR. .NOT. bit

MOV C,bit

C = bit

MOV bit,C

bit = C

CLR C

C = 0

CLR bit

bit = 0

SETB C

C = 1

SETB bit

bit = 1

CPL C

C = .NOT. C

CPL bit

bit = .NOT. bit

JC rel

Jump if C =1

JNC rel

Jump if C = 0

JB bit,rel

Jump if bit =1

JNB bit,rel

Jump if bit = 0

JBC bit,rel

Jump if bit = 1; CLR bit

UPSD3212C, UPSD3212CV

28/152

Jump Instructions
Table 13 shows the list of unconditional jump in-
structions. The table lists a single "JMP add" in-
struction, but in fact there are three SJMP, LJMP,
and AJMP, which differ in the format of the desti-
nation address. JMP is a generic mnemonic which
can be used if the programmer does not care
which way the jump is en-coded.
The SJMP instruction encodes the destination ad-
dress as a relative offset, as described above. The
instruction is 2 bytes long, consisting of the op-
code and the relative offset byte. The jump dis-
tance is limited to a range of -128 to +127 bytes
relative to the instruction following the SJMP.
The LJMP instruction encodes the destination ad-
dress as a 16-bit constant. The instruction is 3
bytes long, consisting of the opcode and two ad-
dress bytes. The destination address can be any-
where in the 64K Program Memory space.
The AJMP instruction encodes the destination ad-
dress as an 11-bit constant. The instruction is 2
bytes long, consisting of the opcode, which itself
contains 3 of the 11 address bits, followed by an-
other byte containing the low 8 bits of the destina-
tion address. When the instruction is executed,
these 11 bits are simply substituted for the low 11
bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same
2K block as the instruction following the AJMP.
In all cases the programmer specifies the destina-
tion address to the assembler in the same way: as
a label or as a 16-bit constant. The assembler will
put the destination address into the correct format
for the given instruction. If the format required by
the instruction will not support the distance to the
specified destination address, a "Destination out
of range" message is written into the List file.
The JMP @A+DPTR instruction supports case
jumps. The destination address is computed at ex-
ecution time as the sum of the 16-bit DPTR regis-
ter and the Accumulator. Typically. DPTR is set up
with the address of a jump table. In a 5-way
branch, for ex-ample, an integer 0 through 4 is
loaded into the Accumulator. The code to be exe-
cuted might be as follows:

MOV DPTR,#JUMP TABLE
MOV A,INDEX_NUMBER
RL A
JMP @A+DPTR

The RL A instruction converts the index number (0
through 4) to an even number on the range 0
through 8, because each entry in the jump table is
2 bytes long:

JUMP TABLE:
AJMP CASE 0
AJMP CASE 1
AJMP CASE 2

AJMP CASE 3
AJMP CASE 4

Table 13 shows a single "CALL addr" instruction,
but there are two of them, LCALL and ACALL,
which differ in the format in which the subroutine
address is given to the CPU. CALL is a generic
mnemonic which can be used if the programmer
does not care which way the address is encoded.
The LCALL instruction uses the 16-bit address for-
mat, and the subroutine can be anywhere in the
64K Program Memory space. The ACALL instruc-
tion uses the 11-bit format, and the subroutine
must be in the same 2K block as the instruction fol-
lowing the ACALL.
In any case, the programmer specifies the subrou-
tine address to the assembler in the same way: as
a label or as a 16-bit constant. The assembler will
put the address into the correct format for the giv-
en instructions.
Subroutines should end with a RET instruction,
which returns execution to the instruction following
the CALL.
RETI is used to return from an interrupt service
routine. The only difference between RET and
RETI is that RETI tells the interrupt control system
that the interrupt in progress is done. If there is no
interrupt in progress at the time RETI is executed,
then the RETI is functionally identical to RET.

Table 13. Unconditional Jump Instructions

Mnemonic

Operation

JMP addr

Jump to addr

JMP @A+DPTR

Jump to A+DPTR

CALL addr

Call Subroutine at addr

RET

Return from subroutine

RETI

Return from Interrupt

NOP

No operation

29/152

UPSD3212C, UPSD3212CV

Table 14 shows the list of conditional jumps avail-
able to the uPSD321X Devices user. All of these
jumps specify the destination address by the rela-
tive offset method, and so are limited to a jump dis-
tance of -128 to +127 bytes from the instruction
following the conditional jump instruction. Impor-
tant to note, however, the user specifies to the as-
sembler the actual destination address the same
way as the other jumps: as a label or a 16-bit con-
stant.
There is no Zero Bit in the PSW. The JZ and JNZ
instructions test the Accumulator data for that con-
dition.
The DJNZ instruction (Decrement and Jump if Not
Zero) is for loop control. To execute a loop N
times, load a counter byte with N and terminate the
loop with a DJNZ to the beginning of the loop, as
shown below for N = 10:

MOV COUNTER,#10
LOOP: (begin loop)

(end loop)

DJNZ COUNTER, LOOP
(continue)

The CJNE instruction (Compare and Jump if Not
Equal) can also be used for loop control as in Ta-
ble 9. Two bytes are specified in the operand field
of the instruction. The jump is executed only if the
two bytes are not equal. In the example of Table 9
Shifting a BCD Number One Digits to the Right,
the two bytes were data in R1 and the constant
2Ah. The initial data in R1 was 2Eh.

Every time the loop was executed, R1 was decre-
mented, and the looping was to continue until the
R1 data reached 2Ah.
Another application of this instruction is in "greater
than, less than" comparisons. The two bytes in the
operand field are taken as unsigned integers. If the
first is less than the second, then the Carry Bit is
set (1). If the first is greater than or equal to the
second, then the Carry Bit is cleared.
Machine Cycles
A machine cycle consists of a sequence of six
states, numbered S1 through S6. Each state time
lasts for two oscillator periods. Thus, a machine
cycle takes 12 oscillator periods or 1µs if the oscil-
lator frequency is 12MHz. Refer to Figure 14, page
30.
Each state is divided into a Phase 1 half and a
Phase 2 half. State Sequence in uPSD321X De-
vices shows that retrieve/execute sequences in
states and phases for various kinds of instructions.
Normally two program retrievals are generated
during each machine cycle, even if the instruction
being executed does

not

require it. If the instruc-

tion being executed does not need more code
bytes, the CPU simply ignores the extra retrieval,
and the Program Counter is not incremented.
Execution of a one-cycle instruction (Figure 14,
page 30) begins during State 1 of the machine cy-
cle, when the opcode is latched into the Instruction
Register. A second retrieve occurs during S4 of
the same machine cycle. Execution is complete at
the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles
to execute. No program retrieval is generated dur-
ing the second cycle of a MOVX instruction. This
is the only time program retrievals are skipped.
The retrieve/execute sequence for MOVX instruc-
tion is shown in Figure 14, page 30 (d).

Table 14. Conditional Jump Instructions

Mnemonic

Operation

Addressing Modes

Dir.

Ind.

Reg.

Imm

JZ rel

Jump if A = 0

Accumulator only

JNZ rel

Jump if A

Accumulator only

DJNZ <byte>,rel

Decrement and jump if not zero

CJNE A,<byte>,rel

Jump if A

<byte>

CJNE <byte>,#data,rel

Jump if <byte>

#data

31/152

UPSD3212C, UPSD3212CV

UPSD3200 HARDWARE DESCRIPTION
The uPSD321X Devices has a modular architec-
ture with two main functional modules: the MCU
Module and the PSD Module. The MCU Module
consists of a standard 8032 core, peripherals and
other system supporting functions. The PSD Mod-
ule provides configurable Program and Data mem-
ories to the 8032 CPU core. In addition, it has its
own set of I/O ports and a PLD with 16 macrocells
for general logic implementation. Ports A,B,C, and
D are general purpose programmable I/O ports

that have a port architecture which is different from
Ports 0-4 in the MCU Module.
The PSD Module communicates with the CPU
Core through the internal address, data bus (A0-
A15, D0-D7) and control signals (RD_, WR_,
PSEN_ , ALE, RESET_). The user defines the De-
coding PLD in the PSDsoft Development Tool and
can map the resources in the PSD Module to any
program or data address space.

Figure 15. uPSD321X Devices Functional Modules

AI07426

Channel

ADC

512Kb

Main Flash

Decode PLD

16Kb

SRAM

CPLD - 16 MACROCELLS

JTAG ISP

Port 1

Port 3

2 UARTs

Interrupt

3 Timer /

Counters

256 Byte SRAM

8032 Core

Port 3, UART,

Intr, Timers,I2C

PSD Internal Bus

8032 Internal Bus

Port 1, Timers and

2nd UART and ADC

PWM

Channels

Port 4 PWM

Port A & B, PLD

I/O and GPIO

Port D

GPIO

Port C,

JTAG, PLD I/O

and GPIO

VCC, GND,

XTAL

128Kb

Secondary

Flash

Dedicated

Pins

I2C

Port 0, 2
Ext. Bus

Reset Logic
LVD & WDT

Bus

Interface

Reset

D0-D7

A0-A15

RD,PSEN

WR,ALE

Page Register

PSD MODULE

MCU MODULE

UPSD3212C, UPSD3212CV

32/152

MCU MODULE DISCRIPTION
This section provides a detail description of the
MCU Module system functions and Peripherals,
including:

Special Function Registers

Timers/Counter

Interrupts

PWM

Supervisory Function (LVD and Watchdog)

USART

Power Saving Modes

C Bus

On-chip Oscillator

ADC

I/O Ports

Special Function Registers
A map of the on-chip memory area called the Spe-
cial Function Register (SFR) space is shown in Ta-
ble 15.
Note: In the SFRs not all of the addresses are oc-
cupied. Unoccupied addresses are not implement-
ed on the chip. READ accesses to these
addresses will in general return random data, and
WRITE accesses will have no effect. User soft-
ware should write '0s' to these unimplemented lo-
cations.

Table 15. SFR Memory Map

Note: 1. Register can be bit addressing

(1)

ACC

(1)

S2CON

S2STA

S2DAT

S2ADR

PSW

(1)

T2CON

(1)

T2MOD

RCAP2L

RCAP2H

TL2

TH2

(1)

PSCL0L

PSCL0H

PSCL1L

PSCL1H

IPA

(1)

PWM4P

PWM4W

WDKEY

(1)

PWMCON

PWM0

PWM1

PWM2

PWM3

WDRST

IEA

SCON

SBUF

SCON2

SBUF2

(1)

P1SFS

P3SFS

P4SFS

ASCL

ADAT

ACON

TCON

(1)

TMOD

TL0

TL1

TH0

TH1

(1)

DPL

DPH

PCON

33/152

UPSD3212C, UPSD3212CV

Table 16. List of all SFR

SFR

Addr

Reg Name

Bit Register Name

Reset

Value

Comments

Port 0

Stack Ptr

DPL

Data Ptr Low

DPH

Data Ptr High

PCON

SMOD

SMOD1

LVREN ADSFINT RCLK1

TCLK1

IDLE

Power Ctrl

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Timer / Cntr

Control

TMOD

Gate

C/T

Gate

C/T

Timer / Cntr

Mode Control

TL0

Timer 0 Low

TL1

Timer 1 Low

TH0

Timer 0 High

TH1

Timer 1 High

Port 1

P1SFS

P1S7

P1S6

P1S5

P1S4

Port 1 Select

P3SFS

P3S7

P3S6

Port 3 Select

P4SFS

P4S7

P4S6

P4S5

P4S4

P4S3

P4S2

P4S1

P4S0

Port 4 Select

ASCL

8-bit

Prescaler for

ADC clock

ADAT

ADAT7

ADAT6

ADAT5

ADAT4

ADAT3

ADAT2

ADAT1

ADAT0

ADC Data

ACON

ADEN

ADS1

ADS0

ADST

ADSF

ADC Control

SCON

SM0

SM1

SM2

REN

TB8

RB8

Serial Control

SBUF

Serial Buffer

SCON2

SM0

SM1

SM2

REN

TB8

RB8

2nd UART

Ctrl Register

SBUF2

2nd UART

Serial Buffer

Port 2

A1 PWMCON

PWML

PWMP

PWME

CFG4

CFG3

CFG2

CFG1

CFG0

PWM Control

Polarity

PWM0

Output Duty

Cycle

UPSD3212C, UPSD3212CV

34/152

PWM1

Output Duty

Cycle

PWM2

Output Duty

Cycle

PWM3

Output Duty

Cycle

WDRST

Watch Dog

Reset

IEA

ES2

Interrupt

Enable (2nd)

ET2

ET1

EX1

ET0

EX0

Interrupt

Enable

PWM4P

PWM 4

Period

PWM4W

PWM 4 Pulse

Width

WDKEY

Watch Dog

Key Register

Port 3

PSCL0L

Prescaler 0

Low (8-bit)

PSCL0H

Prescaler 0

High (8-bit)

PSCL1L

Prescaler 1

Low (8-bit)

PSCL1H

Prescaler 1

High (8-bit)

IPA

PS2

PI2C

Interrupt

Priority (2nd)

PT2

PT1

PX1

PT0

PX0

Interrupt

Priority

New Port 4

T2CON

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Timer 2

Control

T2MOD

DCEN

Timer 2 Mode

RCAP2L

Timer 2

Reload low

RCAP2H

Timer 2

Reload High

SFR

Addr

Reg Name

Bit Register Name

Reset

Value

Comments

UPSD3212C, UPSD3212CV

36/152

Table 17. PSD Module Register Address Offset

CSIOP

Addr

Offset

Register Name

Bit Register Name

Reset

Value

Comments

Data In (Port A)

Reads Port pins as input

Control (Port A)

Configure pin between I/O or Address Out Mode. Bit = 0 selects I/

Data Out (Port A)

Latched data for output to Port pins, I/O Output Mode

Direction (Port A)

Configures Port pin as input or output. Bit = 0 selects input

Drive (Port A)

Configures Port pin between CMOS, Open Drain or Slew rate. Bit

= 0 selects CMOS

Input Macrocell

(Port A)

Reads latched value on Input Macrocells

Enable Out

(Port A)

Reads the status of the output enable control to the Port pin driver.

Bit = 0 indicates pin is in input mode.

Data In (Port B)

Control (Port B)

Data Out (Port B)

Direction (Port B)

Drive (Port B)

Input Macrocell

(Port B)

Enable Out

(Port B)

Data In (Port C)

Data Out (Port C)

Direction (Port C)

Drive (Port C)

Input Macrocell

(Port C)

Enable Out

(Port C)

Data In (Port D)

Only Bit 1 and

2 are used

Data Out (Port D)

Only Bit 1 and

2 are used

Direction (Port D)

Only Bit 1 and

2 are used

Drive (Port D)

Only Bit 1 and

2 are used

Enable Out

(Port D)

Only Bit 1 and

2 are used

Output

Macrocells AB

37/152

UPSD3212C, UPSD3212CV

Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft)

* indicates bit is not used and need to set to '0.'

Output

Macrocells BC

Mask Macrocells

Primary Flash

Protection

Sec3_

Prot

Sec2_

Prot

Sec1_

Prot

Sec0_

Prot

Bit = 1 sector

is protected

Secondary Flash

Protection

Security

_Bit

Sec1_

Prot

Sec0_

Prot

Security Bit =

1 device is

secured

PMMR0

PLD

Mcells

clk

PLD

array-

clk

PLD

Turbo

APD

enable

Control PLD

power

consumption

PMMR2

PLD

array

Ale

PLD
array

Cntl2

PLD
array

Cntl1

PLD
array

Cntl0

Blocking

inputs to PLD

array

Page

Page Register

Periph-

mode

FL_

data

Boot_

data

FL_

code

Boot_

code

SR_

code

Configure

8032 Program

and Data

Space

CSIOP

Addr

Offset

Register Name

Bit Register Name

Reset

Value

Comments

UPSD3212C, UPSD3212CV

38/152

INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows (see Figure 16, page 39).

INT0 External Interrupt

2nd USART Interrupt

Timer 0 Interrupt

C Interrupt

INT1 External Interrupt (or ADC Interrupt)

Timer 1 Interrupt

USART Interrupt

Timer 2 Interrupt

External Int0
The INT0 can be either level-active or transition-

active depending on Bit IT0 in register TCON.
The flag that actually generates this interrupt is
Bit IE0 in TCON.

When an external interrupt is generated, the

corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.

If the interrupt was level activated then the inter-

rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de-
activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.

Timer 0 and 1 Interrupts
Timer 0 and Timer 1 Interrupts are generated by

TF0 and TF1 which are set by an overflow of
their respective Timer/Counter registers (except
for Timer 0 in Mode 3).

These flags are cleared by the internal hard-

ware when the interrupt is serviced.

Timer 2 Interrupt
Timer 2 Interrupt is generated by TF2 which is

set by an overflow of Timer 2. This flag has to be
cleared by the software - not by hardware.

It is also generated by the T2EX signal (Timer 2

External Interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.

C Interrupt

The interrupt of the I

C is generated by Bit INTR

in the register S2STA.

This flag is cleared by hardware.

External Int1
The INT1 can be either level active or transition

active depending on Bit IT1 in register TCON.
The flag that actually generates this interrupt is
Bit IE1 in TCON.

When an external interrupt is generated, the

corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.

If the interrupt was level activated then the inter-

The ADC can take over the External INT1 to

generate an interrupt on conversion being com-
pleted

UPSD3212C, UPSD3212CV

40/152

USART Interrupt
The USART Interrupt is generated by RI (Re-

ceive Interrupt) OR TI (Transmit Interrupt).

When the USART Interrupt is generated, the

corresponding request flag must be cleared by
the software. The interrupt service routine will
have to check the various USART registers to
determine the source and clear the correspond-
ing flag.

Both USART's are identical, except for the addi-

tional interrupt controls in the Bit 4 of the addi-
tional interrupt control registers (A7H, B7H).

Interrupt Priority Structure

Each interrupt source can be assigned one of two
priority levels. Interrupt priority levels are defined
by the interrupt priority special function register IP
and IPA.
0 = low priority
1 = high priority

A low priority interrupt may be interrupted by a
high priority interrupt level interrupt. A high priority
interrupt routine cannot be interrupted by any oth-
er interrupt source. If two interrupts of different pri-
ority occur simultaneously, the high priority level
request is serviced. If requests of the same priority
are received simultaneously, an internal polling
sequence determines which request is serviced.
Thus, within each priority level, there is a second
priority structure determined by the polling se-
quence.
Interrupts Enable Structure
Each interrupt source can be individually enabled
or disabled by setting or clearing a bit in the inter-
rupt enable special function register IE and IEA. All
interrupt source can also be globally disabled by
the clearing Bit EA in IE (see Table 19). Please
see Tables 20, 21, 22, and 23 for individual bit de-
scriptions.

Table 18. Priority Levels

Table 19. SFR Register

Source

Priority with Level

Int0

0 (highest)

2nd USART

Timer 0

I²C

Int1

reserved

Timer 1

reserved

1st USART

Timer 2+EXF2

9 (lowest)

SFR

Addr

Reg

Name

Bit Register Name

Reset

Value

Comments

IEA

ES2

Interrupt

Enable (2nd)

ET2

ET1

EX1

ET0

EX0

Interrupt

Enable

IPA

PS2

Interrupt

Priority (2nd)

PT2

PT1

PX1

PT0

PX0

Interrupt

Priority

41/152

UPSD3212C, UPSD3212CV

Table 20. Description of the IE Bits.

Table 21. Description of the IEA Bits

Table 22. Description of the IP Bits

Bit

Symbol

Function

Disable all interrupts:
0: no interrupt with be acknowledged
1: each interrupt source is individually enabled or disabled by setting or clearing its
enable bit

Reserved

ET2

Enable Timer 2 Interrupt

Enable USART Interrupt

ET1

Enable Timer 1 Interrupt

EX1

Enable External Interrupt (Int1)

ET0

Enable Timer 0 Interrupt

EX0

Enable External Interrupt (Int0)

Bit

Symbol

Function

Not used

ES2

Enable 2nd USART Interrupt

Not used

EI2C

Enable I²C Interrupt

Not used

Bit

Symbol

Function

Reserved

PT2

Timer 2 Interrupt priority level

USART Interrupt priority level

PT1

Timer 1 Interrupt priority level

PX1

External Interrupt (Int1) priority level

PT0

Timer 0 Interrupt priority level

PX0

External Interrupt (Int0) priority level

UPSD3212C, UPSD3212CV

42/152

Table 23. Description of the IPA Bits

How Interrupts are Handled
The interrupt flags are sampled at S5P2 of every
machine cycle. The samples are polled during fol-
lowing machine cycle. If one of the flags was in a
set condition at S5P2 of the preceding cycle, the
polling cycle will find it and the interrupt system will
generate an LCALL to the appropriate service rou-
tine, provided this H/W generated LCALL is not
blocked by any of the following conditions:
An interrupt of equal priority or higher priority

level is already in progress.

The current machine cycle is not the final cycle

in the execution of the instruction in progress.

The instruction in progress is RETI or any ac-

cess to the interrupt priority or interrupt enable
registers.

The polling cycle is repeated with each machine
cycle, and the values polled are the values that
were present at S5P2 of the previous machine cy-
cle.
Note: If an interrupt flag is active but being re-
sponded to for one of the above mentioned condi-
tions, if the flag is still inactive when the blocking
condition is removed, the denied interrupt will not
be serviced. In other words, the fact that the inter-
rupt flag was once active but not serviced is not re-
membered. Every polling cycle is new.
The processor acknowledges an interrupt request
by executing a hardware generated LCALL to the
appropriate service routine. The hardware gener-
ated LCALL pushes the contents of the Program
Counter on to the stack (but it does not save the

PSW) and reloads the PC with an address that de-
pends on the source of the interrupt being vec-
tored to as shown in Table 24.
Execution proceeds from that location until the
RETI instruction is encountered. The RETI instruc-
tion informs the processor that the interrupt routine
is no longer in progress, then pops the top two
bytes from the stack and reloads the Program
Counter. Execution of the interrupted program
continues from where it left off.
Note: A simple RET instruction would also return
execution to the interrupted program, but it would
have left the interrupt control system thinking an
interrupt was still in progress, making future inter-
rupts impossible.

Table 24. Vector Addresses

Bit

Symbol

Function

Not used

PS2

2nd USART Interrupt priority level

Not used

PI2C

I²C Interrupt priority level

Not used

Source

Vector Address

Int0

0003h

2nd USART

004Bh

Timer 0

000Bh

I²C

0043h

Int1

0013h

Timer 1

001Bh

1st USART

0023h

Timer 2+EXF2

002Bh

43/152

UPSD3212C, UPSD3212CV

POWER-SAVING MODE
Two software selectable modes of reduced power
consumption are implemented (see Table 25).
Idle Mode
The following Functions are Switched Off.
CPU (Halted)
The following Function Remain Active During Idle
Mode.
External Interrupts
Timer 0, Timer 1, Timer 2
PWM Units

USART
8-bit ADC
I

C Interface

Note: Interrupt or RESET terminates the Idle
Mode.
Power-Down Mode
System Clock Halted
LVD Logic Remains Active
SRAM contents remains unchanged
The SFRs retain their value until a RESET is as-

serted

Note: The only way to exit Power-down Mode is a
RESET.
Power Control Register
The Idle and Power-down Modes are activated by
software via the PCON register (see Tables 26
and Table 27, page 44).

Idle Mode
The instruction that sets PCON.0 is the last in-
struction executed in the normal operating mode
before Idle Mode is activated. Once in the Idle
Mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM and All other registers
maintain their data during Idle Mode.
There are three ways to terminate the Idle Mode.
Activation of any enabled interrupt will cause

PCON.0 to be cleared by hardware terminating
Idle mode. The interrupt is serviced, and follow-
ing return from interrupt instruction RETI, the
next instruction to be executed will be the one
which follows the instruction that wrote a logic '1'
to PCON.0.

External hardware reset: the hardware reset is

required to be active for two machine cycle to
complete the RESET operation.

Internal reset: the microcontroller restarts after

3 machine cycles in all cases.

Power-Down Mode
The instruction that sets PCON.1 is the last exe-
cuted prior to going into the Power-down Mode.
Once in Power-down Mode, the oscillator is
stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.
The Power-down Mode can be terminated by an
external RESET.

Table 25. Power-Saving Mode Power Consumption

Table 26. Pin Status During Idle and Power-down Mode

Mode

Addr/Data

Ports1,3,4

PWM

Idle

Maintain Data

Active

Power-down

Maintain Data

Disable

SFR

Addr

Reg

Name

Bit Register Name

Reset

Value

Comments

PCON

SMOD

SMOD1

LVREN ADSFINT RCLK1

TCLK1

IDLE

Power Ctrl

UPSD3212C, UPSD3212CV

44/152

Table 27. Description of the PCON Bits

Note: 1. See the T2CON register for details of the flag description

I/O PORTS (MCU MODULE)
The MCU Module has five ports: Port0, Port1,
Port2, Port3 and Port 4. (Refer to the PSD Module
section on I/O ports A,B,C and D). Ports P0 and
P2 are dedicated for the external address and data
bus and is not available in the 52-pin package de-
vices.
Port1 - Port3 are the same as in the standard 8032
micro-controllers, with the exception of the addi-

tional special peripheral functions (see Table 28).
All ports are bi-directional. Pins of which the alter-
native function is not used may be used as normal
bi-directional I/O.
The use of Port1- Port4 pins as alternative func-
tions are carried out automatically by the
uPSD321X Devices provided the associated SFR
Bit is set HIGH.

Table 28. I/O Port Functions

Bit

Symbol

Function

SMOD

Double Baud Data Rate Bit UART

SMOD1

Double Baud Data Rate Bit 2nd UART

LVREN

LVR Disable Bit (active High)

ADSFINT

Enable ADC Interrupt

RCLK1

(1)

Received Clock Flag (UART 2)

TCLK1

(1)

Transmit Clock Flag (UART 2)

Activate Power-down Mode (High enable)

IDL

Activate Idle Mode (High enable)

Port Name

Main Function

Alternate

Port 1

GPIO

Timer 2 - Bits 0,1

2nd UART - Bits 2,3

ADC - Bits 4..7

Port 3

GPIO

UART - Bits 0,1

Interrupt - Bits 2,3

Timers - Bits 4,5

C - Bits 6,7

Port 4

GPIO

PWM - Bits 3..7

45/152

UPSD3212C, UPSD3212CV

The following SFR registers (Tables 29, 30, and
31) are used to control the mapping of alternate
functions onto the I/O port bits. Port 1 alternate
functions are controlled using the P1SFS register,
except for Timer 2 and the 2nd UART which are
enabled by their configuration registers. P1.0 to
P1.3 are default to GPIO after reset.
Port 3 pins 6 and 7 have been modified from the
standard 8032. These pins that were used for
READ and WRITE control signals are now GPIO

or I

C bus pins. The READ and WRITE pins are

assigned to dedicated pins.

Port 3 (I

C) and Port 4 alternate functions are con-

trolled using the P3SFS and P4SFS Special Func-
tion Selection registers. After a reset, the I/O pins
default to GPIO. The alternate function is enabled
if the corresponding bit in the PXSFS register is
set to '1.' Other Port 3 alternative functions (UART,
Interrupt, and Timer/Counter) are enabled by their
configuration register and do not require setting of
the bits in R3SFS.

Table 29. P1SFS (91H)

Table 30. P3SFS (93H)

Table 31. P4SFS (94H)

0=Port 1.7

1=ACH3

0=Port 1.6

1=ACH2

0=Port 1.5

1=ACH1

0=Port 1.4

1=ACH0

Bits Reserved

0 = Port 3.7

1 = SCL

from I

C unit

0 = Port 3.6

1 = SDA

from I

C unit

Bits are reserved.

0=Port 4.7

1=PWM 4

0=Port 4.6

1=PWM 3

0=Port 4.5

1=PWM 2

0=Port 4.4

1=PWM 1

0=Port 4.3

1=PWM 0

0=Port 4.2

0=Port 4.1

0=Port 4.0

47/152

UPSD3212C, UPSD3212CV

Figure 18. PORT Type and Description (Part 2)

OSCILLATOR

The oscillator circuit of the uPSD321X Devices is
a single stage inverting amplifier in a Pierce oscil-
lator configuration (see Figure 19). The circuitry
between XTAL1 and XTAL2 is basically an invert-
er biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback el-

ement to complete the oscillator circuit. Both are
operated in parallel resonance.
XTAL1 is the high gain amplifier input, and XTAL2
is the output. To drive the uPSD321X Devices ex-
ternally, XTAL1 is driven from an external source
and XTAL2 left open-circuit.

Figure 19. Oscillator

AI07428

Symbol

Circuit

Function

In/

Out

PORT1 <3:0>,

PORT3,

PORT4<7:3,1:0>

PORT2

I/O

PORT4.2

Bidirectional I/O port with
internal pull-ups
Schmitt input
CMOS compatible interface

Bidirectional I/O port with internal

pull-ups

Schmitt input.
TTL compatible interface

PORT1 < 7:4 >

I/O

Bidirectional I/O port with
internal pull-ups
Schmitt input

CMOS compatible interface
Analog input option

I/O

an_enb

AI06620

XTAL1

XTAL2

8 to 40 MHz

XTAL1

XTAL2

External Clock

UPSD3212C, UPSD3212CV

48/152

SUPERVISORY
There are four ways to invoke a reset and initialize
the uPSD321X Devices.

Via the external RESET pin

Via the internal LVR Block.

Via Watch Dog timer

The RESET mechanism is illustrated in Figure 20.
Each RESET source will cause an internal reset
signal active. The CPU responds by executing an
internal reset and puts the internal registers in a
defined state. This internal reset is also routed as
an active low reset input to the PSD Module.
External Reset
The RESET pin is connected to a Schmitt trigger
for noise reduction. A RESET is accomplished by
holding the RESET pin LOW for at least 1ms at
power up while the oscillator is running. Refer to
AC spec on other RESET timing requirements.

Low V

Voltage Reset

An internal reset is generated by the LVR circuit
when the V

drops below the reset threshold. Af-

ter V

reaching back up to the reset threshold,

the RESET signal will remain asserted for 10ms
before it is released. On initial power-up the LVR
is enabled (default). After power-up the LVR can
be disabled via the LVREN Bit in the PCON Reg-
ister.
Note: The LVR logic is still functional in both the
Idle and Power-down Modes.
The reset threshold:

5V operation: 4V +/- 0.25V

3.3V operation: 2.5V +/-0.2V

This logic supports approximately 0.1V of hystere-
sis and 1µs noise-cancelling delay.
Watchdog Timer Overflow
The Watchdog Timer generates an internal reset
when its 22-bit counter overflows. See Watchdog
Timer section for details.

Figure 20. RESET Configuration

AI07429

Reset

CPU

PERI.

Noise

Cancel

LVR

CPU

Clock

Sync

10ms

Timer

WDT

PSD_RST

Active Low

10ms at 40Mhz
50ms at 8Mhz

49/152

UPSD3212C, UPSD3212CV

WATCHDOG TIMER
The hardware Watchdog Timer (WDT) resets the
uPSD321X Devices when it overflows. The WDT
is intended as a recovery method in situations
where the CPU may be subjected to a software
upset. To prevent a system reset the timer must be
reloaded in time by the application software. If the
processor suffers a hardware/software malfunc-
tion, the software will fail to reload the timer. This
failure will result in a reset upon overflow thus pre-
venting the processor running out of control.
In the Idle Mode the watchdog timer and reset cir-
cuitry remain active. The WDT consists of a 22-bit
counter, the Watchdog Timer RESET (WDRST)
SFR and Watchdog Key Register (WDKEY).
Since the WDT is automatically enabled while the
processor is running. the user only needs to be
concerned with servicing it.
The 22-bit counter overflows when it reaches
4194304 (3FFFFFH). The WDT increments once
every machine cycle.

This means the user must reset the WDT at least
every 4194304 machine cycles (1.258 seconds at
40MHz). To reset the WDT the user must write a
value between 00-7EH to the WDRST register.
The value that is written to the WDRST is loaded
to the 7MSB of the 22-bit counter. This allows the
user to pre-loaded the counter to an initial value to
generate a flexible Watchdog time out period.
Writing a "00" to WDRST clears the counter.

The watchdog timer is controlled by the watchdog
key register, WDKEY. Only pattern 01010101
(=55H), disables the watchdog timer. The rest of
pattern combinations will keep the watchdog timer
enabled. This security key will prevent the watch-
dog timer from being terminated abnormally when
the function of the watchdog timer is needed.
In Idle Mode, the oscillator continues to run. To
prevent the WDT from resetting the processor
while in Idle, the user should always set up a timer
that will periodically exit Idle, service the WDT, and
re-enter Idle Mode.

Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)

Table 33. Description of the WDKEY Bits

WDKEY7

WDKEY6

WDKEY5

WDKEY4

WDKEY3

WDKEY2

WDKEY1

WDKEY0

Bit

Symbol

Function

7 to 0

WDKEY7 to

WDKEY0

Enable or disable Watchdog Timer.
01010101 (=55h): disable watchdog timer. Others: enable watchdog timer

51/152

UPSD3212C, UPSD3212CV

TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)
The uPSD321X Devices has three 16-bit Timer/
Counter registers: Timer 0, Timer 1 and Timer 2.
All of them can be configured to operate either as
timers or event counters and are compatible with
standard 8032 architecture.
In the "Timer" function, the register is incremented
every machine cycle. Thus, one can think of it as
counting machine cycles. Since a machine cycle
consists of 6 CPU clock periods, the count rate is
1/6 of the CPU clock frequency or 1/12 of Oscilla-
tor Frequency (f

OSC

In the "Counter" function, the register is increment-
ed in response to a 1-to-0 transition at its corre-
sponding external input pin, T0 or T1. In this
function, the external input is sampled during
S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cy-
cle, the count is incremented. The new count value
appears in the register during S3P1 of the cycle

following the one in which the transition was de-
tected. Since it takes 2 machine cycles (24 f

OSC

clock periods) to recognize a 1-to-0 transition, the
maximum count rate is 1/24 of the f

OSC

. There are

no restrictions on the duty cycle of the external in-
put signal, but to ensure that a given level is sam-
pled at least once before it changes, it should be
held for at least one full cycle. In addition to the
"Timer" or "Counter" selection, Timer 0 and Timer
1 have four operating modes from which to select.
Timer 0 and Timer 1
The "Timer" or "Counter" function is selected by
control bits C/T in the Special Function Register
TMOD. These Timer/Counters have four operat-
ing modes, which are selected by bit-pairs (M1,
M0) in TMOD. Modes 0, 1, and 2 are the same for
Timers/ Counters. Mode 3 is different. The four op-
erating modes are de-scribed in the following text.

Table 36. Control Register (TCON)

Table 37. Description of the TCON Bits

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit Symbol

Function

TF1

Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine

TR1

Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off

TF0

Timer 0 Overflow Flag. Set by hardier on Timer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine

TR0

Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off

IE1

Interrupt 1 Edge Flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed

IT1

Interrupt 1 Type Control Bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt

IE0

Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed

IT0

Interrupt 0 Type Control Bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt

UPSD3212C, UPSD3212CV

52/152

Table 38. TMOD Register (TMOD)

Table 39. Description of the TMOD Bits

Gate

C/T

Gate

C/T

Bit Symbol

Timer

Function

Gate

Timer 1

Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and
TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set

C/T

Timer or Counter selector, cleared for timer operation (input from internal system clock);
set for counter operation (input from T1 input pin)

(M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler
(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be
reloaded into TL1 each time it overflows
(M1,M0)=(1,1): Timer/Counter 1 stopped

Gate

Timer 0

Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and
TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 control bit is set

C/T

Timer or Counter selector, cleared for timer operation (input from internal system clock);
set for counter operation (input from T0 input pin)

(M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler
(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be
reloaded into TL0 each time it overflows
(M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control
bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits

53/152

UPSD3212C, UPSD3212CV

Mode 0. Putting either Timer into Mode 0 makes
it look like an 8048 Timer, which is an 8-bit Counter
with a divide-by-32 prescaler. Figure 22 shows the
Mode 0 operation as it applies to Timer 1.
In this mode, the Timer register is configured as a
13-bit register. As the count rolls over from all '1s'
to all '0s,' it sets the Timer Interrupt Flag TF1. The
counted input is enabled to the Timer when TR1 =
1 and either GATE = 0 or /INT1 = 1. (Setting GATE
= 1 allows the Timer to be controlled by external in-
put /INT1, to facilitate pulse width measurements).
TR1 is a control bit in the Special Function Regis-

ter TCON (TCON Control Register). GATE is in
TMOD.

The 13-bit register consists of all 8 bits of TH1 and
the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and should be ignored. Setting the
run flag does not clear the registers.
Mode 0 operation is the same for the Timer 0 as
for Timer 1. Substitute TR0, TF0, and /INT0 for the
corresponding Timer 1 signals in Figure 22. There
are two different GATE Bits, one for Timer 1 and
one for Timer 0.
Mode 1. Mode 1 is the same as Mode 0, except
that the Timer register is being run with all 16 bits.

Figure 22. Timer/Counter Mode 0: 13-bit Counter

AI06622

OSC

TF1

Interrupt

Gate

TR1

INT1 pin

T1 pin

Control

TL1

(5 bits)

TH1

(8 bits)

C/T = 0

C/T = 1

÷ 12

UPSD3212C, UPSD3212CV

54/152

Mode 2. Mode 2 configures the Timer register as
an 8-bit Counter (TL1) with automatic reload, as
shown in Figure 23. Overflow from TL1 not only
sets TF1, but also reloads TL1 with the contents of
TH1, which is preset by software. The reload
leaves TH1 unchanged. Mode 2 operation is the
same for Timer/Counter 0.
Timer 2
Like Timer 0 and 1, Timer 2 can operate as either
an event timer or as an event counter. This is se-
lected by Bit C/T2 in the special function register
T2CON (see Table 40). It has three operating
modes: Capture, Auto-reload, and Baud Rate
Generator (see Table 41, page 55), which are se-
lected by bits in the T2CON as shown in Table 42,
page 55. In the Capture Mode there are two op-
tions which are selected by Bit EXEN2 in T2CON.
if EXEN2 = 0, then Timer 2 is a 16-bit timer or
counter which upon overflowing sets Bit TF2, the
Timer 2 overflow bit, which can be used to gener-
ate an interrupt. If EXEN2 = 1, then Timer 2 still
does the above, but with the added feature that a

1-to-0 transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and
RCAP2H, respectively. In addition, the transition
at T2EX causes Bit EXF2 in T2CON to be set, and
EXF2 like TF2 can generate an interrupt. The Cap-
ture Mode is illustrated in Figure 24, page 56.
In the Auto-reload Mode, there are again two op-
tions, which are selected by bit EXEN2 in T2CON.
If EXEN2 = 0, then when Timer 2 rolls over it not
only sets TF2 but also causes the Timer 2 regis-
ters to be reloaded with the 16-bit value in regis-
ters RCAP2L and RCAP2H, which are preset by
software. If EXEN2 = 1, then Timer 2 still does the
above, but with the added feature that a 1-to-0
transition at external input T2EX will also trigger
the 16-bit reload and set EXF2. The Auto-reload
Mode is illustrated in Standard Serial Interface
(UART) Figure 25, page 56. The Baud Rate Gen-
eration Mode is selected by (RCLK, RCLK1) = 1
and/or (TCLK, TCLK1) = 1. It will be described in
conjunction with the serial port.

Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload

Table 40. Timer/Counter 2 Control Register (T2CON)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

AI06623

OSC

TF1

Interrupt

Gate

TR1

INT1 pin

T1 pin

Control

TL1

(8 bits)

TH1

(8 bits)

C/T = 0

C/T = 1

÷ 12

55/152

UPSD3212C, UPSD3212CV

Table 41. Timer/Counter 2 Operating Modes

Note:

= falling edge

Table 42. Description of the T2CON Bits

Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.

Mode

T2CON

T2MOD

DECN

T2CON

EXEN

P1.1

T2EX

Remarks

Input Clock

RxCLK

TxCLK

CP/

RL2

TR2

Internal

External

(P1.0/T2)

16-bit

Auto-

reload

reload upon overflow

OSC

/12

MAX

OSC

/24

reload trigger (falling
edge)

Down counting

Up counting

16-bit

Capture

16-bit Timer/Counter
(only up counting)

OSC

/12

MAX

OSC

/24

Capture (TH1,TL2)

(RCAP2H,RCAP2L)

Baud Rate

Generator

No Overflow Interrupt
Request (TF2)

OSC

/12

MAX

OSC

/24

Extra External Interrupt
(Timer 2)

Off

Timer 2 stops

Bit Symbol

Function

TF2

Timer 2 Overflow Flag. Set by a Timer 2 overflow, and must be cleared by software. TF2
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1

EXF2

Timer 2 External Flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by
software

RCLK

(1)

Receive Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the receive clock

TCLK

(1)

Transmit Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the transmit clock

EXEN2

Timer 2 External Enable Flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX

TR2

Start/stop control for Timer 2. A logic 1 starts the timer

C/T2

Timer or Counter Select for Timer 2. Cleared for timer operation (input from internal
system clock, t

CPU

); set for external event counter operation (negative edge triggered)

CP/RL2

Capture/Reload Flag. When set, capture will occur on negative transition of T2EX if
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow

57/152

UPSD3212C, UPSD3212CV

Mode 3. Timer 1 in Mode 3 simply holds its count.
The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. The logic for Mode 3 on Timer
0 is shown in Figure 26. TL0 uses the Timer 0 con-
trol Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is
locked into a timer function (counting machine cy-
cles) and takes over the use of TR1 and TF1 from
Timer 1. Thus, TH0 now controls the "Timer 1" In-
terrupt.

Mode 3 is provided for applications requiring an
extra 8-bit timer on the counter. With Timer 0 in
Mode 3, an uPSD321X Devices can look like it has
three Timer/Counters. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out
of and into its own Mode 3, or can still be used by
the serial port as a baud rate generator, or in fact,
in any application not requiring an interrupt.

Figure 26. Timer/Counter Mode 3: Two 8-bit Counters

AI06624

OSC

TF0

Interrupt

Gate

TR0

INT0 pin

T0 pin

Control

TL0

(8 bits)

C/T = 0

C/T = 1

÷ 12

OSC

TF1

Interrupt

Control

TH1

(8 bits)

÷ 12

TR1

UPSD3212C, UPSD3212CV

58/152

STANDARD SERIAL INTERFACE (UART)
The uPSD321X Devices provides two standard
8032 UART serial ports. The first port is connected
to pin P3.0 (RX) and P3.1 (TX). The second port is
connected to pin P1.2 (RX) and P1.3(TX). The op-
eration of the two serial ports are the same and are
controlled by the SCON and SCON2 registers.
The serial port is full duplex, meaning it can trans-
mit and receive simultaneously. It is also receive-
buffered, meaning it can commence reception of a
second byte before a previously received byte has
been read from the register. (However, if the first
byte still has not been read by the time reception
of the second byte is complete, one of the bytes
will be lost.) The serial port receive and transmit
registers are both accessed at Special Function
Register SBUF (or SBUF2 for the second serial
port). Writing to SBUF loads the transmit register,
and reading SBUF accesses a physically separate
receive register.
The serial port can operate in 4 modes:
Mode 0. Serial data enters and exits through
RxD. TxD outputs the shift clock. 8 bits are trans-
mitted/received (LSB first). The baud rate is fixed
at 1/12 the f

OSC

Mode 1. 10 bits are transmitted (through TxD) or
received (through RxD): a start Bit (0), 8 data bits
(LSB first), and a Stop Bit (1). On receive, the Stop
Bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Mode 2. 11 bits are transmitted (through TxD) or
received (through RxD): start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). On Transmit, the 9th data bit (TB8 in
SCON) can be assigned the value of '0' or '1.' Or,
for example, the Parity Bit (P, in the PSW) could
be moved into TB8. On receive, the 9th data bit
goes into RB8 in Special Function Register SCON,
while the Stop Bit is ignored. The baud rate is pro-
grammable to either 1/32 or 1/64 the oscillator fre-
quency.

Mode 3. 11 bits are transmitted (through TxD) or
received (through RxD): a Start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). In fact, Mode 3 is the same as Mode
2 in all respects except baud rate. The baud rate
in Mode 3 is variable.
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination regis-
ter. Reception is initiated in Mode 0 by the condi-
tion RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming start bit if REN =
1.
Multiprocessor Communications
Modes 2 and 3 have a special provision for multi-
processor communications. In these modes, 9
data bits are received. The 9th one goes into RB8.
Then comes a Stop Bit. The port can be pro-
grammed such that when the Stop Bit is received,
the serial port interrupt will be activated only if RB8
= 1. This feature is enabled by setting Bit SM2 in
SCON. A way to use this feature in multi-proces-
sor systems is as follows:

When the master processor wants to transmit a
block of data to one of several slaves, it first sends
out an address byte which identifies the target
slave. An address byte differs from a data byte in
that the 9th bit is '1' in an address byte and 0 in a
data byte. With SM2 = 1, no slave will be interrupt-
ed by a data byte. An ad-dress byte, however, will
interrupt all slaves, so that each slave can exam-
ine the received byte and see if it is being ad-
dressed. The addressed slave will clear its SM2
Bit and prepare to receive the data bytes that will
be coming. The slaves that weren't being ad-
dressed leave their SM2s set and go on about
their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can
be used to check the validity of the Stop Bit. In a
Mode 1 reception, if SM2 = 1, the Receive Inter-
rupt will not be activated unless a valid Stop Bit is
received.

UPSD3212C, UPSD3212CV

60/152

Table 44. Description of the SCON Bits

Bit Symbol

Function

SM0

(SM1,SM0)=(0,0): Shift Register. Baud rate = f

OSC

/12

(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable
(SM1,SM0)=(0,1): 8-bit UART. Baud rate = f

OSC

/64 or f

OSC

/32

(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable

SM1

SM2

Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if
SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode
1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2
should be '0'

REN

Enables serial reception. Set by software to enable reception. Clear by software to
disable reception

TB8

The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired

RB8

In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used

Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the Stop Bit in the other modes, in any serial transmission. Must be
cleared by software

Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the Stop Bit in the other modes, in any serial reception (except for
SM2). Must be cleared by software

61/152

UPSD3212C, UPSD3212CV

Baud Rates. The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = f

OSC

/ 12

The baud rate in Mode 2 depends on the value of
Bit SMOD = 0 (which is the value on reset), the
baud rate is 1/64 the oscillator frequency. If SMOD
= 1, the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = (2

SMOD

/ 64) x f

OSC

In the uPSD321X Devices, the baud rates in
Modes 1 and 3 are determined by the Timer 1
overflow rate.
Using Timer 1 to Generate Baud Rates. When
Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by
the Timer 1 overflow rate and the value of SMOD
as follows (see Table 45, page 62):
Mode 1,3 Baud Rate =
(2

SMOD

/ 32) x (Timer 1 overflow rate)

The Timer 1 Interrupt should be disabled in this
application. The Timer itself can be configured for
either "timer" or "counter" operation, and in any of
its 3 running modes. In the most typical applica-
tions, it is configured for "timer" operation, in the
Auto-reload Mode (high nibble of TMOD = 0010B).
In that case the baud rate is given by the formula:
Mode 1,3 Baud Rate =
(2

SMOD

/ 32) x (f

OSC

/ (12 x [256 (TH1)]))

One can achieve very low baud rates with Timer 1
by leaving the Timer 1 Interrupt enabled, and con-
figuring the Timer to run as a 16-bit timer (high nib-
ble of TMOD = 0001B), and using the Timer 1
Interrupt to do a 16-bit software reload. Figure 22
lists various commonly used baud rates and how
they can be obtained from Timer 1.
Using Timer/Counter 2 to Generate Baud
Rates. In the uPSD321X Devices, Timer 2 select-
ed as the baud rate generator by setting TCLK
and/or RCLK (see Figure 22, page 53 Timer/
Counter 2 Control Register (T2CON)).
Note: The baud rate for transmit and receive can
be simultaneously different. Setting RCLK and/or
TCLK puts Timer into its Baud Rate Generator
Mode.
The RCLK and TCLK Bits in the T2CON register
configure UART 1. The RCLK1 and TCLK1 Bits in
the PCON register configure UART 2.

The Baud Rate Generator Mode is similar to the
Auto-reload Mode, in that a roll over in TH2 causes
the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which
are preset by software.
Now, the baud rates in Modes 1 and 3 are deter-
mined at Timer 2's overflow rate as follows:
Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16
The timer can be configured for either "timer" or
"counter" operation. In the most typical applica-
tions, it is configured for "timer" operation (C/T2 =
0). "Timer" operation is a little different for Timer 2
when it's being used as a baud rate generator.
Normally, as a timer it would increment every ma-
chine cycle (thus at the 1/6 the CPU clock frequen-
cy). In the case, the baud rate is given by the
formula:
Mode 1,3 Baud Rate = f

OSC

/ (32 x [65536 -

(RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of
RC2H and RC2L taken as a 16-bit unsigned inte-
ger.
Timer 2 also be used as the Baud Rate Generating
Mode. This mode is valid only if RCLK + TCLK = 1
in T2CON or in PCON.
Note: A roll-over in TH2 does not set TF2, and will
not generate an interrupt. Therefore, the Timer in-
terrupt does not have to be disabled when Timer 2
is in the Baud Rate Generator Mode.
Note: If EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when
Timer 2 is in use as a baud rate generator, T2EX
can be used as an extra external interrupt, if de-
sired.
It should be noted that when Timer 2 is running
(TR2 = 1) in "timer" function in the Baud Rate Gen-
erator Mode, one should not try to READ or
WRITE TH2 or TL2. Under these conditions the
timer is being incremented every state time, and
the results of a READ or WRITE may not be accu-
rate. The RC registers may be read, but should not
be written to, because a WRITE might overlap a
reload and cause WRITE and/or reload errors.
Turn the timer off (clear TR2) before accessing the
Timer 2 or RC registers, in this case.

UPSD3212C, UPSD3212CV

62/152

Table 45. Timer 1-Generated Commonly Used Baud Rates

More About Mode 0. Serial data enters and exits
through RxD. TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed at 1/12 the f

OSC

Figure 27, page 59 shows a simplified functional
diagram of the serial port in Mode 0, and associat-
ed timing.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The "WRITE
to SBUF" signal at S6P2 also loads a '1' into the
9th position of the transmit shift register and tells
the TX Control block to commence a transmission.
The internal timing is such that one full machine
cycle will elapse between "WRITE to SBUF" and
activation of SEND.
SEND enables the output of the shift register to the
alternate out-put function line of RxD and also en-
able SHIFT CLOCK to the alternate output func-
tion line of TxD. SHIFT CLOCK is low during S3,
S4, and S5 of every machine cycle, and high dur-
ing S6, S1, and S2. At S6P2 of every machine cy-
cle in which SEND is active, the contents of the
transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in
from the left. When the MSB of the data byte is at
the output position of the shift register, then the '1'
that was initially loaded into the 9th position, is just

to the left of the MSB, and all positions to the left
of that contain zeros. This condition flags the TX
Control block to do one last shift and then deacti-
vate SEND and set T1. Both of these actions occur
at S1P1. Both of these actions occur at S1P1 of
the 10th machine cycle after "WRITE to SBUF."
Reception is initiated by the condition REN = 1 and
R1 = 0. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
shift register, and in the next clock phase activates
RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate
output function line of TxD. SHIFT CLOCK makes
transitions at S3P1 and S6P1 of every machine
cycle in which RECEIVE is active, the contents of
the receive shift register are shifted to the left one
position. The value that comes in from the right is
the value that was sampled at the RxD pin at S5P2
of the same machine cycle.
As data bits come in from the right, '1s' shift out to
the left. When the '0' that was initially loaded into
the right-most position arrives at the left-most po-
sition in the shift register, it flags the RX Control
block to do one last shift and load SBUF. At S1P1
of the 10th machine cycle after the WRITE to
SCON that cleared RI, RECEIVE is cleared as RI
is set.

Baud Rate

OSC

SMOD

Timer 1

C/T

Mode

Reload Value

Mode 0 Max: 1MHz

12MHz

Mode 2 Max: 375K

12MHz

Modes 1, 3: 62.5K

12MHz

FFh

19.2K

11.059MHz

FDh

9.6K

11.059MHz

FDh

4.8K

11.059MHz

FAh

2.4K

11.059MHz

F4h

1.2K

11.059MHz

E8h

137.5

11.059MHz

1Dh

110

6MHz

72h

110

12MHz

FEEBh

63/152

UPSD3212C, UPSD3212CV

Figure 28. Serial Port Mode 0, Waveforms

More About Mode 1. Ten bits are transmitted
(through TxD), or received (through RxD): a start
Bit (0), 8 data bits (LSB first). and a Stop Bit (1). On
receive, the Stop Bit goes into RB8 in SCON. In
the uPSD321X Devices the baud rate is deter-
mined by the Timer 1 or Timer 2 overflow rate.
Figure 29, page 64 shows a simplified functional
diagram of the serial port in Mode 1, and associat-
ed timings for transmit receive.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The "WRITE
to SBUF" signal also loads a '1' into the 9th bit po-
sition of the transmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission actually commences at S1P1 of the
machine cycle following the next rollover in the di-
vide-by-16 counter. (Thus, the bit times are syn-
chronized to the divide-by-16 counter, not to the
"WRITE to SBUF" signal.)
The transmission begins with activation of SEND
which puts the start bit at TxD. One bit time later,
DATA is activated, which enables the output bit of
the transmit shift register to TxD. The first shift
pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked
in from the left (see Figure 30, page 64). When the
MSB of the data byte is at the output position of the
shift register, then the '1' that was initially loaded
into the 9th position is just to the left of the MSB,
and all positions to the left of that contain zeros.
This condition flags the TX Control unit to do one
last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after
"WRITE to SBUF."
Reception is initiated by a detected 1-to-0 transi-
tion at RxD. For this purpose RxD is sampled at a

rate of 16 times whatever baud rate has been es-
tablished. When a transition is detected, the di-
vide-by-16 counter is immediately reset, and 1FFH
is written into the input shift register. Resetting the
divide-by-16 counter aligns its roll-overs with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time
into 16ths. At the 7th, 8th, and 9th counter states
of each bit time, the bit detector samples the value
of RxD. The value accepted is the value that was
seen in at least 2 of the 3 samples. This is done for
noise rejection. If the value accepted during the
first bit time is not '0,' the receive circuits are reset
and the unit goes back to looking for an-other 1-to-
0 transition. This is to provide rejection of false
start bits. If the start bit proves valid, it is shifted
into the input shift register, and reception of the re-
set of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to
the left. When the start bit arrives at the left-most
position in the shift register (which in Mode 1 is a
9-bit register), it flags the RX Control block to do
one last shift, load SBUF and RB8, and set RI. The
signal to load SBUF and RB8, and to set RI, will be
generated if, and only if, the following conditions
are met at the time the final shift pulse is generat-
ed:
1. R1 = 0, and
2. Either SM2 = 0, or the received Stop Bit = 1.
If either of these two conditions is not met, the re-
ceived frame is irretrievably lost. If both conditions
are met, the Stop Bit goes into RB8, the 8 data bits
go into SBUF, and RI is activated. At this time,
whether the above conditions are met or not, the
unit goes back to looking for a 1-to-0 transition in
RxD.

AI06825

Write to SBUF

Send

Shift

RxD (Data Out)

TxD (Shift Clock)

Write to SCON

Receive

Shift

RxD (Data In)

TxD (Shift Clock)

S6P2

S3P1

S6P1

Clear RI

Receive

Transmit

65/152

UPSD3212C, UPSD3212CV

More About Modes 2 and 3. Eleven bits are
transmitted (through TxD), or received (through
RxD): a Start Bit (0), 8 data bits (LSB first), a pro-
grammable 9th data bit, and a Stop Bit (1). On
transmit, the 9th data bit (TB8) can be assigned
the value of '0' or '1.' On receive, the data bit goes
into RB8 in SCON. The baud rate is programma-
ble to either 1/16 or 1/32 the CPU clock frequency
in Mode 2. Mode 3 may have a variable baud rate
generated from Timer 1.
Figure 31, page 66 and Figure 33, page 67 show
a functional diagram of the serial port in Modes 2
and 3. The receive portion is exactly the same as
in Mode 1. The transmit portion differs from Mode
1 only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The "WRITE
to SBUF" signal also loads TB8 into the 9th bit po-
sition of the transmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission commences at S1P1 of the machine
cycle following the next roll-over in the divide-by-
16 counter. (Thus, the bit times are synchronized
to the divide-by-16 counter, not to the "WRITE to
SBUF" signal.)
The transmission begins with activation of SEND,
which puts the start bit at TxD. One bit time later,
DATA is activated, which enables the output bit of
the transmit shift register to TxD. The first shift
pulse occurs one bit time after that (see Figure 32,
page 66 and Figure 34, page 67). The first shift
clocks a '1' (the Stop Bit) into the 9th bit position of
the shift register. There-after, only zeros are
clocked in. Thus, as data bits shift out to the right,
zeros are clocked in from the left. When TB8 is at
the out-put position of the shift register, then the
Stop Bit is just to the left of TB8, and all positions
to the left of that contain zeros. This condition flags
the TX Control unit to do one last shift and then de-

activate SEND and set TI. This occurs at the 11th
divide-by 16 rollover after "WRITE to SUBF."

Reception is initiated by a detected 1-to-0 transi-
tion at RxD. For this purpose RxD is sampled at a
rate of 16 times whatever baud rate has been es-
tablished. When a transition is detected, the di-
vide-by-16 counter is immediately reset, and 1FFH
is written to the input shift register.
At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of R-D.
The value accepted is the value that was seen in
at least 2 of the 3 samples. If the value accepted
during the first bit time is not '0,' the receive circuits
are reset and the unit goes back to looking for an-
other 1-to-0 transition. If the Start Bit proves valid,
it is shifted into the input shift register, and recep-
tion of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to
the left. When the Start Bit arrives at the left-most
position in the shift register (which in Modes 2 and
3 is a 9-bit register), it flags the RX Control block
to do one last shift, load SBUF and RB8, and set
RI.
The signal to load SBUF and RB8, and to set RI,
will be generated if, and only if, the following con-
ditions are met at the time the final shift pulse is
generated:
1. RI = 0, and
2. Either SM2 = 0, or the received 9th data bit = 1
If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes
into RB8, and the first 8 data bits go into SBUF.
One bit time later, whether the above conditions
were met or not, the unit goes back to looking for
a 1-to-0 transition at the RxD input.

UPSD3212C, UPSD3212CV

68/152

ANALOG-TO-DIGITAL CONVERTOR (ADC)
The analog to digital (A/D) converter allows con-
version of an analog input to a corresponding 8-bit
digital value. The A/D module has four analog in-
puts, which are multiplexed into one sample and
hold. The output of the sample and hold is the in-
put into the converter, which generates the result
via successive approximation. The analog supply
voltage is connected to AVREF of ladder resis-
tance of A/D module.

The A/D module has two registers which are the
control register ACON and A/D result register
ADAT. The register ACON, shown in Table 46 and
Table 47, page 69, controls the operation of the A/
D converter module. To use analog inputs, I/O is
selected by P1SFS register. Also an 8-bit prescal-
er ASCL divides the main system clock input down
to approximately 6MHz clock that is required for
the ADC logic. Appropriate values need to be load-
ed into the prescaler based upon the main MCU
clock frequency prior to use.
The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The register ADAT contains
the results of the A/D conversion. When conver-
sion is completed, the result is loaded into the
ADAT the A/D Conversion Status Bit ADSF is set
to '1.'
The block diagram of the A/D module is shown in
Figure 35. The A/D Status Bit ADSF is set auto-

matically when A/D conversion is completed,
cleared when A/D conversion is in process.
The ASCL should be loaded with a value that re-
sults in a clock rate of approximately 6MHz for the
ADC using the following formula (see Table 48,
page 69):

ADC clock input = (f

OSC

/ 2) / (Prescaler register

value +1)
Where f

OSC

is the MCU clock input frequency

The conversion time for the ADC can be calculat-
ed as follows:
ADC Conversion Time = 8 clock * 8bits * (ADC
Clock) ~= 10.67usec (at 6MHz)
ADC Interrupt
The ADSF Bit in the ACON register is set to '1'
when the A/D conversion is complete. The status
bit can be driven by the MCU, or it can be config-
ured to generate a falling edge interrupt when the
conversion is complete.
The ADSF Interrupt is enabled by setting the ADS-
FINT Bit in the PCON register. Once the bit is set,
the external INT1 Interrupt is disabled and the
ADSF Interrupt takes over as INT1. INT1 must be
configured as if it is an edge interrupt input. The
INP1 pin (p3.3) is available for general I/O func-
tions, or Timer1 gate control.

Figure 35. A/D Block Diagram

AI06627

Input

MUX

ACH0

ACH1

ACH2

ACH3

ACON

INTERNAL BUS

ADAT

AVREF

Ladder

Resistor

ecode

S/H

Successive

Approximation

Circuit

Conversion

Complete

Interrupt

69/152

UPSD3212C, UPSD3212CV

Table 46. ADC SFR Memory Map

Table 47. Description of the ACON Bits

Table 48. ADC Clock Input

SFR

Addr

Reg

Name

Bit Register Name

Reset

Value

Comments

ASCL

8-bit

Prescaler for

ADC clock

ADAT

ADAT7

ADAT6

ADAT5

ADAT4

ADAT3

ADAT2

ADAT1

ADAT0

ADC Data

ACON

ADEN

ADS1

ADS0

ADST

ADSF

ADC Control

Bit

Symbol

Function

7 to 6

Reserved

ADEN

ADC Enable Bit: 0 : ADC shut off and consumes no operating current

1 : enable ADC

Reserved

3 to 2

ADS1, ADS0

Analog channel select

0, 0

Channel0 (ACH0)

0, 1

Channel1 (ACH1)

1, 0

Channel2 (ACH2)

1, 1

Channel3 (ACH3)

ADST

ADC Start Bit:

0 : force to zero

1 : start an ADC; after one cycle, bit is cleared to '0'

ADSF

ADC Status Bit:

0 : A/D conversion is in process

1 : A/D conversion is completed, not in process

MCU Clock Frequency

Prescaler Register Value

ADC Clock

40MHz

6.7MHz

36MHz

6MHz

24MHz

6MHz

12MHz

6MHz

UPSD3212C, UPSD3212CV

70/152

PULSE WIDTH MODULATION (PWM)
The PWM block has the following features:

Four-channel, 8-bit PWM unit with 16-bit
prescaler

One-channel, 8-bit unit with programmable
frequency and pulse width

PWM Output with programmable polarity

4-channel PWM Unit (PWM 0-3)
The 8-bit counter of a PWM counts module 256
(i.e., from 0 to 255, inclusive). The value held in
the 8-bit counter is compared to the contents of the
Special Function Register (PWM 0-3) of the corre-
sponding PWM. The polarity of the PWM outputs
is programmable and selected by the PWML Bit in
PWMCON register. Provided the contents of a
PWM 0-3 register is greater than the counter val-
ue, the corresponding PWM output is set HIGH
(with PWML = 0). When the contents of this regis-
ter is less than or equal to the counter value, the
corresponding PWM output is set LOW (with
PWML = 0). The pulse-width-ratio is therefore de-

fined by the contents of the corresponding Special
Function Register (PWM 0-3) of a PWM. By load-
ing the corresponding Special Function Register
(PWM 0-3) with either 00H or FFH, the PWM out-
put can be retained at a constant HIGH or LOW
level respectively (with PWML = 0).
For each PWM unit, there is a 16-bit Prescaler that
are used to divide the main system clock to form
the input clock for the corresponding PWM unit.
This prescaler is used to define the desired repeti-
tion rate for the PWM unit. SFR registers B1h -
B2h are used to hold the 16-bit divisor values.
The repetition frequency of the PWM output is giv-
en by:

fPWM

= (f

OSC

/ prescaler0) / (2 x 256)

And the input clock frequency to the PWM
counters is = f

OSC

/ 2 / (prescaler data value + 1)

See the I/O PORTS (MCU Module), page 44 for
more information on how to configure the Port 4
pin as PWM output.

UPSD3212C, UPSD3212CV

74/152

PWM 4 Channel Operation
The 16-bit Prescaler1 divides the input clock
(f

OSC

/2) to the desired frequency, the resulting

clock runs the 8-bit Counter of the PWM 4 chan-
nel. The input clock frequency to the PWM 4
Counter is:

f PWM4 = (f

OSC

/2)/(Prescaler1 data value +1)

When the Prescaler1 Register (B4h, B3h) is set to
data value '0,' the maximum input clock frequency
to the PWM 4 Counter is f

OSC

/2 and can be as high

as 20MHz.
The PWM 4 Counter is a free-running, 8-bit
counter. The output of the counter is compared to
the Compare Registers, which are loaded with
data from the Pulse Width Register (PWM4W,
ABh) and the Period Register (PWM4P, AAh). The
Pulse Width Register defines the pulse duration or
the Pulse Width, while the Period Register defines
the period of the PWM. When the PWM 4 channel
is enabled, the register values are loaded into the
Comparator Registers and are compared to the

Counter output. When the content of the counter is
equal to or greater than the value in the Pulse
Width Register, it sets the PWM 4 output to low
(with PWMP Bit = 0). When the Period Register
equals to the PWM4 Counter, the Counter is
cleared, and the PWM 4 channel output is set to
logic 'high' level (beginning of the next PWM
pulse).
The Period Register cannot have a value of "00"
and its content should always be greater than the
Pulse Width Register.
The Prescaler1 Register, Pulse Width Register,
and Period Register can be modified while the
PWM 4 channel is active. The values of these reg-
isters are automatically loaded into the Prescaler
Counter and Comparator Registers when the cur-
rent PWM 4 period ends.
The PWMCON Register (Bits 5 and 6) controls the
enable/disable and polarity of the PWM 4 channel.

Figure 38. PWM 4 With Programmable Pulse Width and Frequency

AI07090

PWM4

Defined by Pulse

Width Register

Switch Level

RESET
Counter

Defined by Period Register

75/152

UPSD3212C, UPSD3212CV

C INTERFACE

The serial port supports the twin line I

C-bus, con-

sisting of a data line (SDA1), and a clock line
(SCL1) as shown in Figure 39. Depending on the
configuration, the SDA1 and SCL1 lines may re-
quire pull-up resistors.
These lines also function as I/O port lines if the I

bus is not enabled.
The system is unique because data transport,
clock generation, address recognition, and bus
control arbitration are all controlled by hardware.
The I

C serial I/O has complete autonomy in byte

handling and operates in 4 modes.

Master transmitter

Master receiver

Slave transmitter

Slave receiver

These functions are controlled by the SFRs (see
Tables 50, 51, and Table 52, page 76):
S2CON: the control of byte handling and the op-

eration of 4 mode.

S2STA: the contents of its register may also be

used as a vector to various service routines.

S2DAT: data shift register.
S2ADR: slave address register. Slave address

recognition is performed by On-Chip H/W.

Figure 39. Block Diagram of the I

C Bus Serial I/O

AI07430

SCL1

SDA1

Bus Clock Generator

Arbitration and Sync. Logic

Shift Register

Status Register

Slave Address

Control Register

Internal Bus

UPSD3212C, UPSD3212CV

76/152

Table 50. Serial Control Register (S2CON)

Table 51. Description of the S2CON Bits

Table 52. Selection of the Serial Clock Frequency SCL in Master Mode

CR2

ENII

STA

STO

ADDR

CR1

CR0

Bit Symbol

Function

CR2

This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is
in the Master Mode.

ENII

Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high
impedance state.

STA

START Flag. When this bit is set, the SIO H/W checks the status of the I

C-bus and

generates a START condition if the bus free. If the bus is busy, the SIO will generate a
repeated START condition when this bit is set.

STO

STOP Flag. With this bit set while in Master Mode a STOP condition is generated.

When a STOP condition is detected on the I

C bus, the I

C hardware clears the STO

Flag.
Note: This bit have to be set before 1 cycle interrupt period of STOP. That is, if this bit is
set, STOP condition in Master Mode is generated after 1 cycle interrupt period.

ADDR

This bit is set when address byte was received. Must be cleared by software.

Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
· Own slave address is received
· A data byte is received while the device is programmed to be a Master Receiver
· A data byte is received while the device is a selected Slave Receiver. When this bit is
reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.

CR1

These two bits along with the CR2 Bit determine the serial clock frequency when SIO is
in the Master Mode.

CR0

CR2 CR1

CR0

OSC

Divisor

Bit Rate (kHz) at f

OSC

12MHz

24MHz

36MHz

40MHz

375

750

250

500

750

833

200

400

600

666

100

200

300

333

120

100

150

166

240

480

12.5

37.5

960

6.25

12.5

18.75

77/152

UPSD3212C, UPSD3212CV

Serial Status Register (S2STA)
S2STA is a "Read-only" register. The contents of
this register may be used as a vector to a service
routine. This optimized the response time of the
software and consequently that of the I

C bus. The

status codes for all possible modes of the I

C bus

interface are given Table 54.
This flag is set, and an interrupt is generated, after
any of the following events occur:
1. Own slave address has been received during

AA = 1: ack_int

2. The general call address has been received

while GC(S2ADR.0) = 1 and AA = 1:

3. A data byte has been received or transmitted in

Master Mode (even if arbitration is lost): ack_int

4. A data byte has been received or transmitted as

selected slave: ack_int

5. A stop condition is received as selected slave

receiver or transmitter: stop_int

Data Shift Register (S2DAT)
S2DAT contains the serial data to be transmitted
or data which has just been received. The MSB
(Bit 7) is transmitted or received first; that is, data
shifted from right to left.

Table 53. Serial Status Register (S2STA)

Table 54. Description of the S2STA Bits

Note: 1. Interrupt Flag Bit (INTR, S2STA Bit 5) is cleared by Hardware as reading S2STA register.

2. I

C Interrupt Flag (INTR) can occur in below case.

Table 55. Data Shift Register (S2DAT)

STOP

INTR

TX_MODE

BBUSY

BLOST

/ACK_REP

SLV

Bit

Symbol

Function

General Call Flag

STOP

Stop Flag. This bit is set when a STOP condition is received

INTR

(1,2)

Interrupt Flag. This bit is set when an I²C Interrupt condition is requested

TX_MODE

Transmission Mode Flag.
This bit is set when the I²C is a transmitter; otherwise this bit is reset

BBUSY

Bus Busy Flag.
This bit is set when the bus is being used by another master; otherwise, this bit is reset

BLOST

Bus Lost Flag.
This bit is set when the master loses the bus contention; otherwise this bit is reset

/ACK_REP

Acknowledge Response Flag.
This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal

SLV

Slave Mode Flag.
This bit is set when the I²C plays role in the Slave Mode; otherwise this bit is reset

S2DAT7

S2DAT6

S2DAT5

S2DAT4

S2DAT3

S2DAT2

S2DAT1

S2DAT0

UPSD3212C, UPSD3212CV

78/152

Address Register (S2ADR)
This 8-bit register may be loaded with the 7-bit
slave address to which the controller will respond
when programmed as a slave receive/transmitter.
The Start/Stop Hold Time Detection and System
Clock registers (Tables 57 and 58) are included in

the I

C unit to specify the start/stop detection time

to work with the large range of MCU frequency val-
ues supported. For example, with a system clock
of 40MHz.

Table 56. Address Register (S2ADR)

Note: SLA6 to SLA0: Own slave address.

Table 57. Start /Stop Hold Time Detection Register (S2SETUP)

Table 58. System Cock of 40MHz

Table 59. System Clock Setup Examples

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

Address

Register Name

Reset Value

Note

SFR

D2h

S2SETUP

00h

To control the start/stop hold time detection for the multi-master
I²C module in Slave Mode

S1SETUP,

S2SETUP Register

Value

Number of Sample

Clock (f

OSC

/2 >

50ns)

Required Start/

Stop Hold Time

Note

00h

1EA

50ns

When Bit 7 (enable bit) = 0, the number of
sample clock is 1EA (ignore Bit 6 to Bit 0)

80h

1EA

50ns

81h

2EA

100ns

82h

3EA

150ns

...

8Bh

12EA

600ns

Fast Mode I²C Start/Stop hold time specification

...

FFh

128EA

6000ns

System Clock

S1SETUP,

S2SETUP Register

Value

Number of Sample

Clock

Required Start/Stop Hold Time

40MHz (f

OSC

/2 > 50ns)

8Bh

12 EA

600ns

30MHz (f

OSC

/2 > 66.6ns)

89h

9 EA

600ns

20MHz (f

OSC

/2 > 100ns)

86h

6 EA

600ns

8MHz (f

OSC

/2 > 250ns)

83h

3 EA

750ns

79/152

UPSD3212C, UPSD3212CV

PSD MODULE

The PSD Module provides configurable
Program and Data memories to the 8032 CPU
core (MCU). In addition, it has its own set of I/O
ports and a PLD with 16 macrocells for general
logic implementation.

Ports A,B,C, and D are general purpose
programmable I/O ports that have a port
architecture which is different from the I/O ports
in the MCU Module.

The PSD Module communicates with the MCU
Module through the internal address, data bus
(A0-A15, D0-D7) and control signals (RD, WR,
PSEN, ALE, RESET). The user defines the
Decoding PLD in the PSDsoft Development
Tool and can map the resources in the PSD
Module to any program or data address space.
Figure 40 shows the functional blocks in the
PSD Module.

Functional Overview

512Kbit Flash memory. This is the main Flash
memory. It is divided into 4 sectors (16KBytes
each) that can be accessed with user-specified
addresses.

Secondary 128Kbit Flash boot memory. It is
divided into 2 sectors (8KBytes each) that can
be accessed with user-specified addresses.
This secondary memory brings the ability to
execute code and update the main Flash

concurrently.

16Kbit SRAM. The SRAM's contents can be
protected from a power failure by connecting an
external battery.

CPLD with 16 Output Micro Cells (OMCs) and
up to 20 Input Micro Cells (IMCs). The CPLD
may be used to efficiently implement a variety of
logic functions for internal and external control.

Examples include state machines, loadable
shift registers, and loadable counters.

Decode PLD (DPLD) that decodes address for
selection of memory blocks in the PSD Module.

Configurable I/O ports (Port A,B,C and D) that
can be used for the following functions:
MCU I/Os

PLD I/Os

Latched MCU address output

Special function I/Os.

I/O ports may be configured as open drain

outputs.

Built-in JTAG compliant serial port allows full-
chip, In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.

Internal page register that can be used to
expand the 8032 MCU Module address space
by a factor of 256.

Internal programmable Power Management
Unit (PMU) that supports a low-power mode
called Power-down Mode. The PMU can
automatically detect a lack of the 8032 CPU
core activity and put the PSD Module into
Power-down Mode.

Erase/WRITE cycles:
Flash memory - 100,000 minimum

PLD - 1,000 minimum

Data Retention: 15 year minimum (for Main

Flash memory, Boot, PLD and Configuration
bits)

UPSD3212C, UPSD3212CV

80/152

Figure 40. PSD MODULE Block Diagram

BUS

Interface

WR_, RD_,

PSEN_, ALE,

RESET_,

A0-A15

D0 D7

CLKIN

(PD1)

CLKIN

PLD

INPUT

BUS

PROG.

PORT

PROG.

PORT

POWER

MANGMT

UNIT

512KBIT PRIMARY

FLASH MEMORY

8 SECTORS

VSTDBY

PA0 PA7

PB0 PB7

PROG.

PORT

PROG.

PORT

PC0 PC7

PD1 PD2

ADDRESS

/
DATA

/
CONTROL BUS

PORT A ,B & C

2 EXT CS TO PORT D

20 INPUT MACROCELLS

PORT A ,B & C

128KBIT SECONDARY

NON-VOLATILE MEMORY

(BOOT OR DATA)

2 SECTORS

16KBIT BATTERY

BACKUP SRAM

RUNTIME CONTROL

AND I/O REGISTERS

SRAM SELECT

PERIP I/O MODE SELECTS

MACROCELL FEEDBACK OR PORT INPUT

CSIOP

FLASH ISP CPLD

(CPLD)

16 OUTPUT MACROCELLS

FLASH DECODE

PLD

( DPLD

)

PLD, CONFIGURATION

& FLASH MEMORY

LOADER

JTAG

SERIAL

CHANNEL

( PC2

)

PAGE

REGISTER

EMBEDDED

ALGORITHM

SECTOR

SELECTS

SECTOR

SELECTS

GLOBAL

CONFIG. &

SECURITY

AI07431

BUS

Interface

8032 Bus

UPSD3212C, UPSD3212CV

82/152

DEVELOPMENT SYSTEM
The uPSD3200 is supported by PSDsoft, a Win-
dows-based software development tool (Win-
dows-95, Windows-98, Windows-NT). A PSD
MODULE design is quickly and easily produced in
a point and click environment. The designer does
not need to enter Hardware Description Language
(HDL) equations, unless desired, to define PSD
MODULE pin functions and memory map informa-
tion. The general design flow is shown in Figure
41. PSDsoft is available from our web site (the ad-

dress is given on the back page of this data sheet)
or other distribution channels.
PSDsoft directly supports a low cost device pro-
grammer from ST: FlashLINK (JTAG). The pro-
grammer may be purchased through your local
distributor/representative. The uPSD3200 is also
supported by third party device programmers. See
our web site for the current list.

Figure 41. PSDsoft Express Development Tool

Merge MCU Firmware with

PSD Module Configuration

PSD Programmer

*.OBJ FILE

FlashLINK (JTAG)

A composite object file is created

containing MCU firmware and

PSD configuration

C Code Generation

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

USER'S CHOICE OF

8032

COMPILER/LINKER

*.OBJ FILE

AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

MCU FIRMWARE

HEX OR S-RECORD

FORMAT

AI07432

Define General Purpose

Logic in CPLD

Point and click definition of combin-
atorial and registered logic in CPLD.

Access HDL is available if needed

Define µPSD Pin and

Node Functions

Point and click definition of

PSD pin functions, internal nodes,

and MCU system memory map

Choose µPSD

83/152

UPSD3212C, UPSD3212CV

PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 61 shows the offset addresses to the PSD
MODULE registers relative to the CSIOP base ad-
dress. The CSIOP space is the 256 bytes of ad-
dress that is allocated by the user to the internal

PSD MODULE registers. Table 61 provides brief
descriptions of the registers in CSIOP space. The
following section gives a more detailed descrip-
tion.

Table 61. Register Address Offset

Note: 1. Other registers that are not part of the I/O ports.

Register Name

Port A Port B

Port C

Port D Other

Description

Data In

Reads Port pin as input, MCU I/O Input Mode

Control

Selects mode between MCU I/O or Address Out

Data Out

Stores data for output to Port pins, MCU I/O
Output Mode

Direction

Configures Port pin as input or output

Drive Select

Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.

Input Macrocell

Reads Input Macrocells

Enable Out

Reads the status of the output enable to the I/O
Port driver

Output Macrocells
AB

20 20

READ reads output of macrocells AB
WRITE loads macrocell flip-flops

Output Macrocells
BC

21 21

READ reads output of macrocells BC
WRITE loads macrocell flip-flops

Mask Macrocells AB

Blocks writing to the Output Macrocells AB

Mask Macrocells BC

Blocks writing to the Output Macrocells BC

Primary Flash
Protection

Read-only Primary Flash Sector Protection

Secondary Flash
memory Protection

Read-only PSD MODULE Security and
Secondary Flash memory Sector Protection

PMMR0

Power Management Register 0

PMMR2

Power Management Register 2

Page E0

Page

VM E2

Places PSD MODULE memory areas in Program
and/or Data space on an individual basis.

UPSD3212C, UPSD3212CV

84/152

PSD MODULE DETAILED OPERATION
As shown in Figure 15, the PSD MODULE con-
sists of five major types of functional blocks:

Memory Block

PLD Blocks

I/O Ports

Power Management Unit (PMU)

JTAG Interface

The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.

MEMORY BLOCKS
The PSD MODULE has the following memory
blocks:

Primary Flash memory

Secondary Flash memory

SRAM

The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided into 4 sec-
tors (16KBytes each). The secondary Flash mem-
ory is divided into 2 sectors (8KBytes each). Each
sector of either memory block can be separately
protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PC3).
This pin is set up using PSDsoft Express Configu-
ration.

Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
"PLDs," page 97). Each of the eight sectors of the
primary Flash memory has a Select signal (FS0-
FS3) which can contain up to three product terms.
Each of the 2 sectors of the secondary Flash
memory has a Select signal (CSBOOT0-
CSBOOT1) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in Pro-
gram or Data space.
Ready/Busy (PC3). This signal can be used to
output the Ready/Busy status of the Flash memo-
ry. The output on Ready/Busy (PC3) is a 0 (Busy)
when Flash memory is being written to,

when

Flash memory is being erased. The output is a 1
(Ready) when no WRITE or Erase cycle is in
progress.
Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus. The MCU can access these
memories in one of two ways:
The MCU can execute a typical bus WRITE or

READ

operation

The MCU can execute a specific Flash memory

instruction that consists of several WRITE and
READ operations. This involves writing specific
data patterns to special addresses within the
Flash memory to invoke an embedded algo-
rithm. These instructions are summarized in Ta-
ble 62.

Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy (PC3).

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UPSD3212C, UPSD3212CV

Instructions
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD MODULE and not executed as
a standard WRITE operation. The instruction is ex-
ecuted when the correct number of bytes are prop-
erly received and the time between two
consecutive bytes is shorter than the time-out pe-
riod. Some instructions are structured to include
READ operations after the initial WRITE opera-
tions.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).
The Flash memory supports the instructions sum-
marized in Table 62:
Flash memory:

Erase memory by chip or sector

Suspend or resume sector erase

Program a Byte

RESET to READ Mode

Read Sector Protection Status

These instructions are detailed in Table 62. For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-
cle. Address signals A15-A12 are Don't Care dur-
ing the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS3 or
CSBOOT0-CSBOOT1) must be selected.
The primary and secondary Flash memories have
the same instruction set. The Sector Select signals
determine which Flash memory is to receive and
execute the instruction. The primary Flash memo-
ry is selected if any one of Sector Select (FS0-
FS3) is High, and the secondary Flash memory is
selected if any one of Sector Select (CSBOOT0-
CSBOOT1) is High.

UPSD3212C, UPSD3212CV

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Table 62. Instructions

Note: 1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label

2. All values are in hexadecimal:

X = Don't care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data READ from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0).
PA is an even address for PSD in Word Programming Mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR , CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) of the sector to be
erased, or verified, must be Active (High).

3. Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) signals are active High, and are defined in PSDsoft Express.
4. Only address Bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles are required when the device is in the READ Mode
6. The RESET Instruction is required to return to the READ Mode after reading the Sector Protection Status, or if the Error Flag Bit

(DQ5) goes High.

7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and

(A1,A0)=(1,0)

9. The system may perform READ and Program cycles in non-erasing sectors, read the Sector Protection Status when in the Suspend

Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.

10. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode.
11. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is

intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection
Status of the primary Flash memory.

Instruction

FS0-FS3 or

CSBOOT0-

CSBOOT1

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

READ

(5)

"Read"
RD @ RA

READ Sector

Protection

(6,8,11)

AAh@
X555h

55h@
XAAAh

90h@
X555h

Read status @
XX02h

Program a Flash

Byte

(11)

AAh@
X555h

55h@
XAAAh

A0h@
X555h

PD@ PA

Flash Sector

Erase

(7,11)

AAh@
X555h

55h@
XAAAh

80h@
X555h

AAh@ X555h

55h@
XAAAh

30h@
SA

30h

(7)

next SA

Flash Bulk

Erase

(11)

AAh@
X555h

55h@
XAAAh

80h@
X555h

AAh@ X555h

55h@
XAAAh

10h@
X555h

Suspend Sector

Erase

(9)

B0h@
XXXXh

Resume Sector

Erase

(10)

30h@
XXXXh

RESET

(6)

F0h@
XXXXh

87/152

UPSD3212C, UPSD3212CV

Power-down Instruction and Power-up Mode
Power-up Mode. The PSD MODULE internal
logic is reset upon Power-up to the READ Mode.
Sector Select (FS0-FS3 and CSBOOT0-
CSBOOT1) must be held Low, and WRITE Strobe
(WR, CNTL0) High, during Power-up for maximum
security of the data contents and to remove the
possibility of a byte being written on the first edge
of WRITE Strobe (WR, CNTL0). Any WRITE cycle
initiation is locked when V

is below V

LKO

READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
READ Memory Contents. Primary Flash memo-
ry and secondary Flash memory are placed in the
READ Mode after Power-up, chip reset, or a
Reset Flash instruction (see Table 62, page 86).
The MCU can read the memory contents of the pri-
mary Flash memory or the

secondary Flash mem-

ory by using READ operations any time the READ
operation is not part of an instruction.
READ Memory Sector Protection Status. The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific WRITE operations and a READ opera-
tion (see Table 62). During the READ operation,
address Bits A6, A1, and A0 must be '0,' '1,' and
'0,' respectively, while Sector Select (FS0-FS3 or
CSBOOT0-CSBOOT1) designates the Flash
memory sector whose protection has to be veri-
fied. The READ operation produces 01h if the
Flash memory sector is protected, or 00h if the
sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See

the section entitled "Flash Memory Sector Pro-
tect," page 92, for register definitions.
Reading the Erase/Program Status Bits. The
Flash memory provides several status bits to be
used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These
status bits minimize the time that the MCU spends
performing these tasks and are defined in Table
63, page 88. The status bits can be read as many
times as needed.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
"Programming Flash Memory," page 89, for de-
tails.
Data Polling Flag (DQ7). When erasing or pro-
gramming in Flash memory, the Data Polling Flag
Bit (DQ7) outputs the complement of the bit being
entered for programming/writing on the DQ7 Bit.
Once the Program instruction or the WRITE oper-
ation is completed, the true logic value is read on
the Data Polling Flag Bit (DQ7) (in a READ opera-
tion).
Data Polling is effective after the fourth WRITE

pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being pro-
grammed or at an address within the Flash
memory sector being erased.

During an Erase cycle, the Data Polling Flag Bit

(DQ7) outputs a '0.' After completion of the cy-
cle, the Data Polling Flag Bit (DQ7) outputs the
last bit programmed (it is a '1' after erasing).

If the byte to be programmed is in a protected

Flash memory sector, the instruction is ignored.

If all the Flash memory sectors to be erased are

protected, the Data Polling Flag Bit (DQ7) is re-
set to '0' for about 100µs, and then returns to the
previous addressed byte. No erasure is per-
formed.

UPSD3212C, UPSD3212CV

88/152

Toggle Flag (DQ6). The Flash memory offers an-
other way for determining when the Program cycle
is completed. During the internal WRITE operation
and when either the FS0-FS3 or CSBOOT0-
CSBOOT1 is true, the Toggle Flag Bit (DQ6) tog-
gles from 0 to 1 and 1 to 0 on subsequent attempts
to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and the data READ on the Data Bus D0-D7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive Reads
yield the same output data.
The Toggle Flag Bit (DQ6) is effective after the

fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase in-
struction).

If the byte to be programmed belongs to a pro-

tected Flash memory sector, the instruction is
ignored.

If all the Flash memory sectors selected for era-

sure are protected, the Toggle Flag Bit (DQ6)
toggles to '0' for about 100µs and then returns to
the previous addressed byte.

Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag Bit (DQ5) is to 0. This

bit is set to '1' when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5) indicates the attempt to program
a Flash memory bit from the programmed state,
'0,' to the erased state, '1,' which is not valid. The
Error Flag Bit (DQ5) may also indicate a Time-out
condition while attempting to program a byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag Bit (DQ5) is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3). The Erase Time-
out Flag Bit (DQ3) reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase Time-out Flag Bit (DQ3) is
reset to 0 after a Sector Erase cycle for a time pe-
riod of 100µs + 20% unless an additional Sector
Erase instruction is decoded. After this time peri-
od, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag Bit (DQ3) is
set to '1.'

Table 63. Status Bit

Note: 1. X = Not guaranteed value, can be read either '1' or '0.'

2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS3 and CSBOOT0-CSBOOT1 are active High.

Functional Block

FS0-FS3/CSBOOT0-

CSBOOT1

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Flash Memory

Data
Polling

Toggle
Flag

Error
Flag

Erase
Time-
out

89/152

UPSD3212C, UPSD3212CV

Programming Flash Memory
Flash memory must be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
'1s' (FFh), and is programmed by setting selected
bits to '0.' The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. Howev-
er, the MCU may program Flash memory byte-by-
byte.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 62).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked support several means to provide status
to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or
Ready/Busy (PC3).
Data Polling. Polling on the Data Polling Flag Bit
(DQ7) is a method of checking whether a Program
or Erase cycle is in progress or has completed.
Figure 42 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm begins. The MCU then reads
the location of the byte to be programmed in Flash
memory to check status. The Data Polling Flag Bit
(DQ7) of this location becomes the complement of
b7 of the original data byte to be programmed. The
MCU continues to poll this location, comparing the
Data Polling Flag Bit (DQ7) and monitoring the Er-
ror Flag Bit (DQ5). When the Data Polling Flag Bit
(DQ7) matches b7 of the original data, and the Er-
ror Flag Bit (DQ5) remains '0,' the embedded algo-
rithm is complete. If the Error Flag Bit (DQ5) is '1,'
the MCU should test the Data Polling Flag Bit
(DQ7) again since the Data Polling Flag Bit (DQ7)
may have changed simultaneously with the Error
Flag Bit (DQ5) (see Figure 42).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the

byte that was written to the Flash memory with the
byte that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 42 still applies. However, the
Data Polling Flag Bit (DQ7) is '0' until the Erase cy-
cle is complete. A '1' on the Error Flag Bit (DQ5) in-
dicates a time-out condition on the Erase cycle; a
'0' indicates no error. The MCU can read any loca-
tion within the sector being erased to get the Data
Polling Flag Bit (DQ7) and the Error Flag Bit
(DQ5).
PSDsoft Express generates ANSI C code func-
tions which implement these Data Polling algo-
rithms.

Figure 42. Data Polling Flowchart

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL

PASS

AI01369B

DQ7

DATA

YES

DQ5

= 1

DQ7

DATA

YES

UPSD3212C, UPSD3212CV

90/152

Data Toggle. Checking the Toggle Flag Bit
(DQ6) is a method of determining whether a Pro-
gram or Erase cycle is in progress or has complet-
ed. Figure 43 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm begins. The MCU then reads
the location of the byte to be programmed in Flash
memory to check status. The Toggle Flag Bit
(DQ6) of this location toggles each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag Bit (DQ6) and mon-
itoring the Error Flag Bit (DQ5). When the Toggle
Flag Bit (DQ6) stops toggling (two consecutive
reads yield the same value), and the Error Flag Bit
(DQ5) remains '0,' the embedded algorithm is
complete. If the Error Flag Bit (DQ5) is '1,' the
MCU should test the Toggle Flag Bit (DQ6) again,
since the Toggle Flag Bit (DQ6) may have
changed simultaneously with the Error Flag Bit
(DQ5) (see Figure 43).

The Error Flag Bit(DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 43 still applies. the Toggle
Flag Bit (DQ6) toggles until the Erase cycle is
complete. A '1' on the Error Flag Bit (DQ5) indi-
cates a time-out condition on the Erase cycle; a '0'

indicates no error. The MCU can read any location
within the sector being erased to get the Toggle
Flag Bit (DQ6) and the Error Flag Bit (DQ5).
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.

Figure 43. Data Toggle Flowchart

READ

DQ5 & DQ6

START

READ DQ6

FAIL

PASS

AI01370B

DQ6

TOGGLE

YES

DQ5

= 1

YES

DQ6

TOGGLE

91/152

UPSD3212C, UPSD3212CV

Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruc-
tion uses six WRITE operations followed by a
READ operation of the status register, as de-
scribed in Table 62. If any byte of the Bulk Erase
instruction is wrong, the Bulk Erase instruction
aborts and the device is reset to the READ Flash
memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled "Pro-
gramming Flash Memory," page 89. The Error
Flag Bit (DQ5) returns a '1' if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD MODULE automatically
does this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six WRITE operations, as described in
Table 62. Additional Flash Sector Erase codes
and Flash memory sector addresses can be writ-
ten subsequently to erase other Flash memory
sectors in parallel, without further coded cycles, if
the additional bytes are transmitted in a shorter
time than the time-out period of about 100µs. The
input of a new Sector Erase code restarts the time-
out period.

The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,'
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is '1,' the time-out period
has expired and the embedded algorithm is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase
instructions abort the cycle that is currently in
progress, and reset the device to READ Mode.
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled "Pro-
gramming Flash Memory," page 89.

During execution of the Erase cycle, the Flash
memory accepts only RESET and Suspend Sec-
tor Erase instructions. Erasure of one Flash mem-
ory sector may be suspended, in order to read
data from another Flash memory sector, and then
resumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend the cycle by writ-
ing 0B0h to any address when an appropriate
Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1)
is High. (See Table 62). This allows reading of
data from another Flash memory sector after the
Erase cycle has been suspended. Suspend Sec-
tor Erase is accepted only during an Erase cycle
and defaults to READ Mode. A Suspend Sector
Erase instruction executed during an Erase time-
out period, in addition to suspending the Erase cy-
cle, terminates the time out period.
The Toggle Flag Bit (DQ6) stops toggling when the
internal logic is suspended. The status of this bit
must be monitored at an address within the Flash
memory sector being erased. The Toggle Flag Bit
(DQ6) stops toggling between 0.1µs and 15µs af-
ter the Suspend Sector Erase instruction has been
executed. The Flash memory is then automatically
set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
Attempting to read from a Flash memory sector

that was being erased outputs invalid data.

Reading from a Flash sector that was

not

being

erased is valid.

The Flash memory

cannot

be programmed, and

only responds to Resume Sector Erase and
Reset Flash instructions (READ is an operation
and is allowed).

If a Reset Flash instruction is received, data in

the Flash memory sector that was being erased
is invalid.

Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
erase cycle may be resumed with this instruction.
The Resume Sector Erase instruction consists of
writing 030h to any address while an appropriate
Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1)
is High. (See Table 62.)

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Specific Features
Flash Memory Sector Protect. Each primary
and secondary Flash memory sector can be sepa-
rately protected against Program and Erase cy-
cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro-
gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec-
tors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Pro-
grammer. The MCU can read (but cannot change)
the sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection regis-

ters (in the CSIOP block). See Table 64 and Table
65.
Reset Flash. The Reset Flash instruction con-
sists of one WRITE cycle (see Table 62). It can
also be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
Reading the Flash Protection Status or Flash ID
An Error condition has occurred (and the device

has set the Error Flag Bit (DQ5) to '1' during a
Flash memory Program or Erase cycle.

The Reset Flash instruction puts the Flash memo-
ry back into normal READ Mode. If an Error condi-
tion has occurred (and the device has set the Error
Flag Bit (DQ5) to '1' the Flash memory is put back
into normal READ Mode within a few milliseconds
of the Reset Flash instruction having been issued.
The Reset Flash instruction is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within a
few milliseconds.

Table 64. Sector Protection/Security Bit Definition Flash Protection Register

Note: Bit Definitions:

Sec_Prot

1 = Primary Flash memory or secondary Flash memory Sector is write-protected.

Sec_Prot

0 = Primary Flash memory or secondary Flash memory Sector is not write-protected.

Table 65. Sector Protection/Security Bit Definition Secondary Flash Protection Register

Note: Bit Definitions:

Sec_Prot

1 = Secondary Flash memory Sector is write-protected.

Sec_Prot

0 = Secondary Flash memory Sector is not write-protected.

Security_Bit

0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Security_Bit

not used

Sec1_Prot

Sec0_Prot

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UPSD3212C, UPSD3212CV

SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Standby (V

STBY

, PC2). If you have an

external battery connected to the uPSD3200, the
contents of the SRAM are retained in the event of
a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switchover to the
battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (V

BATON

, PC4) is High

with the supply voltage falls below the battery volt-
age and the battery on Voltage Standby (V

STBY

PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Standby (V

STBY

PC2) and Battery-on Indicator (V

BATON

, PC4) are

all configured using PSDsoft Express Configura-
tion.
Sector Select and SRAM Select
Sector Select (FS0-FS3, CSBOOT0-CSBOOT1)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDsoft Express. The following rules ap-
ply to the equations for these signals:
1. Primary Flash memory and secondary Flash

memory Sector Select signals must

not

be larg-

er than the physical sector size.

2. Any primary Flash memory sector must

not

mapped in the same memory space as another
Flash memory sector.

3. A secondary Flash memory sector must

not

mapped in the same memory space as another
secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must

not

overlap.

5. A secondary Flash memory sector

may

overlap

a primary Flash memory sector. In case of over-

lap, priority is given to the secondary Flash
memory sector.

6. SRAM, I/O, and Peripheral I/O spaces

may

overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.

Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example.
Note: An equation that defined FS1 to anywhere
in the range of 8000h to BFFFh would

not

be valid.

Figure 44 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must

not

overlap. Level one has the highest priority and

level 3 has the lowest.

Figure 44. Priority Level of Memory and I/O
Components in the PSD MODULE

Level 1

SRAM, I /O, or
Peripheral I /O

Level 2

Secondary

Non-Volatile Memory

Highest Priority

Lowest Priority

Level 3

Primary Flash Memory

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Memory Select Configuration in Program and
Data Spaces. The MCU Core has separate ad-
dress spaces for Program memory and Data
memory. Any of the memories within the PSD
MODULE can reside in either space or both spac-
es. This is controlled through manipulation of the
VM Register that resides in the CSIOP space.
The VM Register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.

For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM Register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired. Table 66 de-
scribes the VM Register.

Table 66. VM Register

Bit 7

PIO_EN

Bit 6

Bit 5

Bit 4

Primary

FL_Data

Bit 3

Secondary Data

Bit 2

Primary

FL_Code

Bit 1

Secondary Code

Bit 0

SRAM_Code

0 = disable
PIO Mode

not used

0 = RD
can't
access
Flash
memory

0 = RD can't
access Secondary
Flash memory

0 = PSEN
can't
access
Flash
memory

0 = PSEN can't
access Secondary
Flash memory

0 = PSEN
can't
access
SRAM

1= enable
PIO Mode

not used

1 = RD
access
Flash
memory

1 = RD access
Secondary Flash
memory

1 = PSEN
access
Flash
memory

1 = PSEN access
Secondary Flash
memory

1 = PSEN
access
SRAM

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UPSD3212C, UPSD3212CV

Separate Space Mode. Program space is sepa-
rated from Data space. For example, Program Se-
lect Enable (PSEN) is used to access the program
code from the primary Flash memory, while READ
Strobe (RD) is used to access data from the sec-
ondary Flash memory, SRAM and I/O Port blocks.
This configuration requires the VM Register to be
set to 0Ch (see Figure 45).

Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN) or READ
Strobe (RD). For example, to configure the prima-
ry Flash memory in Combined space, Bits b2 and
b4 of the VM Register are set to '1' (see Figure 46).

Figure 45. Separate Space Mode

Figure 46. Combined Space Mode

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-1

FS0-FS3

PSEN

AI07433

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-1

FS0-FS3

VM REG BIT 2

PSEN

VM REG BIT 0

VM REG BIT 1

VM REG BIT 3

VM REG BIT 4

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Page Register
The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0-
FS3, CSBOOT0-CSBOOT1), and SRAM Select
(RS0) equations.

If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 47 shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.

Figure 47. Page Register

RESET

D 0 - D 7

R / W

D 0

Q 0

Q 1

Q 2

Q 3

Q 4

Q 5

Q 6

Q 7

D 1

D 2

D 3

D 4

D 5

D 6

D 7

PAGE

REGISTER

PGR0

PGR1

PGR2

PGR3

DPLD

AND

CPLD

INTERNAL PSD MODULE
SELECTS
AND LOGIC

PLD

PGR4

PGR5

PGR6

PGR7

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UPSD3212C, UPSD3212CV

PLDS
The PLDs bring programmable logic functionality
to the uPSD. After specifying the logic for the
PLDs in PSDsoft Express, the logic is pro-
grammed into the device and available upon Pow-
er-up.

Table 67. DPLD and CPLD Inputs

Note: 1. These inputs are not available in the 52-pin package.

The PSD MODULE contains two PLDs: the De-
code PLD (DPLD), and the Complex PLD (CPLD).
The PLDs are briefly discussed in the next few
paragraphs, and in more detail in the section enti-
tled "Decode PLD (DPLD)," page 99, and the sec-
tion entitled "Complex PLD (CPLD)," page 100.
Figure 48 shows the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for PSD MODULE components, such as
memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the Out-
put Macrocells (OMC), Input Macrocells (IMC),
and the AND Array. The CPLD can also be used
to generate External Chip Select (ECS1-ECS2)
signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
The PLD input signals consist of internal MCU sig-
nals and external inputs from the I/O ports. The in-
put signals are shown in Table 67.
The Turbo Bit in PSD MODULE
The PLDs can minimize power consumption by
switching off when inputs remain unchanged for
an extended time of about 70ns. Resetting the
Turbo Bit to '0' (Bit 3 of PMMR0) automatically
places the PLDs into standby if no inputs are
changing. Turning the Turbo Mode off increases
propagation delays while reducing power con-
sumption. See the section entitled "POWER MAN-
AGEMENT," page 113, on how to set the Turbo
Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.

Input Source

Input Name

Number

Signals

MCU Address Bus

A15-A0

MCU Control Signals

PSEN, RD, WR,
ALE

RESET

RST

Power-down PDN

Port A Input

Macrocells

PA7-PA0 8

Port B Input
Macrocells

PB7-PB0 8

Port C Input
Macrocells

PC7, PC4-PC2

Port D Inputs

PD2-PD1 2

Page Register

PGR7-PGR0

Macrocell AB
Feedback

MCELLAB.FB7-
FB0

Macrocell BC
Feedback

MCELLBC.FB7-
FB0

Flash memory
Program Status Bit

Ready/Busy

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UPSD3212C, UPSD3212CV

Decode PLD (DPLD)
The DPLD, shown in Figure 49, is used for decod-
ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:
4 Sector Select (FS0-FS3) signals for the prima-

ry Flash memory (three product terms each)

2 Sector Select (CSBOOT0-CSBOOT1) signals

for the secondary Flash memory (three product
terms each)

1 internal SRAM Select (RS0) signal (two prod-

uct terms)

1 internal CSIOP Select signal (selects the PSD

MODULE registers)

2 internal Peripheral Select signals (Peripheral

I/O Mode).

Figure 49. DPLD Logic Array

Note: 1. Port A inputs are not available in the 52-pin package

2. Inputs from the MCU module

(INPUTS)

(20)

(8)

(16)

(1)

PDN (APD OUTPUT)

I /O PORTS (PORT A,B,C)1

(8)

PGR0 - PGR7

(8)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

A[15:0]2

(2)

(4)

PD[2:1]

PSEN, RD, WR, ALE2

(1)

RESET

RD_BSY

RS0

CSIOP

PSEL0

PSEL1

4 PRIMARY FLASH
MEMORY SECTOR
SELECTS

SRAM SELECT

I/O DECODER
SELECT

PERIPHERAL I/O
MODE SELECT

CSBOOT 0

CSBOOT 1

FS0

AI07436

FS1

FS2

FS3

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Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate External Chip Select
(ECS1-ECS2), routed to Port D.
Although External Chip Select (ECS1-ECS2) can
be produced by any Output Macrocell (OMC),
these External Chip Select (ECS1-ECS2) on Port
D do not consume any Output Macrocells (OMC).
As shown in Figure 48, the CPLD has the following
blocks:

20 Input Macrocells (IMC)

16 Output Macrocells (OMC)

Macrocell Allocator

Product Term Allocator

AND Array capable of generating up to 137
product terms

Four I/O Ports.

Each of the blocks are described in the sections
that follow.

The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD MODULE inter-
nal data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.

Figure 50. Macrocell and I/O Port

I/O PORTS

CPLD MACROCELLS

INPUT MACROCELLS

LATCHED

ADDRESS OUT

MUX

Q D

PDR

DATA

PRODUCT TERM

ALLOCATOR

DIR

REG.

SELECT

INPUT

PRODUCT TERMS

FROM OTHER

MACROCELLS

POLARITY
SELECT

UP TO 10

PRODUCT TERMS

CLOCK
SELECT

DI LD

D/T

D/T/JK FF

SELECT

PT CLEAR

PT
CLOCK

GLOBAL
CLOCK

PT OUTPUT ENABLE (OE)

MACROCELL FEEDBACK

I/O PORT INPUT

ALE

PT INPUT LATCH GATE/CLOCK

MCU LOAD

PT PRESET

MCU DATA IN

COMB.

/REG

SELECT

MACROCELL

I/O PORT

ALLOC.

CPLD

OUTPUT

TO OTHER I/O PORTS

PLD INPUT BUS

MCU ADDRESS / DATA BUS

MACROCELL

OUT TO

MCU

DATA
LOAD

CONTROL

AND ARRAY

CPLD OUTPUT

I/O PIN

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UPSD3212C, UPSD3212CV

Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDsoft, the
Macrocell Allocator block assigns it to either Port A
or B. The same is true for a McellBC output on Port
B or C. Table 68 shows the macrocells and port
assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 51. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the

XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in PS-
Dsoft. The flip-flop's clock, preset, and clear inputs
may be driven from a product term of the AND Ar-
ray. Alternatively, CLKIN (PD1) can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of CLKIN (PD1). The
preset and clear are active High inputs. Each clear
input can use up to two product terms.

Table 68. Output Macrocell Port and Data Bit Assignments

Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package.

2. Port PC0, PC1, PC5 and PC6 are assigned to JTAG pins, and are not available as macrocell outputs

Output

Macrocell

Port

Assignment

(1)

Native Product Terms

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellAB0

Port A0, B0

McellAB1

Port A1, B1

McellAB2

Port A2, B2

McellAB3

Port A3, B3

McellAB4

Port A4, B4

McellAB5

Port A5, B5

McellAB6

Port A6, B6

McellAB7

Port A7, B7

McellBC0

Port B0

(2)

McellBC1

Port B1

(2)

McellBC2

Port B2, C2

McellBC3

Port B3, C3

McellBC4

Port B4, C4

McellBC5

Port B5

(2)

McellBC6

Port B6

(2)

McellBC7

Port B7, C7

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Product Term Allocator
The CPLD has a Product Term Allocator. PSDsoft
uses the Product Term Allocator to borrow and
place product terms from one macrocell to anoth-
er. The following list summarizes how product
terms are allocated:

McellAB0-McellAB7 all have three native
product terms and may borrow up to six more

McellBC0-McellBC3 all have four native product
terms and may borrow up to five more

McellBC4-McellBC7 all have four native product
terms and may borrow up to six more.

Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then "external" product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.

This is called product term expansion. PSDsoft
Express performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP block (see the
section entitled "I/O PORTS (PSD MODULE)," on
page 104). The flip-flops in each of the 16 Output
Macrocells (OMC) can be loaded from the data
bus by a MCU. Loading the Output Macrocells
(OMC) with data from the MCU takes priority over
internal functions. As such, the preset, clear, and
clock inputs to the flip-flop can be overridden by
the MCU. The ability to load the flip-flops and read
them back is useful in such applications as load-
able counters and shift registers, mailboxes, and
handshaking protocols.

Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of WRITE Strobe (WR,
edge loading) or during the time that WRITE
Strobe (WR) is active (level loading). The method
of loading is specified in PSDsoft Express Config-
uration.

Figure 51. CPLD Output Macrocell

ALLOCATOR

MASK

REG.

PT CLK

CLKIN

FEEDBACK (.FB)

PORT INPUT

AND ARRAY

PLD INPUT BUS

MUX

POLARITY

SELECT

CLR

DIN

COMB/REG

SELECT

PORT
DRIVER

INPUT

MACROCELL

I/O PIN

MACROCELL

ALLOCATOR

MCU DATA BUS

D [ 7:0]

DIRECTION

REGISTER

CLEAR (.RE)

PROGRAMMABLE
FF (D / T/JK /SR)

ENABLE (.OE)

PRESET(.PR)

MACROCELL CS

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UPSD3212C, UPSD3212CV

The OMC Mask Register. There is one Mask
Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a '1,' the MCU is blocked
from writing to the associated Output Macrocells
(OMC). For example, suppose McellAB0-
McellAB3 are being used for a state machine. You
would not want a MCU write to McellAB to over-
write the state machine registers. Therefore, you
would want to load the Mask Register for McellAB
(Mask Macrocell AB) with the value 0Fh.
The Output Enable of the OMC. The Output
Macrocells (OMC) block can be connected to an I/
O port pin as a PLD output. The output enable of
each port pin driver is controlled by a single prod-
uct term from the AND Array, ORed with the Direc-
tion Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft Express.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other

I/O functions. The internal node feedback can be
routed as an input to the AND Array.

Input Macrocells (IMC)
The CPLD has 20 Input Macrocells (IMC), one for
each pin on Ports A and B, and four on Port C. The
architecture of the Input Macrocells (IMC) is
shown in Figure 52. The Input Macrocells (IMC)
are individually configurable, and can be used as
a latch, register, or to pass incoming Port signals
prior to driving them onto the PLD input bus. The
outputs of the Input Macrocells (IMC) can be read
by the MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE). Each product term
output is used to latch or clock four Input Macro-
cells (IMC). Port inputs 3-0 can be controlled by
one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by equations written in PSDsoft (see Ap-
plication Note

AN1171

). Outputs of the Input Mac-

rocells (IMC) can be read by the MCU via the IMC
buffer. See the section entitled "I/O PORTS (PSD
MODULE)," page 104.

Figure 52. Input Macrocell

OUTPUT

MACROCELLS BC

AND

MACROCELL AB

FEEDBACK

AND ARRAY

PLD INPUT BUS

PORT

DRIVER

I/O PIN

MCU DATA BUS

D [ 7: 0]

DIRECTION

REGISTER

MUX

ALE

LATCH

INPUT MACROCELL

ENABLE (.OE)

D FF

INPUT MACROCELL _ RD

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I/O PORTS (PSD MODULE)
There are four programmable I/O ports: Ports A, B,
C, and D in the PSD MODULE. Each of the ports
is eight bits except Port D, which is 3 bits. Each
port pin is individually user configurable, thus al-
lowing multiple functions per port. The ports are
configured using PSDsoft Express Configuration
or by the MCU writing to on-chip registers in the
CSIOP space. Port A is not available in the 52-pin
package.

The topics discussed in this section are:

General Port architecture

Port operating modes

Port Configuration Registers (PCR)

Port Data Registers

Individual Port functionality.

General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 53. Individual Port architectures
are shown in Figure 55 to Figure 58. In general,
once the purpose for a port pin has been defined,

that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 53, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:

Output data from the Data Out register

Latched address outputs

CPLD macrocell output

External Chip Select (ECS1-ECS2) from the
CPLD.

The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).

Figure 53. General I/O Port Architecture

MCU DATA BUS

DATA OUT

REG.

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE)

EXT CS

ALE

READ MUX

CPLD - INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT PIN

DATA OUT

ADDRESS

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The Port pin's tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDsoft, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE) or a product term from
the PLD AND Array. The outputs from the Input
Macrocells (IMC) drive the PLD input bus and can
be read by the MCU. See the section entitled "In-
put Macrocell," page 103.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft, some
by the MCU writing to the Control Registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft must be pro-
grammed into the device and cannot be changed
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
Address Input, and Peripheral I/O Modes are the
only modes that must be defined before program-
ming the device. All other modes can be changed
by the MCU at run-time. See Application Note

AN1171

for more detail.

Table 69 summarizes which modes are available
on each port. Table 72 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O Mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD MODULE are
mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 61.

A port pin can be put into MCU I/O Mode by writing
a '0' to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled "Peripheral I/O Mode,"
page 105. When the pin is configured as an out-

put, the content of the Data Out Register drives the
pin. When configured as an input, the MCU can
read the port input through the Data In buffer. See
Figure 53, page 104.
Ports C and D do not have Control Registers, and
are in MCU I/O Mode by default. They can be used
for PLD I/O if equations are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD's Input Macrocells (IMC), and/or as an out-
put from the CPLD's Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to '0.'
The corresponding bit in the Direction Register
must not be set to '1' if the pin is defined for a PLD
input signal in PSDsoft. The PLD I/O Mode is
specified in PSDsoft by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out Mode

Address Out Mode can be used to drive latched
MCU addresses on to the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a '1' for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
71 for the address output pin assignments on
Ports A and B for various MCUs.
Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a '1.' Figure 54
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be written in PSDsoft. The buffer is tri-stated when
PSEL0 or PSEL1 is low (not active). The PSEN
signal should be "ANDed" in the PSEL equations
to disable the buffer when PSEL resides in the
data space.
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). For more information
on the JTAG Port, see the section entitled "PRO-
GRAMMING IN-CIRCUIT USING THE JTAG SE-
RIAL INTERFACE," page 118.

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Figure 54. Peripheral I/O Mode

Table 69. Port Operating Modes

Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.

2. Port A is not available in the 52-pin package.
3. On pins PC2, PC3, PC4 and PC7 only.

Table 70. Port Operating Mode Settings

Note: N/A = Not Applicable

1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

Table 71. I/O Port Latched Address Output Assignments

Port Mode

Port A

(2)

Port B

Port C

Port D

MCU I/O

Yes

PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs

Yes
No
No
Yes

Yes
Yes
No
Yes

Yes

(3)

No
Yes

No
No
Yes
Yes

Address Out

Yes (A7 0)

Peripheral I/O

Yes

JTAG ISP

Yes

(1)

Mode

Defined in PSDsoft

Control Register

Setting

Direction Register

Setting

VM Register Setting

MCU I/O

Declare pins only

1 = output,
0 = input (Note 1)

N/A

PLD I/O

Logic equations

N/A

(Note

N/A

Address Out
(Port A,B)

Declare pins only

1 (Note 1)

N/A

Peripheral I/O
(Port A)

Logic equations
(PSEL0 & 1)

N/A

PIO Bit = 1

Port A (PA3-PA0)

Port A (PA7-PA4)

Port B (PB3-PB0)

Port B (PB7-PB4)

Address

a3-a0 Address

a7-a4 Address

a3-a0 Address

a7-a4

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

PA0 - PA7

D0 - D7

DATA BUS

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Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 61. The addresses in Table 61 are
the offsets in hexadecimal from the base of the
CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 72, are used for setting the
Port configurations. The default Power-up state for
each register in Table 72 is 00h.
Control Register. Any bit reset to '0' in the Con-
trol Register sets the corresponding port pin to
MCU I/O Mode, and a '1' sets it to Address Out
Mode. The default mode is MCU I/O. Only Ports A
and B have an associated Control Register.
Direction Register. The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to '1' in the Direction Register
causes the corresponding pin to be an output, and
any bit set to '0' causes it to be an input. The de-
fault mode for all port pins is input.
Figure 55, page 109 and Figure 56, page 110
show the Port Architecture diagrams for Ports A/B
and C, respectively. The direction of data flow for
Ports A, B, and C are controlled not only by the di-
rection register, but also by the output enable
product term from the PLD AND Array. If the out-
put enable product term is not active, the Direction
Register has sole control of a given pin's direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 75. Since
Port D only contains two pins (shown in Figure 58),
the Direction Register for Port D has only two bits
active.
Drive Select Register. The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
'1.' The default pin drive is CMOS.

Note: The slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to '1.' The default rate is slow slew.
Table 76, page 108 shows the Drive Register for
Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which
pins the slew rate can be set for.

Table 72. Port Configuration Registers (PCR)

Note: 1. See Table 76 for Drive Register Bit definition.

Table 73. Port Pin Direction Control, Output
Enable P.T. Not Defined

Table 74. Port Pin Direction Control, Output
Enable P.T. Defined

Table 75. Port Direction Assignment Example

Register Name

Port

MCU Access

Control

A,B

WRITE/READ

Direction

A,B,C,D

WRITE/READ

Drive Select

(1)

A,B,C,D

WRITE/READ

Direction Register Bit

Port Pin Mode

0 Input

1 Output

Direction

Register Bit

Output Enable

P.T.

Port Pin Mode

0 0 Input

0 1 Output

1 0 Output

1 1 Output

Bit 7 Bit 6 Bit 5

Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

0 0 0 0 0 1 1 1

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Port Data Registers
The Port Data Registers, shown in Table 77, are
used by the MCU to write data to or read data from
the ports. Table 77 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In. Port pins are connected directly to the
Data In buffer. In MCU I/O Input Mode, the pin in-
put is read through the Data In buffer.
Data Out Register. Stores output data written by
the MCU in the MCU I/O Output Mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to '1.' The contents of the register can
also be read back by the MCU.
Output Macrocells (OMC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU's
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask

Register Bits are not set, writing to the macrocell
loads data to the macrocell flip-flops. See the sec-
tion entitled "PLDs," page 97.
OMC Mask Register. Each OMC Mask Register
Bit corresponds to an Output Macrocell (OMC) flip-
flop. When the OMC Mask Register Bit is set to a
'1,' loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is '0' or un-
blocked.
Input Macrocells (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can be read by the
MCU. See the section entitled "PLDs," page 97.

Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A '1' indicates the driver is in out-
put mode. A '0' indicates the driver is in tri-state
and the pin is in input mode.

Table 76. Drive Register Pin Assignment

Note: 1. NA = Not Applicable.

Table 77. Port Data Registers

Drive

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port A

Open
Drain

Slew
Rate

Port B

Open
Drain

Slew
Rate

Port C

Open
Drain

(1)

Open
Drain

(1)

Port D

(1)

Slew
Rate

(1)

Register Name

Port

MCU Access

Data In

A,B,C,D

READ input on pin

Data Out

A,B,C,D

WRITE/READ

Output Macrocell

A,B,C

READ outputs of macrocells
WRITE loading macrocells flip-flop

Mask Macrocell

A,B,C

WRITE/READ prevents loading into a given
macrocell

Input Macrocell

A,B,C

READ outputs of the Input Macrocells

Enable Out

A,B,C

READ the output enable control of the port driver

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UPSD3212C, UPSD3212CV

Ports A and B Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 55. The two ports can be
configured to perform one or more of the following
functions:

MCU I/O Mode

CPLD Output Macrocells McellAB7-McellAB0
can be connected to Port A or Port B. McellBC7-
McellBC0 can be connected to Port B or Port C.

CPLD Input Via the Input Macrocells (IMC).

Latched Address output Provide latched
address output as per Table 71.

Open Drain/Slew Rate pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be configured
to Open Drain Mode.

Peripheral Mode Port A only (80-pin package)

Figure 55. Port A and Port B Structure

MCU DATA BUS

DATA OUT

REG.

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE)

ALE

READ MUX

CPLD - INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT

A OR B PIN

DATA OUT

ADDRESS

A[ 7:0]

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Port C Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 56):

MCU I/O Mode

CPLD Output McellBC7-McellBC0 outputs
can be connected to Port B or Port C.

CPLD Input via the Input Macrocells (IMC)

In-System Programming (ISP) JTAG pins
(TMS, TCK, TDI, TDO) are dedicated pins for
device programming. (See the section entitled
"PROGRAMMING IN-CIRCUIT USING THE

JTAG SERIAL INTERFACE," page 118, for
more information on JTAG programming.)

Open Drain Port C pins can be configured in
Open Drain Mode

Battery Backup features PC2 can be
configured for a battery input supply, Voltage
Standby (V

STBY

PC4 can be configured as a Battery-on Indicator
(V

BATON

), indicating when V

is less than

BAT

Port C does not support Address Out Mode, and
therefore no Control Register is required.

Figure 56. Port C Structure

Note: 1. ISP or battery back-up

MCU DATA BUS

DATA OUT

REG.

MCELLBC[ 7:0]

ENABLE PRODUCT TERM (.OE)

READ MUX

CPLD - INPUT

DIR REG.

INPUT

MACROCELL

ENABLE OUT

SPECIAL FUNCTION

CONFIGURATION

BIT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT C PIN

DATA OUT

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Port D Functionality and Structure
Port D has two I/O pins (only one pin, PD1, in the
52-pin package). See Figure 57 and Figure 58.
This port does not support Address Out Mode, and
therefore no Control Register is required. Of the
eight bits in the Port D registers, only Bits 2 and 1
are used to configure pins PD2 and PD1.
Port D can be configured to perform one or more
of the following functions:

MCU I/O Mode

CPLD Output External Chip Select (ECS1-
ECS2)

CPLD Input direct input to the CPLD, no Input
Macrocells (IMC)

Slew rate pins can be set up for fast slew rate

Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:

CLKIN (PD1) as input to the macrocells flip-
flops and APD counter

PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.

Figure 57. Port D Structure

MCU DATA BUS

DATA OUT

REG.

ECS[ 2:1]

READ MUX

CPLD - INPUT

DIR REG.

DATA IN

ENABLE PRODUCT

TERM (.OE)

OUTPUT

SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

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POWER MANAGEMENT
All PSD MODULE offers configurable power sav-
ing options. These options may be used individu-
ally or in combinations, as follows:

The primary and secondary Flash memory, and
SRAM blocks are built with power management
technology. In addition to using special silicon
design methodology, power management
technology puts the memories into Standby
Mode when address/data inputs are not
changing (zero DC current). As soon as a
transition occurs on an input, the affected
memory "wakes up," changes and latches its
outputs, then goes back to standby. The
designer does

not

have to do anything special to

achieve Memory Standby Mode when no inputs
are changing--it happens automatically.
The PLD sections can also achieve Standby
Mode when its inputs are not changing, as de-
scribed in the sections on the Power Manage-
ment Mode Registers (PMMR).

As with the Power Management Mode, the
Automatic Power Down (APD) block allows the
PSD MODULE to reduce to standby current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. The APD Unit is described
in more detail in the sections entitled "POWER
MANAGEMENT" page 113.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain time period (MCU is asleep), the APD Unit

initiates Power-down Mode (if enabled). Once in
Power-down Mode, all address/data signals are
blocked from reaching memory and PLDs, and
the memories are deselected internally. This al-
lows the memory and PLDs to remain in
Standby Mode even if the address/data signals
are changing state externally (noise, other de-
vices on the MCU bus, etc.). Keep in mind that
any unblocked PLD input signals that are
changing states keeps the PLD out of Standby
Mode, but not the memories.

PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in Standby Mode even if inputs are changing.
This feature does not block any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memory access time when PSD Chip Select
Input (CSI, PD2) makes its initial transition from
deselected to selected.

The PMMRs can be written by the MCU at run-
time to manage power. The PSD MODULE
supports "blocking bits" in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 62 and Figure 63). Significant power
savings can be achieved by blocking signals
that are not used in DPLD or CPLD logic
equations.

Figure 59. APD Unit

The PSD MODULE has a Turbo Bit in PMMR0.
This bit can be set to turn the Turbo Mode off (the
default is with Turbo Mode turned on). While Turbo
Mode is off, the PLDs can achieve standby current
when no PLD inputs are changing (zero DC cur-

rent). Even when inputs do change, significant
power can be saved at lower frequencies (AC cur-
rent), compared to when Turbo Mode is on. When
the Turbo Mode is on, there is a significant DC cur-
rent component and the AC component is higher.

APD EN
PMMR0 BIT 1=1

ALE

RESET

CSI

CLKIN

TRANSITION

DETECTION

EDGE

DETECT

APD

COUNTER

POWER DOWN
(PDN)

DISABLE BUS
INTERFACE

CSIOP SELECT

FLASH SELECT

SRAM SELECT

CLR

DISABLE
FLASH/SRAM

PLD

SELECT

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Automatic Power-down (APD) Unit and Power-
down Mode. The APD Unit, shown in Figure 59,
puts the PSD MODULE into Power-down Mode by
monitoring the activity of Address Strobe (ALE). If
the APD Unit is enabled, as soon as activity on Ad-
dress Strobe (ALE) stops, a four-bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD MODULE enters Power-down Mode, as dis-
cussed next.
Power-down Mode. By default, if you enable the
APD Unit, Power-down Mode is automatically en-
abled. The device enters Power-down Mode if Ad-
dress Strobe (ALE) remains inactive for fifteen
periods of CLKIN (PD1).
The following should be kept in mind when the
PSD MODULE is in Power-down Mode:

If Address Strobe (ALE) starts pulsing again, the

PSD MODULE returns to normal Operating
mode. The PSD MODULE also returns to nor-
mal Operating mode if either PSD Chip Select
Input (CSI, PD2) is Low or the RESET input is
High.

The MCU address/data bus is blocked from all

memory and PLDs.

Various signals can be blocked (prior to Power-

down Mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1).

Note: Blocking CLKIN (PD1) from the PLDs

does not block CLKIN (PD1) from the APD Unit.

All memories enter Standby Mode and are

drawing standby current. However, the PLD and
I/O ports blocks do

not

go into Standby Mode

because you don't want to have to wait for the
logic and I/O to "wake-up" before their outputs
can change. See Table 78 for Power-down
Mode effects on PSD MODULE ports.

Typical standby current is of the order of micro-

amperes. These standby current values as-
sume that there are no transitions on any PLD
input.

Other Power Saving Options. The PSD MOD-
ULE offers other reduced power saving options
that are independent of the Power-down Mode.
Except for the SRAM Standby and PSD Chip Se-
lect Input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2.

Figure 60. Enable Power-down Flow Chart

Table 78. Power-down Mode's Effect on Ports

Port Function

Pin Level

MCU I/O

No Change

PLD Out

No Change

Address Out

Undefined

Peripheral I/O

Tri-State

Enable APD

Set PMMR0 Bit 1 = 1

PSD Module in Power

Down Mode

ALE idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

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PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo Bit (Bit 3) in PMMR0 (see Table 79).
By setting the bit to '1,' the Turbo Mode is off and
the PLDs consume the specified standby current
when the inputs are not switching for an extended
time of 70ns. The propagation delay time is in-
creased by 10ns (for a 5V device) after the Turbo
Bit is set to '1' (turned off) when the inputs change
at a composite frequency of less than 15MHz.
When the Turbo Bit is reset to '0' (turned on), the
PLDs run at full power and speed. The Turbo Bit
affects the PLD's DC power, AC power, and prop-
agation delay. When the Turbo Mode is off, the
uPSD3200 input clock frequency is reduced by
5MHz from the maximum rated clock frequency.
Blocking MCU control signals with the bits of
PMMR2 (see Table 80, page 116) can further re-
duce PLD AC power consumption.
SRAM Standby Mode (Battery Backup). The
SRAM in the PSD MODULE supports a battery
backup mode in which the contents are retained in
the event of a power loss. The SRAM has Voltage
Standby (V

STBY

, PC2) that can be connected to an

external battery. When V

becomes lower than

STBY

then the SRAM automatically connects to

Voltage Standby (V

STBY

, PC2) as a power source.

The SRAM Standby Current (I

STBY

) is typically 0.5

µA. The SRAM data retention voltage is 2V mini-
mum. The Battery-on Indicator (V

BATON

) can be

routed to PC4. This signal indicates when the V

has dropped below V

STBY

PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the PSD MODULE
Flash memory, SRAM, and I/O blocks for READ or
WRITE operations. A High on PSD Chip Select In-
put (CSI, PD2) disables the Flash memory, and
SRAM, and reduces power consumption. Howev-
er, the PLD and I/O signals remain operational
when PSD Chip Select Input (CSI, PD2) is High.

Input Clock
CLKIN (PD1) can be turned off, to the PLD to save
AC power consumption. CLKIN (PD1) is an input
to the PLD AND Array and the Output Macrocells
(OMC).

During Power-down Mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting Bits 4 or 5
to a '1' in PMMR0.
Input Control Signals
The PSD MODULE provides the option to turn off
the MCU signals (WR, RD, PSEN, and Address
Strobe (ALE)) to the PLD to save AC power con-
sumption (see Table 81, page 116). These control
signals are inputs to the PLD AND Array. During
Power-down Mode, or, if any of them are not being
used as part of the PLD logic equation, these con-
trol signals should be disabled to save AC power.
They are disconnected from the PLD AND Array
by setting Bits 2, 3, 4, 5, and 6 to a '1' in PMMR2.

Table 79. Power Management Mode Registers PMMR0

Bit 0

Not used, and should be set to zero.

Bit 1

APD Enable

0 = off Automatic Power-down (APD) is disabled.

1 = on Automatic Power-down (APD) is enabled.

Bit 2

Not used, and should be set to zero.

Bit 3

PLD Turbo

0 = on PLD Turbo Mode is on

1 = off

PLD Turbo Mode is off, saving power.
uPSD3200 operates at 5MHz below the maximum rated clock frequency

Bit 4

PLD Array clk

0 = on

CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo Bit is '0.'

1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.

Bit 5

PLD MCell clk

0 = on CLKIN (PD1) input to the PLD macrocells is connected.

1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.

Bit 6

Not used, and should be set to zero.

Bit 7

Not used, and should be set to zero.

UPSD3212C, UPSD3212CV

116/152

Table 80. Power Management Mode Registers PMMR2

Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.

Table 81. APD Counter Operation

Bit 0

Not used, and should be set to zero.

Bit 1

Not used, and should be set to zero.

Bit 2

PLD Array
WR

0 = on WR input to the PLD AND Array is connected.

1 = off WR input to PLD AND Array is disconnected, saving power.

Bit 3

PLD Array
RD

0 = on RD input to the PLD AND Array is connected.

1 = off RD input to PLD AND Array is disconnected, saving power.

Bit 4

PLD Array
PSEN

0 = on PSEN input to the PLD AND Array is connected.

1 = off PSEN input to PLD AND Array is disconnected, saving power.

Bit 5

PLD Array
ALE

0 = on ALE input to the PLD AND Array is connected.

1 = off ALE input to PLD AND Array is disconnected, saving power.

Bit 6

Not used, and should be set to zero.

Bit 7

Not used, and should be set to zero.

APD Enable Bit

ALE Level

APD Counter

0 X

Not

Counting

1 Pulsing

Not

Counting

0 or 1

Counting (Generates PDN after 15 Clocks)

117/152

UPSD3212C, UPSD3212CV

RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD MODULE requires a Re-
set (RESET) pulse of duration t

NLNH-PO

after V

is steady. During this period, the device loads in-
ternal configurations, clears some of the registers
and sets the Flash memory into operating mode.
After the rising edge of Reset (RESET), the PSD
MODULE remains in the Reset Mode for an addi-
tional period, t

OPR

, before the first memory access

is allowed.

The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS3 and
CSBOOT0-CSBOOT1) must all be Low, WRITE
Strobe (WR, CNTL0) High, during Power-on
RESET for maximum security of the data contents
and to remove the possibility of a byte being writ-
ten on the first edge of WRITE Strobe (WR). Any
Flash memory WRITE cycle initiation is prevented
automatically when V

is below V

LKO

Warm RESET
Once the device is up and running, the PSD MOD-
ULE can be reset with a pulse of a much shorter
duration, t

NLNH

. The same t

OPR

period is needed

before the device is operational after a Warm
RESET. Figure 61 shows the timing of the Power-
up and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table 82 shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET, and
Power-down Mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal Configuration bits are
loaded. This loading is completed typically long
before the V

ramps up to operating level. Once

the PLD is active, the state of the outputs are de-
termined by the PLD equations.

Figure 61. Reset (RESET) Timing

Table 82. Status During Power-on RESET, Warm RESET and Power-down Mode

Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.

Port Configuration

Power-on RESET Warm

RESET Power-down

Mode

MCU I/O

Input mode

Unchanged

PLD Output

Valid after internal PSD
configuration bits are
loaded

Valid

Depends on inputs to PLD
(addresses are blocked in
PD Mode)

Address

Out

Tri-stated Tri-stated Not

defined

Peripheral

I/O

Tri-stated Tri-stated Tri-stated

Register Power-on

RESET Warm

RESET Power-down

Mode

PMMR0 and PMMR2

Cleared to '0'

Unchanged

Macrocells flip-flop status

Cleared to '0' by internal
Power-on RESET

Depends on .re and .pr
equations

VM Register

(1)

Initialized, based on the
selection in PSDsoft
Configuration menu

Unchanged

All other registers

Cleared to '0'

Unchanged

tNLNH-PO

tOPR

AI07437

RESET

tNLNH

tOPR

(min)

Power-On Reset

Warm Reset

UPSD3212C, UPSD3212CV

118/152

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface pins (TMS, TCK, TDI,
TDO) are dedicated pins on Port C (see Table 83).
All memory blocks (primary and secondary Flash
memory), PLD logic, and PSD MODULE Configu-
ration Register Bits may be programmed through
the JTAG Serial Interface block. A blank device
can be mounted on a printed circuit board and pro-
grammed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.

By default, on a blank device (as shipped from the
factory or after erasure), four pins on Port C are
the basic JTAG signals TMS, TCK, TDI, and TDO

Standard JTAG Signals
At power-up, the standard JTAG pins are inputs,
waiting for a JTAG serial command from an exter-
nal JTAG controller device (such as FlashLINK or
Automated Test Equipment). When the enabling
command is received, TDO becomes an output
and the JTAG channel is fully functional. The
same command that enables the JTAG channel
may optionally enable the two additional JTAG sig-
nals, TSTAT and TERR.
The RESET input to the uPS3200 should be active
during JTAG programming. The active RESET
puts the MCU module into RESET Mode while the
PSD Module is being programmed. See Applica-
tion Note AN1153 for more details on JTAG In-
System Programming (ISP).
The uPSD321X Devices supports JTAG In-Sys-
tem-Configuration (ISC) commands, but not
Boundary Scan. The PSDsoft Express software
tool and FlashLINK JTAG programming cable im-
plement the JTAG In-System-Configuration (ISC)
commands.

Table 83. JTAG Port Signals

JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an "ISC_ENABLE" command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on uPDS
signals instead of having to scan the status out se-
rially using the standard JTAG channel. See Appli-
cation Note

AN1153

TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
"ISC_CLEAR" command is executed or a chip Re-
set (RESET) pulse is received after an
"ISC_DISABLE" command.
TSTAT behaves the same as Ready/Busy de-
scribed in the section entitled "Ready/Busy (PC3),"
page 84. TSTAT is High when the PSD MODULE
device is in READ Mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being writ-
ten to the secondary Flash memory.
TSTAT and TERR can be configured as "open
drain" type signals during an "ISC_ENABLE" com-
mand.
Security and Flash memory Protection
When the Security Bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.

INITIAL DELIVERY STATE
When delivered from ST, the uPSD321X Devices
have all bits in the memory and PLDs set to '1.'
The code, configuration, and PLD logic are loaded
using the programming procedure. Information for
programming the device is available directly from
ST. Please contact your local sales representa-
tive.

Port C Pin

JTAG Signals

Description

PC0

TMS

Mode Select

PC1

TCK

Clock

PC3

TSTAT

Status (optional)

PC4

TERR

Error Flag (optional)

PC5

TDI

Serial Data In

PC6

TDO

Serial Data Out

119/152

UPSD3212C, UPSD3212CV

AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the uPSD321X Devices:

DC Electrical Specification

AC Timing Specification

PLD Timing

Combinatorial Timing

Synchronous Clock Mode

Asynchronous Clock Mode

Input Macrocell Timing

MCU Module Timing

READ Timing

WRITE Timing

Power-down and RESET Timing

The following are issues concerning the parame-
ters presented:
In the DC specification the supply current is giv-

en for different modes of operation.

The AC power component gives the PLD, Flash

memory, and SRAM mA/MHz specification. Fig-
ure 62 and Figure 63 show the PLD mA/MHz as
a function of the number of Product Terms (PT)
used.

In the PLD timing parameters, add the required

delay when Turbo Bit is '0.'

Figure 62. PLD I

/Frequency Consumption (5V range)

Figure 63. PLD I

/Frequency Consumption (3V range)

100

110

= 5V

20 25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

 (mA)

TURBO ON (100%)

TURBO ON (25%)

TURBO OFF

PT 100%

PT 25%

AI02894

= 3V

20 25

 (mA)

TURBO ON (100%)

TURBO ON (25%)

TURBO OFF

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

PT 100%

PT 25%

AI03100

UPSD3212C, UPSD3212CV

120/152

Table 84. PSD MODULE Example, Typ. Power Calculation at V

= 5.0V (Turbo Mode Off)

Conditions

MCU Clock Frequency

= 12MHz

Highest Composite PLD input frequency

(Freq PLD)

= 8MHz

MCU ALE frequency (Freq ALE)

= 2MHz

% Flash memory
Access

= 80%

% SRAM access

= 15%

% I/O access

= 5% (no additional power above base)

Operational Modes

% Normal

= 40%

% Power-down Mode

= 60%

Number of product terms used

(from fitter report)

= 45 PT

% of total product terms

= 45/182 = 24.7%

Turbo Mode

= Off

Calculation (using typical values)

total

= I

(MCUactive) x %MCUactive + I

(PSDactive) x %PSDactive + I

(pwrdown) x %pwrdown

(MCUactive)

= 20mA

(pwrdown)

= 250µA

(PSDactive)

= I

(ac) + I

(dc)

= %flash x 2.5 mA/MHz x Freq ALE

+ %SRAM x 1.5 mA/MHz x Freq ALE

+ % PLD x (from graph using Freq PLD)

= 0.8 x 2.5 mA/MHz x 2MHz + 0.15 x 1.5 mA/MHz x 2MHz + 24 mA

= (4 + 0.45 + 24) mA

= 28.45mA

total

= 20mA x 40% + 28.45mA x 40% + 250µA x 60%

= 8mA + 11.38mA + 150µA

= 19.53mA

This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/
O pins being disconnected and I

OUT

= 0 mA.

121/152

UPSD3212C, UPSD3212CV

MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.

Table 85. Absolute Maximum Ratings

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500

, R2=500

)

Symbol

Parameter

Min.

Max.

Unit

STG

Storage Temperature

125

°C

LEAD

Lead Temperature during Soldering (20 seconds max.)

(1)

235

°C

Input and Output Voltage (Q = V

or Hi-Z)

0.5

6.5

Supply Voltage

0.5

6.5

Device Programmer Supply Voltage

0.5

14.0

ESD

Electrostatic Discharge Voltage (Human Body Model)

2000

UPSD3212C, UPSD3212CV

122/152

DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-

ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.

Table 86. Operating Conditions (5V Devices)

Table 87. Operating Conditions (3V Devices)

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

4.5

5.5

Ambient Operating Temperature (industrial)

°C

Ambient Operating Temperature (commercial)

°C

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

3.0

3.6

Ambient Operating Temperature (industrial)

°C

Ambient Operating Temperature (commercial)

°C

UPSD3212C, UPSD3212CV

124/152

Table 89. DC Characteristics (5V Devices)

Symbol

Parameter

Test Condition

(in addition to those

in Table 86, page 122)

Min.

Typ.

Max.

Unit

Input High Voltage (Ports 1, 2,
3, 4[Bits 7,6,5,4,3,1,0], XTAL1,
RESET)

4.5V < V

< 5.5V

0.7V

+ 0.5

IH1

Input High Voltage (Ports A, B,
C, D, 4[Bit 2])

4.5V < V

< 5.5V

2.0

+ 0.5

Input Low Voltage (Ports 1, 2,
3, 4[Bits 7,6,5,4,3,1,0], XTAL1,
RESET)

4.5V < V

< 5.5V

0.5

0.3V

IL1

Input Low Voltage
(Ports A, B, C, D)

4.5V < V

< 5.5V

0.5

0.8

Input Low Voltage
(Port 4[Bit 2])

4.5V < V

< 5.5V

0.5

0.8

Output Low Voltage
(Ports A,B,C,D)

= 20µA

= 4.5V

0.01

0.1

= 8mA

= 4.5V

0.25

0.45

OL1

Output Low Voltage
(Ports 1,2,3,4, WR, RD)

= 1.6mA

0.45

OL2

Output Low Voltage
(Port 0, ALE, PSEN)

= 3.2mA

0.45

Output High Voltage
(Ports A,B,C,D)

= 20µA

= 4.5V

4.4

4.49

= 2mA

= 4.5V

2.4

3.9

OH1

Output High Voltage
(Ports 1,2,3,4, WR, RD)

= 80µA

2.4

= 10µA

4.05

OH2

Output High Voltage (Port 0 in

ext. Bus Mode, ALE, PSEN)

= 800µA

2.4

= 80µA

4.05

OH3

Output High Voltage V

STBYON

= 1µA

STBY

0.8

LVR

Low Voltage RESET

0.1V hysteresis

3.75

4.0

4.25

XTAL Open Bias Voltage
(XTAL1, XTAL2)

= 3.2mA

2.0

3.0

LKO

(min) for Flash Erase and

Program

2.5

4.2

STBY

SRAM (PSD) Standby Voltage

2.0

0.2

SRAM (PSD) Data Retention
Voltage

Only on V

STBY

Logic '0' Input Current
(Ports 1,2,3,4)

= 0.45V

(0V for Port 4[pin 2])

µA

Logic 1-to-0 Transition Current
(Ports 1,2,3,4)

= 3.5V

(2.5V for Port 4[pin 2])

650

µA

125/152

UPSD3212C, UPSD3212CV

Note: 1. I

(Power-down Mode) is measured with:

XTAL1=V

; XTAL2=not connected; RESET=V

; Port 0 =V

; all other pins are disconnected. PLD not in Turbo Mode.

2. I

CC_CPU

(active mode) is measured with:

XTAL1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+0.5V, V

= Vcc 0.5V, XTAL2 = not connected; RESET=V

; Port 0=V

; all

other pins are disconnected. I

would be slightly higher if a crystal oscillator is used (approximately 1mA).

3. I

CC_CPU

(Idle Mode) is measured with:

XTAL1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+0.5V, V

= V

0.5V, XTAL2 = not connected; Port 0 = V

;

RESET=V

; all other pins are disconnected.

4. See Figure 62 for the PLD current calculation.
5. I/O current = 0 mA, all I/O pins are disconnected.

STBY

SRAM (PSD) Standby Current
(V

STBY

input)

= 0V

0.5

µA

IDLE

SRAM (PSD) Idle Current
(V

STBY

input)

> V

STBY

0.1

µA

RST

Reset Pin Pull-up Current
(RESET)

= V

µA

XTAL Feedback Resistor
Current (XTAL1)

XTAL1 = V

XTAL2 = V

µA

Input Leakage Current

< V

µA

Output Leakage Current

0.45 < V

OUT

< V

µA

(1)

Power-down Mode

= 5.5V

LVD logic disabled

250

µA

LVD logic enabled

380

µA

CC_CPU

(2,3,5)

Active (12MHz)

= 5V

Idle (12MHz)

Active (24MHz)

= 5V

Idle (24MHz)

Active (40MHz)

= 5V

Idle (40MHz)

CC_PSD

(DC)

(5)

Operating
Supply Current

PLD Only

PLD_TURBO = Off,

f = 0MHz

(4)

µA/PT

(5)

PLD_TURBO = On,

f = 0MHz

400

700

µA/PT

Flash
memory

During Flash memory

WRITE/Erase Only

Read only, f = 0MHz

SRAM

f = 0MHz

CC_PSD

(AC)

(5)

PLD AC Base

Note 4

Flash memory AC Adder

2.5

3.5

mA/

MHz

SRAM AC Adder

1.5

3.0

mA/

MHz

Symbol

Parameter

Test Condition

(in addition to those

in Table 86, page 122)

Min.

Typ.

Max.

Unit

UPSD3212C, UPSD3212CV

126/152

Table 90. DC Characteristics (3V Devices)

Symbol

Parameter

Test Condition

(in addition to those

in Table 87, page 122)

Min.

Typ.

Max.

Unit

Input High Voltage (Ports 1, 2,
3, 4[Bits 7,6,5,4,3,1,0], A, B, C,
D, XTAL1, RESET)

3.0V < V

< 3.6V

0.7V

+ 0.5

IH1

Input High Voltage (Port 4[Bit
2])

3.0V < V

< 3.6V

2.0

+ 0.5

Input High Voltage (Ports 1, 2,
3, 4[Bits 7,6,5,4,3,1,0], XTAL1,
RESET)

3.0V < V

< 3.6V

0.5

0.3V

IL1

Input Low Voltage
(Ports A, B, C, D)

3.0V < V

< 3.6V

0.5

0.8

Input Low Voltage
(Port 4[Bit 2])

3.0V < V

< 3.6V

0.5

0.8

Output Low Voltage
(Ports A,B,C,D)

= 20µA

= 3.0V

0.01

0.1

= 4mA

= 3.0V

0.15

0.45

OL1

Output Low Voltage
(Ports 1,2,3,4, WR, RD)

= 1.6mA

0.45

= 100µA

0.3

OL2

Output Low Voltage
(Port 0, ALE, PSEN)

= 3.2mA

0.45

= 200µA

0.3

Output High Voltage
(Ports A,B,C,D)

= 20µA

= 3.0V

2.9

2.99

= 1mA

= 3.0V

2.4

2.6

OH1

Output High Voltage
(Ports 1,2,3,4, WR, RD)

= 20µA

2.0

= 10µA

2.7

OH2

Output High Voltage (Port 0 in

ext. Bus Mode, ALE, PSEN)

= 800µA

2.0

= 80µA

2.7

OH3

Output High Voltage V

STBYON

= 1µA

STBY

0.8

LVR

Low Voltage Reset

0.1V hysteresis

2.3

2.5

2.7

XTAL Open Bias Voltage
(XTAL1, XTAL2)

= 3.2mA

1.0

2.0

LKO

(min) for Flash Erase and

Program

1.5

2.2

STBY

SRAM (PSD) Standby Voltage

2.0

0.2

SRAM (PSD) Data Retention
Voltage

Only on V

STBY

Logic '0' Input Current
(Ports 1,2,3,4)

= 0.45V

(0V for Port 4[pin 2])

µA

127/152

UPSD3212C, UPSD3212CV

Note: 1. I

(Power-down Mode) is measured with:

XTAL1=V

; XTAL2=not connected; RESET=V

; Port 0 =V

; all other pins are disconnected. PLD not in Turbo mode.

2. I

CC_CPU

(active mode) is measured with:

XTAL1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+0.5V, V

= Vcc 0.5V, XTAL2 = not connected; RESET=V

; Port 0=V

; all

other pins are disconnected. I

would be slightly higher if a crystal oscillator is used (approximately 1mA).

3. I

CC_CPU

(Idle Mode) is measured with:

XTAL1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+0.5V, V

= V

0.5V, XTAL2 = not connected; Port 0 = V

;

RESET=V

; all other pins are disconnected.

4. See Figure 62 for the PLD current calculation.
5. I/O current = 0 mA, all I/O pins are disconnected.

Logic 1-to-0 Transition Current
(Ports 1,2,3,4)

= 3.5V

(2.5V for Port 4[pin 2])

250

µA

STBY

SRAM (PSD) Standby Current
(V

STBY

input)

= 0V

0.5

µA

IDLE

SRAM (PSD) Idle Current
(V

STBY

input)

> V

STBY

0.1

µA

RST

Reset Pin Pull-up Current
(RESET)

= V

µA

XTAL Feedback Resistor
Current (XTAL1)

XTAL1 = V

XTAL2 = V

µA

Input Leakage Current

< V

µA

Output Leakage Current

0.45 < V

OUT

< V

µA

(1)

Power-down Mode

= 3.6V

LVD logic disabled

110

µA

LVD logic enabled

180

µA

CC_CPU

(2,3,5)

Active (12MHz)

= 3.6V

Idle (12MHz)

Active (24MHz)

= 3.6V

Idle (24MHz)

CC_PSD

(DC)

(5)

Operating
Supply Current

PLD Only

PLD_TURBO = Off,

f = 0MHz

(4)

µA/PT

(5)

PLD_TURBO = On,

f = 0MHz

200

400

µA/PT

Flash
memory

During Flash memory

WRITE/Erase Only

Read only, f = 0MHz

SRAM

f = 0MHz

CC_PSD

(AC)

(5)

PLD AC Base

Note 4

Flash memory AC Adder

1.5

2.0

mA/MHz

SRAM AC Adder

0.8

1.5

mA/MHz

Symbol

Parameter

Test Condition

(in addition to those

in Table 87, page 122)

Min.

Typ.

Max.

Unit

UPSD3212C, UPSD3212CV

128/152

Figure 65. External Program Memory READ Cycle

Table 91. External Program Memory AC Characteristics (with the 5V MCU Module)

Note: 1. Conditions (in addition to those in Table 86, V

= 4.5 to 5.5V): V

= 0V; C

for Port 0, ALE and PSEN output is 100pF; C

for

other outputs is 80pF

2. Interfacing the uPSD321X Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause

any damage to Port 0 drivers.

Symbol

Parameter

(1)

40MHz Oscillator

Variable Oscillator

1/t

CLCL

= 24 to 40MHz

Unit

Min

Max

Min

Max

LHLL

ALE pulse width

CLCL

AVLL

Address set up to ALE

CLCL

LLAX

Address hold after ALE

CLCL

LLIV

ALE Low to valid instruction in

CLCL

LLPL

ALE to PSEN

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

(2)

Input instruction float after PSEN

CLCL

PXAV

(2)

Address valid after PSEN

CLCL

AVIV

Address to valid instruction in

CLCL

AZPL

Address float to PSEN

tAVLL

tPLPH

tPXIZ

tAVIV

PSEN

PORT 2

PORT 0

AI06848

tLHLL

ALE

tLLPL

A0-A7

tLLAX

tAZPL

tLLIV
tPLIV

A0-A7

tPXAV

tPXIX

A8-A11

INSTR

A8-A11

129/152

UPSD3212C, UPSD3212CV

Table 92. External Program Memory AC Characteristics (with the 3V MCU Module)

Note: 1. Conditions (in addition to those in Table 87, V

= 3.0 to 3.6V): V

= 0V; C

for Port 0, ALE and PSEN output is 100pF, for 5V

devices, and 50pF for 3V devices; C

for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)

2. Interfacing the uPSD321X Devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause

any damage to Port 0 drivers.

Table 93. External Clock Drive (with the 5V MCU Module)

Note: 1. Conditions (in addition to those in Table 86, V

= 4.5 to 5.5V): V

= 0V; C

for Port 0, ALE and PSEN output is 100pF; C

for

other outputs is 80pF

Table 94. External Clock Drive (with the 3V MCU Module)

Note: 1. Conditions (in addition to those in Table 87, V

= 3.0 to 3.6V): V

= 0V; C

for Port 0, ALE and PSEN output is 100pF, for 5V

devices, and 50pF for 3V devices; C

for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)

Symbol

Parameter

(1)

24MHz Oscillator

Variable Oscillator

1/t

CLCL

= 8 to 24MHz

Unit

Min

Max

Min

Max

LHLL

ALE pulse width

CLCL

AVLL

Address set up to ALE

CLCL

LLAX

Address hold after ALE

CLCL

LLIV

ALE Low to valid instruction in

CLCL

LLPL

ALE to PSEN

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

(2)

Input instruction float after PSEN

CLCL

PXAV

(2)

Address valid after PSEN

CLCL

AVIV

Address to valid instruction in

148

CLCL

AZPL

Address float to PSEN

Symbol

Parameter

(1)

40MHz Oscillator

Variable Oscillator

1/t

CLCL

= 24 to 40MHz

Unit

Min

Max

Min

Max

RLRH

Oscillator period

41.7

WLWH

High time

CLCL

CLCX

LLAX2

Low time

CLCL

CLCX

RHDX

Rise time

RHDX

Fall time

Symbol

Parameter

(1)

24MHz Oscillator

Variable Oscillator

1/t

CLCL

= 8 to 24MHz

Unit

Min

Max

Min

Max

RLRH

Oscillator period

41.7

125

WLWH

High time

CLCL

CLCX

LLAX2

Low time

CLCL

CLCX

RHDX

Rise time

RHDX

Fall time

131/152

UPSD3212C, UPSD3212CV

Table 95. External Data Memory AC Characteristics (with the 5V MCU Module)

Note: 1. Conditions (in addition to those in Table 86, V

= 4.5 to 5.5V): V

= 0V; C

for Port 0, ALE and PSEN output is 100pF; C

for

other outputs is 80pF

Symbol

Parameter

(1)

40MHz Oscillator

Variable Oscillator

1/t

CLCL

= 24 to 40MHz

Unit

Min

Max

Min

Max

RLRH

RD pulse width

120

CLCL

WLWH

WR pulse width

120

CLCL

LLAX2

Address hold after ALE

CLCL

RHDX

RD to valid data in

CLCL

RHDX

Data hold after RD

RHDZ

Data float after RD

CLCL

LLDV

ALE to valid data in

150

CLCL

AVDV

Address to valid data in

150

CLCL

LLWL

ALE to WR or RD

CLCL

+ 15

AVWL

Address valid to WR or RD

CLCL

WHLH

WR or RD High to ALE High

CLCL

+ 15

QVWX

Data valid to WR transition

CLCL

QVWH

Data set up before WR

125

CLCL

WHQX

Data hold after WR

CLCL

RLAZ

Address float after RD

UPSD3212C, UPSD3212CV

132/152

Table 96. External Data Memory AC Characteristics (with the 3V MCU Module)

Note: 1. Conditions (in addition to those in Table 87, V

= 3.0 to 3.6V): V

= 0V; C

for Port 0, ALE and PSEN output is 100pF, for 5V

devices, and 50pF for 3V devices; C

for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)

Table 97. A/D Analog Specification

Symbol

Parameter

(1)

24MHz Oscillator

Variable Oscillator

1/t

CLCL

= 8 to 24MHz

Unit

Min

Max

Min

Max

RLRH

RD pulse width

180

CLCL

WLWH

WR pulse width

180

CLCL

LLAX2

Address hold after ALE

CLCL

RHDX

RD to valid data in

118

CLCL

RHDX

Data hold after RD

RHDZ

Data float after RD

CLCL

LLDV

ALE to valid data in

200

CLCL

133

AVDV

Address to valid data in

220

CLCL

155

LLWL

ALE to WR or RD

175

CLCL

+ 50

AVWL

Address valid to WR or RD

CLCL

WHLH

WR or RD High to ALE High

CLCL

+ 25

QVWX

Data valid to WR transition

CLCL

QVWH

Data set up before WR

170

CLCL

122

WHQX

Data hold after WR

CLCL

RLAZ

Address float after RD

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

REF

Analog Power Supply Input
Voltage Range

Analog Input Voltage Range

0.3

REF

+ 0.3

AVDD

Current Following between V

and V

200

µA

Overall Accuracy

±2

l.s.b.

NLE

Non-Linearity Error

±2

l.s.b.

DNLE

Differential Non-Linearity Error

±2

l.s.b.

ZOE

Zero-Offset Error

±2

l.s.b.

FSE

Full Scale Error

±2

l.s.b.

Gain Error

±2

l.s.b.

CONV

Conversion Time

at 8MHz clock

µs

133/152

UPSD3212C, UPSD3212CV

Figure 68. Input to Output Disable / Enable

Table 98. CPLD Combinatorial Timing (5V Devices)

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount

2. t

for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial

output (80-pin package only)

Table 99. CPLD Combinatorial Timing (3V Devices)

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount

2. t

for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial

output (80-pin package only)

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate

(1)

Unit

(2)

CPLD Input Pin/Feedback to
CPLD Combinatorial Output

+ 2

+ 10

CPLD Input to CPLD Output
Enable

+ 10

CPLD Input to CPLD Output
Disable

+ 10

ARP

CPLD Register Clear or Preset
Delay

+ 10

ARPW

CPLD Register Clear or Preset
Pulse Width

+ 10

ARD

CPLD Array Delay

Any

macrocell

+ 2

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate

(1)

Unit

(2)

CPLD Input Pin/Feedback to
CPLD Combinatorial Output

+ 4

+ 20

CPLD Input to CPLD Output
Enable

+ 20

CPLD Input to CPLD Output
Disable

+ 20

ARP

CPLD Register Clear or
Preset Delay

+ 20

ARPW

CPLD Register Clear or
Preset Pulse Width

+ 20

ARD

CPLD Array Delay

Any

macrocell

+ 4

tER

tEA

INPUT

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

UPSD3212C, UPSD3212CV

134/152

Figure 69. Synchronous Clock Mode Timing PLD

Table 100. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

2. CLKIN (PD1) t

CLCL

= t

+ t

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate

(1)

Unit

MAX

Maximum Frequency
External Feedback

1/(t

)

40.0

MHz

Maximum Frequency
Internal Feedback (f

CNT

)

1/(t

10)

66.6

MHz

Maximum Frequency
Pipelined Data

1/(t

)

83.3

MHz

Input Setup Time

+ 2

+ 10

Input Hold Time

Clock High Time

Clock Input

Clock Low Time

Clock Input

Clock to Output Delay

Clock Input

ARD

CPLD Array Delay

Any

macrocell

+ 2

MIN

Minimum Clock Period

(2)

tCH

tCL

tCO

CLKIN

INPUT

REGISTERED

OUTPUT

AI02860

UPSD3212C, UPSD3212CV

136/152

Figure 70. Asynchronous RESET / Preset

Figure 71. Asynchronous Clock Mode Timing (product term clock)

Table 102. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

Rate

Unit

MAXA

Maximum Frequency
External Feedback

1/(t

COA

)

38.4

MHz

Maximum Frequency
Internal Feedback (f

CNTA

)

1/(t

COA

10)

62.5

MHz

Maximum Frequency
Pipelined Data

1/(t

CHA

CLA

)

71.4

MHz

Input Setup Time

+ 2

+ 10

Input Hold Time

CHA

Clock Input High Time

+ 10

CLA

Clock Input Low Time

+ 10

COA

Clock to Output Delay

+ 10

ARDA

CPLD Array Delay

Any macrocell

+ 2

MINA

Minimum Clock Period

1/f

CNTA

tARP

REGISTER

OUTPUT

tARPW

RESET/PRESET

INPUT

AI02864

tCHA

tCLA

tCOA

tHA

tSA

CLOCK

INPUT

REGISTERED

OUTPUT

AI02859

UPSD3212C, UPSD3212CV

138/152

Figure 72. Input Macrocell Timing (product term clock)

Table 104. Input Macrocell Timing (5V Devices)

Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t

AVLX

and t

LXAX

Table 105. Input Macrocell Timing (3V Devices)

Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t

AVLX

and t

LXAX

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Unit

Input Setup Time

(Note

Input Hold Time

(Note

+ 10

INH

NIB Input High Time

(Note

INL

NIB Input Low Time

(Note

INO

NIB Input to Combinatorial Delay

(Note

+ 2

+ 10

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Unit

Input Setup Time

(Note

Input Hold Time

(Note

+ 20

INH

NIB Input High Time

(Note

INL

NIB Input Low Time

(Note

INO

NIB Input to Combinatorial Delay

(Note

+ 4

+ 20

INH

INL

INO

PT CLOCK

INPUT

OUTPUT

AI03101

139/152

UPSD3212C, UPSD3212CV

Table 106. Program, WRITE and Erase Times (5V Devices)

Note: 1. Programmed to all zero before erase.

2. The polling status, DQ7, is valid t

Q7VQV

time units before the data byte, DQ0-DQ7, is valid for reading.

Table 107. Program, WRITE and Erase Times (3V Devices)

Note: 1. Programmed to all zero before erase.

2. The polling status, DQ7, is valid t

Q7VQV

time units before the data byte, DQ0-DQ7, is valid for reading.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Flash Program

8.5

Flash Bulk Erase

(1)

(pre-programmed)

Flash Bulk Erase (not pre-programmed)

WHQV3

Sector Erase (pre-programmed)

WHQV2

Sector Erase (not pre-programmed)

2.2

WHQV1

Byte Program

150

µs

Program / Erase Cycles (per Sector)

100,000

cycles

WHWLO

Sector Erase Time-out

100

µs

Q7VQV

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

(2)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Flash Program

8.5

Flash Bulk Erase

(1)

(pre-programmed)

Flash Bulk Erase (not pre-programmed)

WHQV3

Sector Erase (pre-programmed)

WHQV2

Sector Erase (not pre-programmed)

2.2

WHQV1

Byte Program

150

µs

Program / Erase Cycles (per Sector)

100,000

cycles

WHWLO

Sector Erase Time-out

100

µs

Q7VQV

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

(2)

UPSD3212C, UPSD3212CV

140/152

Figure 73. Peripheral I/O READ Timing

Table 108. Port A Peripheral Data Mode READ Timing (5V Devices)

Note: 1. Any input used to select Port A Data Peripheral Mode.

2. Data is already stable on Port A.

Table 109. Port A Peripheral Data Mode READ Timing (3V Devices)

Note: 1. Any input used to select Port A Data Peripheral Mode.

2. Data is already stable on Port A.

Symbol

Parameter

Conditions

Min

Max

Turbo

Off

Unit

AVQVPA

Address Valid to Data
Valid

(Note

+ 10

SLQVPA

CSI Valid to Data Valid

+ 10

RLQVPA

RD to Data Valid

(Note

DVQVPA

Data In to Data Out Valid

RHQZPA

RD to Data High-Z

Symbol

Parameter

Conditions

Min

Max

Turbo

Off

Unit

AVQVPA

Address Valid to Data Valid

(Note

+ 20

SLQVPA

CSI Valid to Data Valid

+ 20

RLQVPA

RD to Data Valid

(Note

DVQVPA

Data In to Data Out Valid

RHQZPA

RD to Data High-Z

tRLQV (PA)

tDVQV (PA)

tRHQZ (PA)

tSLQV (PA)

tAVQV (PA)

ADDRESS

DATA VALID

ALE

A /D BUS

DATA ON PORT A

CSI

AI06610

UPSD3212C, UPSD3212CV

142/152

Figure 75. Reset (RESET) Timing

Table 112. Reset (RESET) Timing (5V Devices)

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

Table 113. Reset (RESET) Timing (3V Devices)

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

Table 114. V

STBYON

Definitions Timing (5V Devices)

Note: 1. V

STBYON

timing is measured at V

ramp rate of 2ms.

Table 115. V

STBYON

Timing (3V Devices)

Note: 1. V

STBYON

timing is measured at V

ramp rate of 2ms.

Symbol

Parameter

Conditions

Min

Max

Unit

NLNH

RESET Active Low Time

(1)

150

NLNHPO

Power-on Reset Active Low Time

OPR

RESET High to Operational Device

120

Symbol

Parameter

Conditions

Min

Max

Unit

NLNH

RESET Active Low Time

(1)

300

NLNHPO

Power-on Reset Active Low Time

OPR

RESET High to Operational Device

300

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

BVBH

STBY

Detection to V

STBYON

Output High

(Note

µs

BXBL

STBY

Off Detection to V

STBYON

Output

Low

(Note

µs

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

BVBH

STBY

Detection to V

STBYON

Output High

(Note

µs

BXBL

STBY

Off Detection to V

STBYON

Output

Low

(Note

µs

tNLNH-PO

tOPR

AI07437

RESET

tNLNH

tOPR

(min)

Power-On Reset

Warm Reset

143/152

UPSD3212C, UPSD3212CV

Figure 76. ISC Timing

Table 116. ISC Timing (5V Devices)

Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.

2. For Program or Erase PLD only.

Symbol

Parameter

Conditions

Min

Max

Unit

ISCCF

Clock (TCK, PC1) Frequency (except for PLD)

(Note

MHz

ISCCH

Clock (TCK, PC1) High Time (except for PLD)

(Note

ISCCL

Clock (TCK, PC1) Low Time (except for PLD)

(Note

ISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note

MHz

ISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note

240

ISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note

240

ISCPSU

ISC Port Set Up Time

ISCPH

ISC Port Hold Up Time

ISCPCO

ISC Port Clock to Output

ISCPZV

ISC Port High-Impedance to Valid Output

ISCPVZ

ISC Port Valid Output to High-Impedance

ISCCH

TCK

TDI/TMS

ISC OUTPUTS/TDO

ISCCL

ISCPH

ISCPSU

ISCPVZ

ISCPZV

ISCPCO

AI02865

UPSD3212C, UPSD3212CV

144/152

Table 117. ISC Timing (3V Devices)

Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.

2. For Program or Erase PLD only.

Figure 77. MCU Module AC Measurement I/O Waveform

Note: AC inputs during testing are driven at V

0.5V for a logic '1,' and 0.45V for a logic '0.'

Timing measurements are made at V

(min) for a logic '1,' and V

(max) for a logic '0'

Figure 78. PSD MODULE AC Float I/O Waveform

Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to

float when a 100mV change from the loaded V

or V

level occurs

and I

20mA

Symbol

Parameter

Conditions

Min

Max

Unit

ISCCF

Clock (TCK, PC1) Frequency (except for PLD)

(Note

MHz

ISCCH

Clock (TCK, PC1) High Time (except for PLD)

(Note

ISCCL

Clock (TCK, PC1) Low Time (except for PLD)

(Note

ISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note

MHz

ISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note

240

ISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note

240

ISCPSU

ISC Port Set Up Time

ISCPH

ISC Port Hold Up Time

ISCPCO

ISC Port Clock to Output

ISCPZV

ISC Port High-Impedance to Valid Output

ISCPVZ

ISC Port Valid Output to High-Impedance

AI06650

VCC 0.5V

0.45V

Test Points

0.2 VCC 0.1V

0.2 VCC + 0.9V

AI06651

Test Reference Points

VOL + 0.1V

VOH 0.1V

VLOAD 0.1V

VLOAD + 0.1V

0.2 VCC 0.1V

145/152

UPSD3212C, UPSD3212CV

Figure 79. External Clock Cycle

Figure 80. Recommended Oscillator Circuits

Note: C1, C2 = 30pF ± 10pF for crystals

For ceramic resonators, contact resonator manufacturer
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator
have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Figure 81. PSD MODULE AC Measurement I/O
Waveform

Figure 82. PSD MODULEAC Measurement
Load Circuit

Table 118. Capacitance

Note: Sampled only, not 100% tested.

1. Typical values are for T

= 25°C and nominal supply voltages.

3.0V

Test Point

1.5V

AI03103b

Device

Under Test

2.01 V

195

= 30 pF

(Including Scope and
Jig Capacitance)

AI03104b

Symbol

Parameter

Test Condition

Typ.

(1)

Max

Unit

Input Capacitance (for input pins)

= 0V

OUT

Output Capacitance (for input/
output pins)

OUT

= 0V

UPSD3212C, UPSD3212CV

152/152

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: uPSD3412CV-24U6T

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: uPSD3412CV-24U6T