Document Outline

• FEATURES SUMMARY
  • Figure 1. Packages
  • Table 1. Device Summary
• SUMMARY DESCRIPTION
  • Figure 2. Block Diagram
• PIN DESCRIPTIONS
  • Figure 3. TQFP52 Connections
  • Figure 4. TQFP80 Connections
  • Table 2. Pin Definitions
• HARDWARE DESCRIPTION
  • Table 3. Port Type and Voltage Source Combinations
  • Figure 5. Functional Modules
• MEMORY ORGANIZATION
  • Figure 6. uPSD34xx Memories
  • Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR)
  • External Memory (PSD Module: Program memory, Data memory)
• 8032 MCU CORE PERFORMANCE ENHANCEMENTS
  • Figure 7. Comparison of uPSD34xx with Standard 8032 Performance
  • Figure 8. Instruction Pre-Fetch Queue and Branch Cache
  • Pre-Fetch Queue (PFQ) and Branch Cache (BC)
  • PFQ Example, Multi-cycle Instructions
  • Aggregate Performance
    • Figure 9. PFQ Operation on Multi-cycle Instructions
    • Figure 10. uPSD34xx Multi-cycle Instructions Compared to Standard 8032
• MCU MODULE DISCRIPTION
• 8032 MCU REGISTERS
  • Figure 11. 8032 MCU Registers
  • Stack Pointer (SP)
  • Data Pointer (DPTR)
  • Program Counter (PC)
  • Accumulator (ACC)
  • B Register (B)
  • General Purpose Registers (R0 - R7)
  • Program Status Word (PSW)
    • Table 4. .Register Bank Select Addresses
    • Figure 12. Program Status Word (PSW) Register
• SPECIAL FUNCTION REGISTERS (SFR)
  • Table 5. SFR Memory Map with Direct Address and Reset Value
• 8032 ADDRESSING MODES
  • Register Addressing
  • Direct Addressing
  • Register Indirect Addressing
  • Immediate Addressing
  • External Direct Addressing
  • External Indirect Addressing
  • Indexed Addressing
  • Relative Addressing
  • Absolute Addressing
  • Long Addressing
  • Bit Addressing
• uPSD34xx INSTRUCTION SET SUMMARY
  • Table 6. Arithmetic Instruction Set
  • Table 7. Logical Instruction Set
  • Table 8. Data Transfer Instruction Set
  • Table 9. Boolean Variable Manipulation Instruction Set
  • Table 10. Program Branching Instruction Set
  • Table 11. Miscellaneous Instruction Set
  • Table 12. Notes on Instruction Set and Addressing Modes
• DUAL DATA POINTERS
  • Data Pointer Control Register, DPTC (85h)
    • Table 13. DPTC: Data Pointer Control Register (SFR 85h, reset value 00h)
  • Data Pointer Mode Register, DPTM (86h)
    • Table 14. DPTM: Data Pointer Mode Register (SFR 86h, reset value 00h)
    • Table 15. 8051 Assembly Code Example
• DEBUG UNIT
• INTERRUPT SYSTEM
  • Table 16. Interrupt Summary
  • Figure 13. Enabling and Polling Interrupts
  • Individual Interrupt Sources
    • Table 17. IE: Interrupt Enable Register (SFR A8h, reset value 00h)
    • Table 18. IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h)
    • Table 19. IP: Interrupt Priority Register (SFR B8h, reset value 00h)
    • Table 20. IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h)
• MCU CLOCK GENERATION
  • MCU_CLK
  • PERIPH_CLK
    • Table 21. PLLM and PLLD Values for Different fOSC Frequencies
    • Figure 14. Clock Generation Logic
    • Table 22. CCON0: Clock Control Register (SFR F9h, reset value 50h)
    • Table 23. CCON1 PLL Control Register (SFR FAh, reset value 00h)
• POWER SAVING MODES
  • Idle Mode
  • Power-down Mode
  • Reduced Frequency Mode
    • Table 24. MCU Module Port and Peripheral Status during Reduced Power Modes
    • Table 25. State of 8032 MCU Bus Signals during Power-down and Idle Modes
    • Table 26. PCON: Power Control Register (SFR 87h, reset value 00h)
• OSCILLATOR AND EXTERNAL COMPONENTS
  • Figure 15. Oscillator and Clock Connections
• I/O PORTS of MCU MODULE
  • MCU Port Operating Modes
    • Figure 16. MCU Module Port Pin Function Routing
    • Figure 17. MCU I/O Cell Block Diagram for Port 1
    • Figure 18. MCU I/O Cell Block Diagram for Port 3
    • Figure 19. MCU I/O Cell Block Diagram for Port 4
    • Table 27. P1: I/O Port 1 Register (SFR 90h, reset value FFh)
    • Table 28. P3: I/O Port 3 Register (SFR B0h, reset value FFh)
    • Table 29. P4: I/O Port 4 Register (SFR C0h, reset value FFh)
    • Table 30. P3SFS: Port 3 Special Function Select Register (SFR 91h, reset value 00h)
    • Table 31. P1SFS0: Port 1 Special Function Select 0 Register (SFR 8Eh, reset value 00h)
    • Table 32. P1SFS1: Port 1 Special Function Select 1 Register (SFR 8Fh, reset value 00h)
    • Table 33. P1SFS0 and P1SFS1 Details
    • Table 34. P4SFS0: Port 4 Special Function Select 0 Register (SFR 92h, reset value 00h)
    • Table 35. P4SFS1: Port 4 Special Function Select 1 Register (SFR 93h, reset value 00h)
    • Table 36. P4SFS0 and P4SFS1 Details
• MCU BUS INTERFACE
  • PSEN Bus Cycles
  • READ or WRITE Bus Cycles
  • Connecting External Devices to the MCU Bus
    • Figure 20. Connecting External Devices using Ports A and B for Address AD[15:0]
    • Figure 21. Connecting External Devices using Port A and an External Latch for Address AD[15:0]
  • Programmable Bus Timing
  • Controlling the PFQ and BC
    • Figure 22. A RD or PSEN Bus Cycle Set to 5 MCU_CLK
    • Table 37. BUSCON: Bus Control Register (SFR 9Dh, reset value EBh)
    • Table 38. Number of MCU_CLK Periods Required to Optimize Bus Transfer Rate
• SUPERVISORY FUNCTIONS
  • External Reset Input Pin, RESET_IN
    • Figure 23. Supervisor Reset Generation
  • Low VCC Voltage Detect, LVD
  • Power-up Reset
  • JTAG Debug Reset
  • Watchdog Timer, WDT
    • Figure 24. Watchdog Counter
    • Table 39. WDKEY: Watchdog Timer Key Register (SFR AEh, reset value 55h)
    • Table 40. WDRST: Watchdog Timer Reset Counter Register (SFR A6h, reset value 00h)
• STANDARD 8032 TIMER/COUNTERS
  • Standard Timer SFRs
  • Clock Sources
    • Table 41. TCON: Timer Control Register (SFR 88h, reset value 00h)
  • SFR, TCON
  • SFR, TMOD
  • Timer 0 and Timer 1 Operating Modes
    • Table 42. TMOD: Timer Mode Register (SFR 89h, reset value 00h)
    • Figure 25. Timer/Counter Mode 0: 13-bit Counter
    • Figure 26. Timer/Counter Mode 2: 8-bit Auto-reload
    • Figure 27. Timer/Counter Mode 3: Two 8-bit Counters
  • Timer 2
    • Table 43. T2CON: Timer 2 Control Register (SFR C8h, reset value 00h)
    • Table 44. Timer/Counter 2 Operating Modes
    • Table 45. Commonly Used Baud Rates Generated from Timer2 (T2CON = 34h)
    • Figure 28. Timer 2 in Capture Mode
    • Figure 29. Timer 2 in Auto-Reload Mode
    • Figure 30. Timer 2 in Baud Rate Generator Mode
• SERIAL UART INTERFACES
  • UART Operation Modes
    • Table 46. UART Operating Modes
  • Serial Port Control Registers
    • Table 47. SCON0: Serial Port UART0 Control Register (SFR 98h, reset value 00h)
    • Table 48. SCON1: Serial Port UART1 Control Register (SFR D8h, reset value 00h)
  • UART Baud Rates
    • Table 49. Commonly Used Baud Rates Generated from Timer 1
  • More About UART Mode 0
    • Figure 31. UART Mode 0, Block Diagram
    • Figure 32. UART Mode 0, Timing Diagram
  • More About UART Mode 1
    • Figure 33. UART Mode 1, Block Diagram
    • Figure 34. UART Mode 1, Timing Diagram
  • More About UART Modes 2 and 3
    • Figure 35. UART Mode 2, Block Diagram
    • Figure 36. UART Mode 2, Timing Diagram
    • Figure 37. UART Mode 3, Block Diagram
    • Figure 38. UART Mode 3, Timing Diagram
• IrDA INTERFACE
  • Figure 39. IrDA Interface
  • Figure 40. Pulse Shaping by the IrDA Interface
  • Baud Rate Selection
    • Table 50. IRDACON Register Bit Definition (SFR CEh, Reset Value 0Fh)
    • Table 51. Baud Rate Selection Register (SFR xxh, reset value xxh)
    • Table 52. Baud Rate of UART#2 for IrDA Interface
  • Pulse Width Selection
    • Table 53. Recommended CDIV[4:0] Values to Generate SIRClk (default CDIV[4:0] = 0Fh, 15 decimal)
• I2C INTERFACE
  • I2C Interface Main Features
    • Figure 41. Typical I2C Bus Configuration
  • Communication Flow
    • Figure 42. Data Transfer on an I2C Bus
  • Operating Modes
  • Bus Arbitration
  • Clock Synchronization
  • General Call Address
  • Serial I/O Engine (SIOE)
    • Figure 43. I2C Interface SIOE Block Diagram
  • I2C Interface Control Register (S1CON)
    • Table 54. Serial Control Register S1CON (SFR DCh, Reset Value 00h)
    • Table 55. Selection of the SCL Frequency in Master Mode based on fOSC Examples
  • I2C Interface Status Register (S1STA)
    • Table 56. S1STA: I2C Interface Status register (SFR DDh, reset value 00h)
  • I2C Data Shift Register (S1DAT)
    • Table 57. S1DAT: I2C Data Shift register (SFR DEh, reset value 00h)
  • I2C Address Register (S1ADR)
    • Table 58. S1ADR: I2C Address register (SFR DFh, reset value 00h)
  • I2C START Sample Setting (S1SETUP)
    • Table 59. S1SETUP: I2C START Condition Sample Setup register (SFR DBh, reset value 00h)
    • Table 60. Number of I2C Bus Samples Taken after 1-to-0 Transition on SDA (START Condition)
    • Table 61. Start Condition Hold Time
    • Table 62. S1SETUP Examples for Various I2C Bus Speeds and Oscillator Frequencies
  • I2C Operating Sequences
• SPI (SYNCHRONOUS PERIPHERAL INTERFACE)
  • Figure 44. SPI Device Connection Examples
  • SPI Bus Features and Communication Flow
  • Full-Duplex Operation
  • Bus-Level Activity
    • Figure 45. SPI Full-Duplex Data Exchange
    • Figure 46. SPI Receive Operation Example
    • Figure 47. SPI Transmit Operation Example
  • SPI SFR Registers
    • Figure 48. SPI Interface, Master Mode Only
  • SPI Configuration
  • Dynamic Control
    • Table 63. SPICON0: Control Register 0 (SFR D6h, Reset Value 00h)
    • Table 64. SPICON1: SPI Interface Control Register 1 (SFR D7h, Reset Value 00h)
    • Table 65. SPICLKD: SPI Prescaler (Clock Divider) Register (SFR D2h, Reset Value 04h)
    • Table 66. SPISTAT: SPI Interface Status Register (SFR D3h, Reset Value 02h)
• USB INTERFACE
  • Figure 49. USB Module Block Diagram
  • Basic USB Concepts
    • Table 67. Types of Packet IDs
    • Figure 50. USB Packets in a USB Transfer Example
  • Types of Transfers
    • Figure 51. IN and OUT Bulk Transfers
    • Figure 52. Interrupt Transfer
    • Figure 53. Control Transfer
  • Endpoint FIFOs
    • Table 68. uPSD34xx Supported Endpoints
    • Figure 54. FIFOs with no Pairing
    • Figure 55. FIFO Pairing Example (1/2 IN Paired and 3/4 OUT Paired)
  • USB Registers
    • Table 69. uPSD34xx USB SFR Register Map
    • Table 70. USB Device Address Register (UADDR 0E2h, Reset Value 00h)
    • Table 71. Pairing Control Register (UPAIR 0E3h, Reset Value 00h)
    • Table 72. USB Global Interrupt Enable Register (UIE0 0E4h, Reset Value 00h)
    • Table 73. USB IN FIFO Interrupt Enable Register (UIE1 0E5h, Reset Value 00h)
    • Table 74. USB OUT FIFO Interrupt Enable Register (UIE2 0E6h, Reset Value 00h)
    • Table 75. USB IN FIFO NAK Interrupt Enable Register (UIE3 0E7h, Reset Value 00h)
    • Table 76. USB Global Interrupt Flag Register (UIF0 0E8h, Reset Value 00h)
    • Table 77. USB IN FIFO Interrupt Flag (UIF1 0E9h, Reset Value 00h)
    • Table 78. USB OUT FIFO Interrupt Flag (UIF2 0EAh, Reset Value 00h)
    • Table 79. USB IN FIFO NAK Interrupt Flag (UIF3 0EBh, Reset Value 00h)
    • Table 80. USB Control Register (UCTL 0ECh, Reset Value 00h)
    • Table 81. USB Endpoint0 Status (USTA 0EDh, Reset Value 00h)
    • Table 82. USB Endpoint Select Register (USEL 0EFh, Reset Value 00h)
    • Table 83. USB Endpoint Control Register (UCON 0F1h, Reset Value 00h)
    • Table 84. USB FIFO Valid Size (USIZE 0F2h, Reset Value 00h)
    • Table 85. USB FIFO Base Address High Register (UBASEH 0F3h, Reset Value 00h)
    • Table 86. USB FIFO Base Address Low Register (UBASEL 0F4h, Reset Value 00h)
    • Table 87. USB Setup Command Index Register (USCI 0F5h, Reset Value 00h)
    • Table 88. USB Setup Command Value Register (USCV 0F6h, Reset Value 00h)
  • Typical Connection to USB
    • Figure 56. Typical Self Powered Example
• ANALOG-TO-DIGITAL CONVERTOR (ADC)
  • Port 1 ADC Channel Selects
    • Figure 57. 10-Bit ADC
    • Table 89. ACON Register (SFR 97h, Reset Value 00h)
    • Table 90. ADCPS Register Details (SFR 94h, Reset Value 00h)
    • Table 91. ADAT0 Register (SFR 95h, Reset Value 00h)
    • Table 92. ADAT1 Register (SFR 96h, Reset Value 00h)
• PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM
  • PCA Block
    • Figure 58. PCA0 Block Diagram
    • Table 93. PCA0 and PCA1 Registers
  • PCA Clock Selection
    • Table 94. CCON2 Register Bit Definition (SFR 0FBh, Reset Value 10h)
    • Table 95. CCON3 Register Bit Definition (SFR 0FCh, Reset Value 10h)
  • Operation of TCM Modes
  • Capture Mode
  • Timer Mode
  • Toggle Mode
  • PWM Mode - (X8), Fixed Frequency
    • Figure 59. Timer Mode
    • Figure 60. PWM Mode - (X8), Fixed Frequency
  • PWM Mode - (X8), Programmable Frequency
    • Figure 61. PWM Mode - (X8) Programmable Frequency
  • PWM Mode - Fixed Frequency, 16-bit
  • PWM Mode - Fixed Frequency, 10-bit
  • Writing to Capture/Compare Registers
  • Control Register Bit Definition
    • Table 96. PCA0 Control Register PCACON0 (SFR 0A4h, Reset Value 00h)
    • Table 97. PCA1 Control Register PCACON1 (SFR 0BCh, Reset Value 00h)
    • Table 98. PCA Status Register PCASTA (SFR 0A5h, Reset Value 00h)
  • TCM Interrupts
    • Table 99. TCMMODE0 - TCMMODE5 (6 Registers, Reset Value 00h)
    • Table 100. TCMMODE Register Configurations
• PSD MODULE
  • Figure 62. PSD Module Block Diagram
  • PSD Module Functional Description
    • Table 101. uPSD34xx Memory Configuration
    • Figure 63. Memory Page Register
    • Table 102. General I/O pins on PSD Module
  • Memory Mapping
    • Figure 64. Typical System Memory Map
    • Table 103. HDL Statement Example Generated from PSDsoft Express for Memory Map
    • Figure 65. PSDsoft Express Memory Mapping
    • Figure 66. Mapping: Split Second Flash in Half
    • Figure 67. Mapping: All Flash in Code Space
    • Figure 68. Mapping: Small Code / Big Data
    • Figure 69. PSD Module Memory Priority
    • Table 104. VM Register (address = csiop + offset E2h)
    • Figure 70. VM Register Control of Memories
    • Figure 71. VM Register Example Corresponding to Memory Map Example
  • PSD Module Data Bus Width
    • Table 105. Data Width in Different Bus Cycles
  • Runtime Control Register Definitions (csiop)
    • Table 106. CSIOP Registers and their Offsets (in hexadecimal)
  • PSD Module Detailed Operation
    • Table 107. Flash Memory Instruction Sequences(1,2)
    • Table 108. Flash Memory Status Bit Definition
    • Figure 72. Data Polling Flowchart
    • Figure 73. Data Toggle Flowchart
    • Table 109. Main Flash Memory Protection Register Definition (address = csiop + offset C0h)
    • Table 110. Secondary Flash Memory Protection/Security Register Definition (csiop + offset C2h)
    • Table 111. DPLD and GPLD Inputs
    • Figure 74. DPLD and GPLD
    • Figure 75. DPLD Logic Array
    • Figure 76. GPLD: One OMC, One IMC, and One I/O Port (typical pin, Port A, B, or C)
    • Figure 77. Detail of a Single OMC
    • Figure 78. OMC Allocator
    • Table 112. OMC Port and Data Bit Assignments
    • Table 113. Output Macrocell MCELLAB (address = csiop + offset 20h)
    • Table 114. Output Macrocell MCELLBC (address = csiop + offset 21h)
    • Table 115. Output Macrocell MCELLAB Mask Register (address = csiop + offset 22h)
    • Table 116. Output Macrocell MCELLBC Mask Register (address = csiop + offset 23h)
    • Figure 79. Detail of a Single IMC
    • Table 117. Input Macrocell Port A(1) (address = csiop + offset 0Ah)
    • Table 118. Input Macrocell Port B (address = csiop + offset 0Bh)
    • Table 119. Input Macrocell Port C (address = csiop + offset 18h)
    • Figure 80. Detail of a Single I/O Port (typical of Ports A, B, C)
    • Table 120. Port Operating Modes
    • Table 121. Port Configuration Setting Requirements
    • Table 122. MCU I/O Mode Port A Data In Register(1) (address = csiop + offset 00h)
    • Table 123. MCU I/O Mode Port B Data In Register (address = csiop + offset 01h)
    • Table 124. MCU I/O Mode Port C Data In Register (address = csiop + offset 10h)
    • Table 125. MCU I/O Mode Port D Data In Register (address = csiop + offset 11h)
    • Table 126. MCU I/O Mode Port A Data Out Register(1) (address = csiop + offset 04h)
    • Table 127. MCU I/O Mode Port B Data Out Register (address = csiop + offset 05h)
    • Table 128. MCU I/O Mode Port C Data Out Register (address = csiop + offset 12h)
    • Table 129. MCU I/O Mode Port D Data Out Register (address = csiop + offset 13h)
    • Table 130. MCU I/O Mode Port A Direction Register(1) (address = csiop + offset 06h)
    • Table 131. MCU I/O Mode Port B Direction In Register (address = csiop + offset 07h)
    • Table 132. MCU I/O Mode Port C Direction Register (address = csiop + offset 14h)
    • Table 133. MCU I/O Mode Port D Direction Register (address = csiop + offset 15h)
    • Figure 81. Simple PLD Logic Example
    • Figure 82. Pin Declarations in PSDsoft Express for Simple PLD Example
    • Figure 83. Using the Design Assistant in PSDsoft Express for Simple PLD Example
    • Table 134. Latched Address Output, Port A Control Register(1) (address = csiop + offset 02h)
    • Table 135. Latched Address Output, Port B Control Register (address = csiop + offset 03h)
    • Figure 84. Peripheral I/O Mode
    • Table 136. Port A Pin Drive Select Register(1) (address = csiop + offset 08h)
    • Table 137. Port B Pin Drive Select Register (address = csiop + offset 09h)
    • Table 138. Port C Pin Drive Select Register (address = csiop + offset 16h)
    • Table 139. Port D Pin Drive Select Register (address = csiop + offset 17h)
    • Table 140. Port A Enable Out Register(1) (address = csiop + offset 0Ch)
    • Table 141. Port B Enable Out Register (address = csiop + offset 0Dh)
    • Table 142. Port C Enable Out Register (address = csiop + offset 1Ah)
    • Table 143. Port D Enable Out Register (address = csiop + offset 1Bh)
    • Figure 85. Port A Structure
    • Figure 86. Port B Structure
    • Figure 87. Port C Structure
    • Figure 88. Port D Structure
    • Table 144. Power Management Mode Register PMMR0 (address = csiop + offset B0h)
    • Table 145. Power Management Mode Register PMMR2 (address = csiop + offset B4h)
    • Table 146. Power Management Mode Register PMMR3 (address = csiop + offset C7h)
    • Table 147. Forced Power-Down Example
    • Figure 89. Automatic Power Down (APD) Unit
    • Figure 90. Power-Down Mode Flow Chart
  • PSD Module Reset Conditions
    • Table 148. Function Status During Power-Up Reset, Warm Reset, Power-down Mode
    • Figure 91. JTAG Chain in uPSD34xx Package
    • Figure 92. Recommended 4-pin JTAG Connections
    • Figure 93. Recommended 6-pin JTAG Connections
    • Figure 94. Recommended JTAG Connector
    • Figure 95. Example of Chaining uPSD34xx Devices
• AC/DC PARAMETERS
  • Figure 96. PLD ICC /Frequency Consumption (5V range)
  • Figure 97. PLD ICC /Frequency Consumption (3V range)
  • Table 149. PSD Module Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
• MAXIMUM RATING
  • Table 150. Absolute Maximum Ratings
• DC AND AC PARAMETERS
  • Table 151. Operating Conditions (5V Devices)
  • Table 152. Operating Conditions (3.3V Devices)
  • Table 153. AC Signal Letters for Timing
  • Table 154. AC Signal Behavior Symbols for Timing
  • Figure 98. Switching Waveforms � Key
  • Table 155. Major Parameters
  • Table 156. Preliminary MCU Module DC Characteristics
  • Table 157. PSD Module DC Characteristics (with 5V VDD)
  • Table 158. PSD Module DC Characteristics (with 3.3V VDD)
  • Figure 99. External READ Cycle (80-pin Device Only)
  • Table 159. External READ Cycle AC Characteristics (3V or 5V Device)
  • Table 160. n, m, and x, y Values
  • Figure 100. External WRITE Cycle (80-pin Device Only)
  • Table 161. External WRITE Cycle AC Characteristics (3V or 5V Device)
  • Table 162. External Clock Drive
  • Table 163. A/D Analog Specification
  • Table 164. USB Transceiver Specification
  • Figure 101. Input to Output Disable / Enable
  • Table 165. CPLD Combinatorial Timing (5V PSD Module)
  • Table 166. CPLD Combinatorial Timing (3V PSD Module)
  • Figure 102. Synchronous Clock Mode Timing � PLD
  • Table 167. CPLD Macrocell Synchronous Clock Mode Timing (5V PSD Module)
  • Table 168. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
  • Figure 103. Asynchronous RESET / Preset
  • Figure 104. Asynchronous Clock Mode Timing (Product Term Clock)
  • Table 169. CPLD Macrocell Asynchronous Clock Mode Timing (5V PSD Module)
  • Table 170. CPLD Macrocell Asynchronous Clock Mode Timing (3V PSD Module)
  • Figure 105. Input Macrocell Timing (Product Term Clock)
  • Table 171. Input Macrocell Timing (5V PSD Module)
  • Table 172. Input Macrocell Timing (3V PSD Module)
  • Table 173. Program, WRITE and Erase Times (5V, 3V PSD Modules)
  • Figure 106. Peripheral I/O READ Timing
  • Table 174. Port A Peripheral Data Mode READ Timing (5V PSD Module)
  • Table 175. Port A Peripheral Data Mode READ Timing (3V PSD Module)
  • Figure 107. Peripheral I/O WRITE Timing
  • Table 176. Port A Peripheral Data Mode WRITE Timing (5V PSD Module)
  • Table 177. Port A Peripheral Data Mode WRITE Timing (3V PSD Module)
  • Table 178. Supervisor Reset and LVD
  • Table 179. VSTBYON Definitions Timing (5V, 3V PSD Modules)
  • Figure 108. ISC Timing
  • Table 180. ISC Timing (5V PSD Module)
  • Table 181. ISC Timing (3V PSD Module)
  • Figure 109. MCU Module AC Measurement I/O Waveform
  • Figure 110. PSD Module AC Float I/O Waveform
  • Figure 111. External Clock Cycle
  • Figure 112. PSD Module AC Measurement I/O Waveform
  • Figure 113. PSD Module AC Measurement Load Circuit
  • Table 182. I/O Pin Capacitance
• PACKAGE MECHANICAL INFORMATION
  • Figure 114. TQFP52 � 52-lead Plastic Thin, Quad, Flat Package Outline
  • Table 183. TQFP52 � 52-lead Plastic Thin, Quad, Flat Package Mechanical Data
  • Figure 115. TQFP80 � 80-lead Plastic Thin, Quad, Flat Package Outline
  • Table 184. TQFP80 � 80-lead Plastic Thin, Quad, Flat Package Mechanical Data
• PART NUMBERING
  • Table 185. Ordering Information Scheme
• REVISION HISTORY
  • Table 186. Document Revision History