1/11
USBLC6-2
VERY LOW CAPACITANCE
ESD PROTECTION
REV. 2
SOT23-6L
USBLC6-2SC6
SOT-666
USBLC6-2P6
June 2005
MAIN APPLICATIONS
USB2.0 ports at 480Mbps (high speed) and
USB OTG ports
Backwards Compatible with USB1.1 Low and
full speed
Ethernet port: 10/100Mb/s
SIM card protection
Video line protection
Portable and mobile electronics
DESCRIPTION
The USBLC6-2P6 and USBLC6-2SC6 are two
monolithic Application Specific Devices dedicated
to ESD protection of high speed interfaces such as
USB2.0, Ethernet links and Video lines.
The very low line capacitance secures a high level
of signal integrity without compromising in
protection sensitive chips against the most
stringent characterized ESD strikes.
FEATURES
2 data lines protection
Protects V
BUS
Very low capacitance: 3.5pF max
Very low leakage current: 1A max
SOT-666 and SOT23-6L packages
RoHS compliant
BENEFITS
Very low capacitance between lines to GND for
optimized data integrity and speed
Ultra low PCB space consuming: 2.9mm max
for SOT-666 package and 9mm max for
SOT23-6L package
Enhanced ESD protection: IEC61000-4-2 level
4 compliance guaranteed at device level,
hence greater immunity at system level
ESD protection of V
BUS
. Allows ESD current
flowing to Ground when ESD event occurs on
data line
High reliability offered by monolithic integration
Very low leakage current for longer operation
of battery powered devices
Fast response time
Consistant D+/D- signal balance
- Best capacitance matching tolerance I/O to
GND of 0.04pF
- Compliance with USB2.0 requirement (<1pF)
Table 1: Order Codes
Part Number
Marking
USBLC6-2SC6
UL26
USBLC6-2P6
F
Figure 1: Functional Diagram
1
1
6
2
5
3
4
I/O1
I/O1
GND
V
BUS
I/O2
I/O2
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2 level 4:
15kV (air discharge)
8kV
(contact discharge)
ASD
(Application Specific Devices)
USBLC6-2
2/11
Table 2: Absolute Ratings
Table 3: Electrical Characteristics (T
amb
= 25C)
Symbol
Parameter
Value
Unit
V
PP
Peak pulse voltage
At device level:
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
MIL STD883C-Method 3015-6
15
15
25
kV
T
stg
Storage temperature range
-55 to +150
C
T
j
Maximum junction temperature
125
C
T
L
Lead solder temperature (10 seconds duration)
260
C
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
V
RM
Reverse stand-off voltage
5
V
I
RM
Leakage current
V
RM
= 5V
1
A
V
BR
Breakdown voltage between V
BUS
and GND
I
F
= 1mA
6
V
V
F
Forward voltage
I
F
= 10mA
1.1
V
V
CL
Clamping voltage
I
PP
= 1A, t
p
= 8/20s
Any I/O pin to GND
12
V
I
PP
= 5A, t
p
= 8/20s
Any I/O pin to GND
17
V
C
i/o-GND
Capacitance between I/O and GND
V = 0V F = 1MHz
any I/O pin to GND
2.5
3.5
pF
C
i/o-GND
0.04
C
i/o-i/o
Capacitance between I/O
V = 0V F = 1MHz
between I/O, GND
not connected
1.2
1.7
pF
C
i/o-i/o
0.04
USBLC6-2
3/11
Figure 2: Capacitance versus line voltage
(typical values)
Figure 3: Line capacitance versus frequency
(typical values)
Figure 4: Relative variation of leakage current
versus junction temperature (typical values)
Figure 5: Frequency response
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
C(pF)
F=1MHz
V
=30mV
T =25C
OSC
RMS
j
C =I/O-I/O
j
C =I/O-GND
O
Data line voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
1
10
100
1000
C(pF)
V
=30mV
T =25C
OSC
RMS
j
V
=0V to 3.3V
LINE
F(MHz)
1
10
100
25
50
75
100
125
T (C)
j
V
=5V
BUS
I
[T
RM
j
] / I
[T
RM
j
=25C]
100.0k
1.0M
10.0M
100.0M
1.0G
-20.00
-15.00
-10.00
-5.00
0.00
S21(dB)
F(Hz)
USBLC6-2
4/11
TECHNICAL INFORMATION
1. SURGE PROTECTION
The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage V
CL
can be calculated as follow :
V
CL
+ = V
BUS
+ V
F
for positive surge
V
CL
- = - V
F
for negative surge
with: V
F
= V
T
+ R
d
.I
p
(V
F
forward drop voltage) / (V
T
threshold voltage)
We assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 0.5
and V
T
= 1.2V.
For an IEC61000-4-2 surge Level 4 (Contact Discharge: V
g
=8kV, R
g
=330
), V
BUS
= +5V, and if in first
approximation, we assume that : I
p
= V
g
/ R
g
= 24A.
So, we find:
V
CL
+ = +17V
V
CL
- = -12V
Note: the calculations do not take into account phenomena due to parasitic inductances.
2. SURGE PROTECTION APPLICATION EXAMPLE
If we consider that the connections from the pin V
BUS
to V
CC
and from GND to PCB GND are done by
two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks
are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the
voltage V
CL
has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping
voltage will be :
V
CL
+ = +17 + 144 = 161V
V
CL
- = -12 - 144 = -156V
We can reduce as much as possible these phenomena with simple layout optimization.
It's the reason why some recommendations have to be followed (see paragraph "How to ensure a good
ESD protection").
Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout
Lw
VI/O
ESD
SURGE
GND
I/O
+V
CC
V
BUS
V
F
Lw di
dt
Lw di
dt
V
+ =
CL
V
+V +Lw
BUS
F
di
dt
surge >0
di
dt
surge <0
V
- =
CL
-V -Lw
F
t
tr=1ns
V
V
CC
F
+
Lw
di
dt
V
CL+
POSITIVE
SURGE
183V
-Lw
di
dt
t
tr=1ns
-
V
F
V
CL-
NEGATIVE
SURGE
-178V
USBLC6-2
5/11
3. HOW TO ENSURE A GOOD ESD PROTECTION
While the USBLC6-2 provides a high immunity to ESD surge, an efficient protection depends on the layout
of the board. In the same way, with the rail to rail topology, the track from the V
BUS
pin to the power supply
+V
CC
and from the GND pin to GND must be as short as possible to avoid overvoltages due to parasitic
phenomena (see figure 6).
It's often harder to connect the power supply near to the USBLC6-2 unlike the ground thanks to the ground
plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can't be short enough, we
recommend to put close to the USBLC6-2, between V
BUS
and ground, a capacitance of 100nF to prevent
from these kinds of overvoltage disturbances (see figure 7).
The add of this capacitance will allow a better protection by providing during surge a constant voltage.
The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations
described above.
IMPORTANT:
A main precaution to take is to put the protection device closer to the disturbance source (generally the
connector).
Note: The measurements have been done with the USBLC6-2 in open circuit.
Figure 7: ESD behavior: optimized layout and
add of a capacitance of 100nF
Figure 8: ESD behavior: measurements
conditions (with coupling capacitance)
Figure 9: Remaining voltage after the
USBLC6-2 during positive ESD surge
Figure 10: Remaining voltage after the
USBLC6-2 during negative ESD surge
REF1=GND
VI/O
ESD
SURGE
I/O
REF2=+
V
CC
C=100nF
Lw
V
+
V
CL
CC
F
V
+
=
surge >0
surge <0
V
V
CL
F
-
- =
t
V
+
CL
POSITIVE
SURGE
t
V
-
CL
NEGATIVE
SURGE
+5V
C=100nF
TEST BOARD
ESD
SURGE
USBLC6-2SC6
Vin
Vout
Vin
Vout
USBLC6-2
6/11
4. CROSSTALK BEHAVIOR
4.1. Crosstalk phenomena
Figure 11: Crosstalk phenomena
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (
12
or
21
)
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load R
L2
is
2
V
G2
, in fact the real voltage at this point has got an extra value
21
V
G1
.
This part of the V
G1
signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.
This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage
signal or high load impedance (few k
).
Figure 12: Analog crosstalk measurements
Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog
signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).
Line 1
Line 2
V
G1
V
G2
R
G1
R
G2
DRIVERS
R
L1
R
L2
RECEIVERS
+
1
12
V
G1
V
G2
+
2
21
V
G2
V
G1
SPECTRUM ANALYSER
Vout
50
TRACKING GENERATOR
Vg
Vin
50
TEST BOARD
V
BUS
C=100nF
USBLC6-2SC6
Figure 13: Analog crosstalk results
As the USBLC6-2 is designed to protect high
speed data lines, it must ensure a good transmis-
sion of operating signals. The frequency response
(figure 5) gives attenuation information and shows
that the USBLC6-2 is well suitable for data line
transmission up to 480 Mbit/s while it works as a
filter for undesirable signals like GSM (900MHz)
frequencies, for instance.
100.0k
1.0M
10.0M
100.0M
1.0G
-120.00
-90.00
-60.00
-30.00
0.00
Analog Crosstalk
APLAC 7.91 User: ST Microelectronics Jan 12 2005
dB
f/Hz
Attenuation
USBLC6-2
7/11
5. APPLICATION EXAMPLES
Figure 14: USB2.0 port application diagram using USBLC6-2
Figure 15: T1/E1/Ethernet protection
HUB-
DOWNSTREAM
TRANSCEIVER
+ 5V
R
S
R
S
R
S
R
S
R
PD
R
PD
R
PD
R
PD
Protecting
Bus Switch
DEVICE-
UPSTREAM
TRANSCEIVER
+ 3.3V
SW
1
R
PU
V
BUS
D+
D-
GND
V
BUS
V
BUS
V
BUS
R
X LS/FS
+
R
X LS/FS
+
R
X LS/FS
+
R
X LS/FS
+
R
X HS
+
R
X HS
+
R
X HS
+
R
X HS
+
T
X HS
+
T
X HS
+
T
X HS
+
T
X HS
+
T
X LS/FS
+
T
X LS/FS
+
T
X LS/FS
+
T
X LS/FS
+
R
S
R
S
USB
connector
T
X LS/FS -
T
X LS/FS -
T
X LS/FS -
T
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X HS -
R
X HS -
R
X HS -
R
X HS -
T
X HS -
T
X HS -
T
X HS -
T
X HS -
GND
GND
GND
GND
SW
2
DEVICE-
UPSTREAM
TRANSCEIVER
USBLC6-4SC6
USBLC6-2P6
USBLC6-2SC6
+ 3.3V
SW
1
R
PU
V
BUS
D+
D-
GND
R
S
R
S
USB
connector
SW
2
Open
Closed then open
High Speed HS
Open
Closed
Full Speed FS
Closed
Open
Low Speed LS
SW
2
SW
1
Mode
DATA
TRANSCEIVER
SMP75-8
SMP75-8
Tx
Rx
+V
CC
+V
CC
100nF
100nF
USBLC6-2SC6
USBLC6-2SC6
USBLC6-2
8/11
6. PSPICE MODEL
Figure 16 shows the PSPICE model of one USBLC6-2 cell. In this model, the diodes are defined by the
PSPICE parameters given in figure 17.
Note: This simulation model is available only for an ambient temperature of 27C.
Figure 16: PSPICE model
Figure 17: PSPICE parameters
Figure
18:
USBLC6-2 PCB layout
considerations
MODEL = Dlow
MODEL = Dhigh
VBUS
LI/O
LGND
GND
D+in
MODEL = Dzener
RI/O
LI/O
D-in
RI/O
LI/O
LI/O
RGND
RI/O
D-out
RI/O
MODEL = Dlow
MODEL = Dhigh
LI/O
D+out
RI/O
Dlow
Dhigh
Dzener
BV
50
50
7.3
CJ0
0.9p
2.0p
40p
IBV
1m
1m
1m
M
0.3333
0.3333
0.3333
RS
0.2
0.52
0.84
VJ
0.6
0.6
0.6
TT
0.1u
0.1u
0.1u
LI/O
750p
RI/O
110m
LGND
550p
RGND
60m
D+in
D+out
D-out
GND
USBLC6-2
D-in
V
BUS
1
C
= 100nF
BUS
USBLC6-2
9/11
Figure 20: SOT-666 Package Mechanical Data
Figure 19: Ordering Information Scheme
Figure 21: Foot Print Dimensions (in millimeters)
USB LC 6 - 2 xxx
Product Designation
Low capacitance
Breakdown Voltage
Packages
6 = 6 Volts
2 = 2 lines
SC6 = SOT23-6L
P6 = SOT-666
Number of lines protected
D
bp
e1
e
E
Lp
He
A
U
0.5
0.3
2.
7
5
0.
43
1.16
REF.
DIMENSIONS
Millimeters
Inches
Min.
Max.
Min.
Max.
A
0.50
0.60
0.020
0.024
bp
0.17
0.27
0.007
0.011
c
0.08
0.18
0.003
0.007
D
1.50
1.70
0.060
0.067
E
1.10
1.30
0.043
0.051
e
1.00 typ.
0.040 typ.
e1
0.50 typ.
0.020 typ.
He
1.50
1.70
0.059
0.067
Lp
0.10
0.30
0.004
0.012
USBLC6-2
10/11
Figure 22: SOT23-6L Package Mechanical Data
Figure 23: Foot Print Dimensions (in millimeters)
A2
A
L
H
c
B
E
D
e
e
A1
0.95
0.60
1.20
1.10
3.50
2.30
REF.
DIMENSIONS
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.90
1.45
0.035
0.057
A1
0
0.10
0
0.004
A2
0.90
1.30
0.035
0.051
b
0.35
0.50
0.014
0.02
C
0.09
0.20
0.004
0.008
D
2.80
3.05
0.110
0.120
E
1.50
1.75
0.059
0.069
e
0.95
0.037
H
2.60
3.00
0.102
0.118
L
0.10
0.60
0.004
0.024
0
10
0
10
Table 4: Ordering Information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
USBLC6-2SC6
UL26
SOT23-6L
16.7 mg
3000
Tape & reel
USBLC6-2P6
F
SOT-666
2.9 mg
3000
Tape & reel
Table 5: Revision History
Date
Revision
Description of Changes
14-Mar-2005
1
First issue.
07-Jun-2005
2
Format change to figure 3; no content changed.
USBLC6-2
11/11
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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