Электронный компонент: uUPSD3412CV-24T1T

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1/152

September 2003

Rev. 1.2

UPSD3212C

UPSD3212CV

Flash Programmable System Devices

with 8032 Microcontroller Core and 16Kbit SRAM

FEATURES SUMMARY

s

The uPSD321X Devices combine a Flash PSD
architecture with an 8032 microcontroller core.
The uPSD321X Devices of Flash PSDs feature
dual banks of Flash memory, SRAM, general
purpose I/O and programmable logic, supervi-
sory functions and access via I

2

C, ADC and

PWM channels, and an on-board 8032 micro-
controller core, with two UARTs, three 16-bit
Timer/Counters and two External Interrupts. As
with other Flash PSD families, the uPSD321X
Devices are also in-system programmable (ISP)
via a JTAG ISP interface.

s

Large 2KByte SRAM with battery back-up
option

s

Dual bank Flash memories

� 64KByte main Flash memory

� 16KByte secondary Flash memory

s

Content Security

� Block access to Flash memory

s

Programmable Decode PLD for flexible address
mapping of all memories within 8032 space.

s

High-speed clock standard 8032 core (12-cycle)

s

I

2

C interface for peripheral connections

s

5 Pulse Width Modulator (PWM) channels

s

Analog-to-Digital Converter (ADC)

s

Six I/O ports with up to 46 I/O pins

s

3000 gate PLD with 16 macrocells

s

Supervisor functions with Watchdog Timer

s

In-System Programming (ISP) via JTAG

s

Zero-Power Technology

s

Single Supply Voltage

� 4.5 to 5.5V

� 3.0 to 3.6V

Figure 1. 52-lead, Thin, Quad, Flat Package

Figure 2. 80-lead, Thin, Quad, Flat Package

TQFP52 (T)

TQFP80 (U)

UPSD3212C, UPSD3212CV

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TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

uPSD321X Devices Product Matrix (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

80-Pin Package Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Direct Addressing (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Indirect Addressing (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Indexed Addressing (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Arithmetic Instructions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logical Instructions (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data Transfer Instructions that Access Internal Data Memory Space (Table 6.) . . . . . . . . . . . . . . 24

Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.) . . . . . . . 25

Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.) . . . . . . . . 25

Shifting a BCD Number One Digit to the Right (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Transfer Instruction that Access External Data Memory Space (Table 10.) . . . . . . . . . . . . . . 26

Lookup Table READ Instruction (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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UPSD3212C, UPSD3212CV

Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Boolean Instructions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Unconditional Jump Instructions (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Conditional Jump Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

State Sequence in uPSD321X Devices (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

uPSD3200 HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

uPSD321X Devices Functional Modules (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SFR Memory Map (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

List of all SFR (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PSD Module Register Address Offset (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

External Int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

I2C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

External Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupt System (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Priority Levels (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SFR Register (Table 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Description of the IE Bits. (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IEA Bits (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IP Bits (Table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IPA Bits (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Vector Addresses (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

UPSD3212C, UPSD3212CV

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POWER-SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Saving Mode Power Consumption (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Pin Status During Idle and Power-down Mode (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Description of the PCON Bits (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I/O Port Functions (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

P1SFS (91H) (Table 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

P3SFS (93H) (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

P4SFS (94H) (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PORT Type and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PORT Type and Description (Part 1) (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PORT Type and Description (Part 2) (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Oscillator (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SUPERVISORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

RESET Configuration (Figure 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Low VDD Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Watchdog Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Watchdog Timer Key Register (WDKEY: 0AEH) (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Description of the WDKEY Bits (Table 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

RESET Pulse Width (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Watchdog Timer Clear Register (WDRST: 0A6H) (Table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Description of the WDRST Bits (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0

TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Control Register (TCON) (Table 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Description of the TCON Bits (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

TMOD Register (TMOD) (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Description of the TMOD Bits (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Timer/Counter Mode 0: 13-bit Counter (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter Mode 2: 8-bit Auto-reload (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter 2 Control Register (T2CON) (Table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter 2 Operating Modes (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Description of the T2CON Bits (Table 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Timer 2 in Capture Mode (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timer 2 in Auto-Reload Mode (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timer/Counter Mode 3: Two 8-bit Counters (Figure 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Port Mode 0, Block Diagram (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Port Control Register (SCON) (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Description of the SCON Bits (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Timer 1-Generated Commonly Used Baud Rates (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Serial Port Mode 0, Waveforms (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Serial Port Mode 1, Block Diagram (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Serial Port Mode 1, Waveforms (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Serial Port Mode 2, Block Diagram (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Serial Port Mode 2, Waveforms (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Serial Port Mode 3, Block Diagram (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Serial Port Mode 3, Waveforms (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

A/D Block Diagram (Figure 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

ADC SFR Memory Map (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Description of the ACON Bits (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

ADC Clock Input (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4-channel PWM Unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Four-Channel 8-bit PWM Block Diagram (Figure 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

PWM SFR Memory Map (Table 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Programmable PWM 4 Channel Block Diagram (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

PWM 4 With Programmable Pulse Width and Frequency (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . 74

Document Outline

• FEATURES SUMMARY
  • Figure 1. 52-lead, Thin, Quad, Flat Package
  • Figure 2. 80-lead, Thin, Quad, Flat Package
• TABLE OF CONTENTS
• SUMMARY DESCRIPTION
  • Table 1. uPSD321X Devices Product Matrix
  • Figure 3. TQFP52 Connections
  • Figure 4. TQFP80 Connections
  • Table 2. 80-Pin Package Pin Description
• 52 PIN PACKAGE I/O PORT
• ARCHITECTURE OVERVIEW
  • Memory Organization
    • Figure 5. Memory Map and Address Space
  • Registers
    • Figure 6. 8032 MCU Registers
    • Figure 7. Configuration of BA 16-bit Registers
    • Figure 8. Stack Pointer
    • Figure 9. PSW (Program Status Word) Register
  • Program Memory
  • Data memory
  • RAM
  • XRAM-PSD
    • Figure 10. Interrupt Location of Program Memory
  • SFR
    • Table 3. RAM Address
  • Addressing Modes
    • Figure 11. Direct Addressing
    • Figure 12. Indirect Addressing
    • Figure 13. Indexed Addressing
  • Arithmetic Instructions
    • Table 4. Arithmetic Instructions
  • Logical Instructions
    • Table 5. Logical Instructions
  • Data Transfers
    • Table 6. Data Transfer Instructions that Access Internal Data Memory Space
    • Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes)
    • Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes)
    • Table 9. Shifting a BCD Number One Digit to the Right
    • Table 10. Data Transfer Instruction that Access External Data Memory Space
    • Table 11. Lookup Table READ Instruction
  • Boolean Instructions
  • Relative Offset
    • Table 12. Boolean Instructions
  • Jump Instructions
    • Table 13. Unconditional Jump Instructions
  • Machine Cycles
    • Table 14. Conditional Jump Instructions
    • Figure 14. State Sequence in uPSD321X Devices
• uPSD3200 HARDWARE DESCRIPTION
  • Figure 15. uPSD321X Devices Functional Modules
• MCU MODULE DISCRIPTION
  • Special Function Registers
    • Table 15. SFR Memory Map
    • Table 16. List of all SFR
    • Table 17. PSD Module Register Address Offset
• INTERRUPT SYSTEM
  • External Int0
  • Timer 0 and 1 Interrupts
  • Timer 2 Interrupt
  • I2C Interrupt
  • External Int1
    • Figure 16. Interrupt System
  • USART Interrupt
  • Interrupt Priority Structure
  • Interrupts Enable Structure
    • Table 18. Priority Levels
    • Table 19. SFR Register
    • Table 20. Description of the IE Bits.
    • Table 21. Description of the IEA Bits
    • Table 22. Description of the IP Bits
    • Table 23. Description of the IPA Bits
  • How Interrupts are Handled
    • Table 24. Vector Addresses
• POWER-SAVING MODE
  • Idle Mode
  • Power-Down Mode
  • Power Control Register
  • Idle Mode
  • Power-Down Mode
    • Table 25. Power-Saving Mode Power Consumption
    • Table 26. Pin Status During Idle and Power-down Mode
    • Table 27. Description of the PCON Bits
• I/O PORTS (MCU Module)
  • Table 28. I/O Port Functions
  • Table 29. P1SFS (91H)
  • Table 30. P3SFS (93H)
  • Table 31. P4SFS (94H)
  • PORT Type and Description
    • Figure 17. PORT Type and Description (Part 1)
    • Figure 18. PORT Type and Description (Part 2)
• OSCILLATOR
  • Figure 19. Oscillator
• SUPERVISORY
  • External Reset
  • Low VDD Voltage Reset
  • Watchdog Timer Overflow
    • Figure 20. RESET Configuration
• WATCHDOG TIMER
  • Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)
  • Table 33. Description of the WDKEY Bits
  • Figure 21. RESET Pulse Width
  • Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)
  • Table 35. Description of the WDRST Bits
• TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)
  • Timer 0 and Timer 1
    • Table 36. Control Register (TCON)
    • Table 37. Description of the TCON Bits
    • Table 38. TMOD Register (TMOD)
    • Table 39. Description of the TMOD Bits
    • Figure 22. Timer/Counter Mode 0: 13-bit Counter
  • Timer 2
    • Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload
    • Table 40. Timer/Counter 2 Control Register (T2CON)
    • Table 41. Timer/Counter 2 Operating Modes
    • Table 42. Description of the T2CON Bits
    • Figure 24. Timer 2 in Capture Mode
    • Figure 25. Timer 2 in Auto-Reload Mode
    • Figure 26. Timer/Counter Mode 3: Two 8-bit Counters
• STANDARD SERIAL INTERFACE (UART)
  • Multiprocessor Communications
  • Serial Port Control Register
    • Figure 27. Serial Port Mode 0, Block Diagram
    • Table 43. Serial Port Control Register (SCON)
    • Table 44. Description of the SCON Bits
    • Table 45. Timer 1-Generated Commonly Used Baud Rates
    • Figure 28. Serial Port Mode 0, Waveforms
    • Figure 29. Serial Port Mode 1, Block Diagram
    • Figure 30. Serial Port Mode 1, Waveforms
    • Figure 31. Serial Port Mode 2, Block Diagram
    • Figure 32. Serial Port Mode 2, Waveforms
    • Figure 33. Serial Port Mode 3, Block Diagram
    • Figure 34. Serial Port Mode 3, Waveforms
• ANALOG-TO-DIGITAL CONVERTOR (ADC)
  • ADC Interrupt
    • Figure 35. A/D Block Diagram
    • Table 46. ADC SFR Memory Map
    • Table 47. Description of the ACON Bits
    • Table 48. ADC Clock Input
• PULSE WIDTH MODULATION (PWM)
  • 4-channel PWM Unit (PWM 0-3)
    • Figure 36. Four-Channel 8-bit PWM Block Diagram
    • Table 49. PWM SFR Memory Map
  • Programmable Period 8-bit PWM
    • Figure 37. Programmable PWM 4 Channel Block Diagram
  • PWM 4 Channel Operation
    • Figure 38. PWM 4 With Programmable Pulse Width and Frequency
• I2C INTERFACE
  • Figure 39. Block Diagram of the I2C Bus Serial I/O
  • Table 50. Serial Control Register (S2CON)
  • Table 51. Description of the S2CON Bits
  • Table 52. Selection of the Serial Clock Frequency SCL in Master Mode
  • Serial Status Register (S2STA)
  • Data Shift Register (S2DAT)
    • Table 53. Serial Status Register (S2STA)
    • Table 54. Description of the S2STA Bits
    • Table 55. Data Shift Register (S2DAT)
  • Address Register (S2ADR)
    • Table 56. Address Register (S2ADR)
    • Table 57. Start /Stop Hold Time Detection Register (S2SETUP)
    • Table 58. System Cock of 40MHz
    • Table 59. System Clock Setup Examples
• PSD MODULE
  • Functional Overview
    • Figure 40. PSD MODULE Block Diagram
  • In-System Programming (ISP)
    • Table 60. Methods of Programming Different Functional Blocks of the PSD MODULE
• DEVELOPMENT SYSTEM
  • Figure 41. PSDsoft Express Development Tool
• PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
  • Table 61. Register Address Offset
• PSD MODULE DETAILED OPERATION
• MEMORY BLOCKS
  • Primary Flash Memory and Secondary Flash memory Description
  • Memory Block Select Signals
  • Instructions
    • Table 62. Instructions
  • Power-down Instruction and Power-up Mode
  • READ
    • Table 63. Status Bit
  • Programming Flash Memory
    • Figure 42. Data Polling Flowchart
    • Figure 43. Data Toggle Flowchart
  • Erasing Flash Memory
  • Specific Features
    • Table 64. Sector Protection/Security Bit Definition � Flash Protection Register
    • Table 65. Sector Protection/Security Bit Definition � Secondary Flash Protection Register
  • SRAM
  • Sector Select and SRAM Select
    • Figure 44. Priority Level of Memory and I/O Components in the PSD MODULE
    • Table 66. VM Register
    • Figure 45. Separate Space Mode
    • Figure 46. Combined Space Mode
  • Page Register
    • Figure 47. Page Register
• PLDs
  • Table 67. DPLD and CPLD Inputs
  • The Turbo Bit in PSD MODULE
    • Figure 48. PLD Diagram
  • Decode PLD (DPLD)
    • Figure 49. DPLD Logic Array
  • Complex PLD (CPLD)
    • Figure 50. Macrocell and I/O Port
  • Output Macrocell (OMC)
    • Table 68. Output Macrocell Port and Data Bit Assignments
  • Product Term Allocator
    • Figure 51. CPLD Output Macrocell
  • Input Macrocells (IMC)
    • Figure 52. Input Macrocell
• I/O PORTS (PSD MODULE)
  • General Port Architecture
    • Figure 53. General I/O Port Architecture
  • Port Operating Modes
  • MCU I/O Mode
  • PLD I/O Mode
  • Address Out Mode
  • Peripheral I/O Mode
  • JTAG In-System Programming (ISP)
    • Figure 54. Peripheral I/O Mode
    • Table 69. Port Operating Modes
    • Table 70. Port Operating Mode Settings
    • Table 71. I/O Port Latched Address Output Assignments
  • Port Configuration Registers (PCR)
    • Table 72. Port Configuration Registers (PCR)
    • Table 73. Port Pin Direction Control, Output Enable P.T. Not Defined
    • Table 74. Port Pin Direction Control, Output Enable P.T. Defined
    • Table 75. Port Direction Assignment Example
  • Port Data Registers
    • Table 76. Drive Register Pin Assignment
    • Table 77. Port Data Registers
  • Ports A and B � Functionality and Structure
    • Figure 55. Port A and Port B Structure
  • Port C � Functionality and Structure
    • Figure 56. Port C Structure
  • Port D � Functionality and Structure
    • Figure 57. Port D Structure
  • External Chip Select
    • Figure 58. Port D External Chip Select Signals
• POWER MANAGEMENT
  • Figure 59. APD Unit
  • Figure 60. Enable Power-down Flow Chart
  • Table 78. Power-down Mode�s Effect on Ports
  • PLD Power Management
  • PSD Chip Select Input (CSI, PD2)
  • Input Clock
  • Input Control Signals
    • Table 79. Power Management Mode Registers PMMR0
    • Table 80. Power Management Mode Registers PMMR2
    • Table 81. APD Counter Operation
• RESET TIMING AND DEVICE STATUS AT RESET
  • Warm RESET
  • I/O Pin, Register and PLD Status at RESET
    • Figure 61. Reset (RESET) Timing
    • Table 82. Status During Power-on RESET, Warm RESET and Power-down Mode
• PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
  • Standard JTAG Signals
    • Table 83. JTAG Port Signals
  • JTAG Extensions
  • Security and Flash memory Protection
• INITIAL DELIVERY STATE
• AC/DC PARAMETERS
  • Figure 62. PLD ICC /Frequency Consumption (5V range)
  • Figure 63. PLD ICC /Frequency Consumption (3V range)
  • Table 84. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
• MAXIMUM RATING
  • Table 85. Absolute Maximum Ratings
• DC AND AC PARAMETERS
  • Table 86. Operating Conditions (5V Devices)
  • Table 87. Operating Conditions (3V Devices)
  • Table 88. AC Symbols for Timing
  • Figure 64. Switching Waveforms � Key
  • Table 89. DC Characteristics (5V Devices)
  • Table 90. DC Characteristics (3V Devices)
  • Figure 65. External Program Memory READ Cycle
  • Table 91. External Program Memory AC Characteristics (with the 5V MCU Module)
  • Table 92. External Program Memory AC Characteristics (with the 3V MCU Module)
  • Table 93. External Clock Drive (with the 5V MCU Module)
  • Table 94. External Clock Drive (with the 3V MCU Module)
  • Figure 66. External Data Memory READ Cycle
  • Figure 67. External Data Memory WRITE Cycle
  • Table 95. External Data Memory AC Characteristics (with the 5V MCU Module)
  • Table 96. External Data Memory AC Characteristics (with the 3V MCU Module)
  • Table 97. A/D Analog Specification
  • Figure 68. Input to Output Disable / Enable
  • Table 98. CPLD Combinatorial Timing (5V Devices)
  • Table 99. CPLD Combinatorial Timing (3V Devices)
  • Figure 69. Synchronous Clock Mode Timing � PLD
  • Table 100. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
  • Table 101. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
  • Figure 70. Asynchronous RESET / Preset
  • Figure 71. Asynchronous Clock Mode Timing (product term clock)
  • Table 102. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
  • Table 103. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
  • Figure 72. Input Macrocell Timing (product term clock)
  • Table 104. Input Macrocell Timing (5V Devices)
  • Table 105. Input Macrocell Timing (3V Devices)
  • Table 106. Program, WRITE and Erase Times (5V Devices)
  • Table 107. Program, WRITE and Erase Times (3V Devices)
  • Figure 73. Peripheral I/O READ Timing
  • Table 108. Port A Peripheral Data Mode READ Timing (5V Devices)
  • Table 109. Port A Peripheral Data Mode READ Timing (3V Devices)
  • Figure 74. Peripheral I/O WRITE Timing
  • Table 110. Port A Peripheral Data Mode WRITE Timing (5V Devices)
  • Table 111. Port A Peripheral Data Mode WRITE Timing (3V Devices)
  • Figure 75. Reset (RESET) Timing
  • Table 112. Reset (RESET) Timing (5V Devices)
  • Table 113. Reset (RESET) Timing (3V Devices)
  • Table 114. VSTBYON Definitions Timing (5V Devices)
  • Table 115. VSTBYON Timing (3V Devices)
  • Figure 76. ISC Timing
  • Table 116. ISC Timing (5V Devices)
  • Table 117. ISC Timing (3V Devices)
  • Figure 77. MCU Module AC Measurement I/O Waveform
  • Figure 78. PSD MODULE AC Float I/O Waveform
  • Figure 79. External Clock Cycle
  • Figure 80. Recommended Oscillator Circuits
  • Figure 81. PSD MODULE AC Measurement I/O Waveform
  • Figure 82. PSD MODULEAC Measurement Load Circuit
  • Table 118. Capacitance
• PACKAGE MECHANICAL INFORMATION
  • Figure 83. TQFP52 � 52-lead Plastic Quad Flatpack Package Outline
  • Table 119. TQFP52 � 52-lead Plastic Quad Flatpack Package Mechanical Data
  • Figure 84. TQFP80 � 80-lead Plastic Quad Flatpack Package Outline
  • Table 120. TQFP80 � 80-lead Plastic Quad Flatpack Package Mechanical Data
• PART NUMBERING
  • Table 121. Ordering Information Scheme
• REVISION HISTORY
  • Table 122. Document Revision History