SUMMIT MICROELECTRONICS, Inc. · 300 Orchard City Drive, Suite 131 · Campbell, CA 95008 · Telephone 408-378-6461 · Fax 408-378-6586 · www.summitmicro.com

Characteristics subject to change without notice

SUMMIT

MICROELECTRONICS, Inc.

S24163

FEATURES

· Precision Supply Voltage Monitor

Precision Supply Voltage Monitor

-- Active Low

-- Active Low
-- Integrated memory write lockout

-- Integrated memory write lockout

· Guaranteed RESET (RESET#) assertion

Guaranteed RESET (RESET#) assertion

Guaranteed RESET (RESET#) assertion
to V

to V

= 1V

· Power-Fail Accuracy Guaranteed

Power-Fail Accuracy Guaranteed

· No External Components

No External Components

· 3V and 5V system versions

3V and 5V system versions

· Low Power CMOS

Low Power CMOS

-- Active current less than 3mA

Active current less than 3mA

-- Standby current less than 25µA

Standby current less than 25µA

· Memory Internally Organized 2k X 8

Memory Internally Organized 2k X 8

-- Two Wire Serial Interface (I

Two Wire Serial Interface (I

CTM)

Bidirectional data transfer protocol

Standard 100KHz and Fast 400KHz

Precision RESET Contr

ecision RESET Contr

ecision RESET Controller with 16K I

oller with 16K I

C Memor

C Memory

· High Reliability

High Reliability

-- Endurance: 100,000 erase/write cycles

Endurance: 100,000 erase/write cycles

-- Data retention: 100 years

Data retention: 100 years

· 8-Pin PDIP or SOIC Packages

8-Pin PDIP or SOIC Packages

OVERVIEW

The S24163 is a power supervisory device with 16,384-
bits of serial E

PROM. It is fabricated using SUMMIT's

advanced CMOS E

PROM technology and is suitable for

both 3 and 5 volt systems.

The S24163 is internally organized as 2048 x 8. It fea-
tures the I

C serial interface and software protocol allow-

ing operation on a simple two-wire bus.

BLOCK DIAGRAM

3 and 5 Volt Systems

GND

VCC

RESET#

VTRIP

RESET
PULSE

GENERATOR

5kHz

OSCILLATOR

RESET

CONTROL

MODE

DECODE

ADDRESS

DECODER

WRITE

CONTROL

DATA I/O

E2PROM

MEMORY

ARRAY

1.26V

SCL

SDA

2014 T BD 2.0

S24163

2014 2.0 3/21/00

ENDURANCE AND DATA RETENTION

The S24163 is designed for applications requiring up to
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or without
power applied, after the execution of 100,000 erase/write
cycles.

APPLICATIONS

The S24163 is ideal for applications requiring low voltage
and low power consumption. This device provides
microcontroller RESET control and can be manually
resettable. This device also uses a cost effective, space-
saving, 8-pin SOIC or PDIP plastic package. Typical
applications include alarm devices, electronic locks,
meters, keys, pagers and cellular phones.

RESET CONTROLLER DESCRIPTION

The device provides a precise reset output to a
microcontroller and it's associated circuitry ensuring cor-
rect system operation during power-up/down conditions
and brownout situations. The output is open drain, allow-
ing control of the reset function by multiple devices.

During power-up the reset output remains in a fixed active
state until V

passes through the reset threshold and

remains above the threshold for 200ms. The reset output
is valid whenever V

1V. If V

falls below the

threshold for more than t

GLITCH

the device will immediately

generate a reset and drive the output.

The reset pin is an I/O; therefore, forcing the pin to the
active state can also manually reset the device. Because
the I/O needs to be an open drain, the internal timer can
only be triggered by the leading edge of the input. The
resulting reset output will either be t

PURST

, or the exter-

nally applied reset signal, whichever is longer. This can
provide an affective debounce or reset signal extender
solution.

CHARACTERISTICS OF THE I

C BUS

General Description

General Description
The I

C bus was designed for two-way, two-line serial

communication between different integrated circuits. The
two lines are a serial data line (SDA), and a serial clock line
(SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 1). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).

PIN DESCRIPTIONS

SCL -- Serial Clock:

SCL -- Serial Clock: The SCL input is used to clock data
into and out of the device. In the WRITE mode data must
remain stable while SCL is HIGH. In the READ mode data
is clocked out on the falling edge of SCL.

SDA --

SDA -- Serial Data:

Serial Data:

Serial Data: The SDA pin is a bidirectional pin

used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.

RESET# -- Reset:

RESET# -- Reset: This is an active low open drain output.
It is driven low whenever V

is below V

TRIP

. It is also an

input and can be used to debounce a switch input or
perform signal conditioning. The pin has an internal pull-up
and should be left unconnected if the signal is not used in
the system. However, an external pull-up resistor must be
connected when the pin is tied to a system RESET# line.

-- Power

-- Power: V

is the voltage input, typically 2.7 to 5.5

volts.

GND -- Ground

GND -- Ground: Power return.

NC -- No Connect:

No Connect:

No Connect: The no connect inputs are not used.

However, to ensure proper operation, they can be uncon-
nected or tied to ground. They must not be tied to V

PIN CONFIGURATION

RESET#

VSS

VCC
NC
SCL
SDA

1
2
3
4

8
7
6
5

SMS24163

8-Pin PDIP

or 8-Pin SOIC

2014 T PCon 2.0

S24163

2014 2.0 3/21/00

FIGURE 1. TYPICAL SYSTEM CONFIGURATION

FIGURE 3. START AND STOP CONDITIONS

FIGURE 2. INPUT DATA PROTOCOL

Data must

remain stable

while clock

is HIGH.

Data must

remain stable

while clock

is HIGH.

Change

of data

allowed

SCL

SDA In

HD:DAT

SU:DAT

HD:DAT

2014 ILL4 1.0

SCL

SDA In

START

Condition

STOP

Condition

2014 ILL5 1.0

SDA

SCL

(µC/ µP)

(24163)

2014 T fig01 2.0

RESET

Master

Transmitter

Slave

Transmitter/

Receiver

Master

Transmitter/

Receiver

Slave

Receiver

Master

Transmitter/

Receiver

S24163

2014 2.0 3/21/00

FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER

Input Data Protocol

Input Data Protocol
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition (See
Figure 2).

START and STOP Conditions

START and STOP Conditions
When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the "START"
condition. A LOW-to-HIGH transition on the data line, while
the clock is HIGH, is defined as the "STOP" condition (See
Figure 3).

DEVICE OPERATION

The S24163 is a 16,384-bit serial E

PROM. The device

supports the I

C bidirectional data transmission protocol.

The protocol defines any device that sends data onto the
bus as a "transmitter" and any device which receives data
as a "receiver." The device controlling data transmission
is called the "master" and the controlled device is called
the "slave." Since it never initiates any data transfers the
S24163 is always a "slave" device.

Acknowledge (ACK)

Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to ACKnowledge that it
received the eight bits of data (See Figure 4).

The S24163 will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S24163 will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word.

FIGURE 5. SLAVE ADDRESS BYTE

In the READ mode the S24163 transmits eight bits of data,
then releases the SDA line, and monitors the line for an
ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24163 will continue to transmit data. If an ACKnowledge is
not detected the S24163 will terminate further data transmis-
sions and await a STOP condition before returning to the
standby power mode.

Device Addressing

Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 5). For the S24163 this is fixed as 1010[B

HEX

Word Address

Word Address
The next three bits of the slave address are an extension
of the array's address and are concatenated with the eight
bits of address in the word address field, providing direct
access to the 2,048 X 8 array.

Read/Write Bit

Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to "1" a read operation is selected;
when set to "0" a write operation is selected.

SCL from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start
Condition

ACKnowledge

2014 ILL6 1.0

1 0 1 0

A10 A9 A8 R/W

DEVICE

IDENTIFIER

HIGH ORDER

WORD ADDRESS

2014 ILL7 1.0

S24163

2014 2.0 3/21/00

FIGURE 6. PAGE/BYTE WRITE MODE

WRITE OPERATIONS

The S24163 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (t

). The

page write operation allows up to 16 bytes in the same
page to be written during t

Byte

Byte WRITE

WRITE

After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 2,048
words in the array.

Upon receipt of the word address, the S24163 responds
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The master
then terminates the transfer by generating a STOP condi-
tion, at which time the S24163 begins the internal write
cycle.

While the internal write cycle is in progress, the S24163
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 6 for the
address, ACKnowledge and data transfer sequence.

Page

Page WRITE

WRITE

The S24163 is capable of a 16-byte page write operation.
It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
words of data. After the receipt of each word, the S24163
will respond with an ACKnowledge.

The S24163 automatically increments the address for
subsequent data words. After the receipt of each word, the
four low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the ad-
dress counter will "roll over," and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 6 for the address, ACKnowledge and data
transfer sequence.

S
T
A
R
T

Word Address

Data Byte n

Data Byte n+15

S
T

A
C
K

Acknowledges Transmitted from

24163 to Master Receiver

Slave Address

Device

Type

Address

Read/Write

0= Write

A10,A9,A8

SDA
Bus
Activity

A
C
K

Master Sends Read
Request to Slave

Master Writes Word
Address to Slave

1 0 1 0

Data Byte n+1

A
C
K

Master Writes
Data to Slave

Master Transmitter

Slave Receiver

Slave Transmitter

Master Receiver

Slave Transmitter

Master Receiver

Master Transmitter

Slave Receiver

Master Transmitter

Slave Receiver

Shading Denotes

24163

SDA Output Active

Master Transmitter

Slave Receiver

Slave Transmitter

Master Receiver

Slave Transmitter

Master Receiver

Master Transmitter

Slave Receiver

Slave Transmitter

Master Receiver

Master Writes
Data to Slave

Acknowledges Transmitted from

24163 to Master Receiver

If single byte-write only,

Stop bit issued here.

A
C
K

2014 T fig06 2.0

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