SMM665

Preliminary Information

(See Last Page)

© SUMMIT Microelectronics, Inc. 2003

1717 Fox Drive · San Jose CA 95131 · Phone 408 436-9890 · FAX 408 436-9897

www.summitmicro.com

2067 1.9 5/16/03

Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer

FEATURES & APPLICATIONS

· Extremely accurate (±0.1%) Active
DC Output Control (ADOC)

· ADOC Automatically adjusts supply output
voltage level under all load conditions

· Monitors, controls, sequences and margins up
to six supplies from 0.3V to 5.5V with 1.25V Vref

Wide Margin/ADOC range from 0.3V to VDD

· Programmable Power-on/-off sequencing

· Monitors internal temperature sensor

· Operates from any intermediate bus supply

from 8V to 15V and from 2.7V to 5.5V

· Monitors 12V input and VDD

· Monitors two general-purpose 10-bit ADC inputs

· Programmable threshold limits (2 OV/2 UV) for
each monitored input

· Programmable RESET, HEALTHY and FAULT

· 4k-bit general purpose nonvolatile memory

· I

C 2-wire serial bus for programming

configuration and monitoring status, including
10-bit ADC conversion results

Applications

· Monitor/Control Distributed and POL Supplies

· Multi-voltage Processors, DSPs, ASICs used in
Telecom, CompactPCI or server systems

INTRODUCTION

The SMM665 is an Active DC Output power supply
Controller (ADOC) that monitors, margins and
cascade sequences. The ADOC feature is unique and
maintains extremely accurate settings of system
supply voltages to within ±0.2% under full load. The
device actively controls up to six bricks or DC/DC
converters that use a Trim or VADJ/FB pin to adjust
the output voltage. For system test, the part also
controls margining of the supplies using I

commands. It can margin supplies with either positive
or negative control within a range of 0.3V to VDD
depending on the specified range of the converter.
The SMM665 also intelligently sequences or cascades
the power supplies on and off in any order using
enable outputs with programmable polarity. It can
operate off any intermediate bus supply ranging from
8V to 15V or from 5.5V to as low as 2.7V. The part
monitors six power supply channels as well as VDD,
12V input, two general-purpose analog inputs and an
internal temperature sensor using a 10-bit ADC. The
10-bit ADC can measure the value on any one of the
monitor channels and output the data via the I

C bus.

A host system can communicate with the SMM665
status register, optionally control Power-on/off,
margining and utilize 4K-bits of nonvolatile memory.

SIMPLIFIED APPLICATIONS DRAWING

TRIM

PUP

TRIM_CAP

CAP

TRIM

PUP

TRIM_CAP

CAP

SMM665

µP/

ASIC

RST

HEA

THY

3.3VIN (+2.7V to +5.5V Range)

RESET

READY

HEALTHY

I
N

12VIN (+10V to +15V Range)

External

Internal

TEMP

SENSOR

AIN1

VREF_ADC

2.5VIN

1.2VIN

12V

SDA

SCL

BUS

3.3V

VREF_CNTL

VIN

TRIM

Vout

DC/DC

Converter A

ON/OFF

VIN

TRIM

Vout

DC/DC

Converter B

ON/OFF

External or

Internal

REFERENCE

Environ

mental

SENSOR

AIN2

DC/DC

Converter C, E

DC/DC

Converter D, F

2 of 6 DC-DC
Converters shown

Figure 1 Applications Schematic using the SMM665 Controller to actively control the output levels of up to

six DC/DC Converters while also providing power on/off, cascade sequencing and output margining.

Note: This is an applications example only. Some pins, components and values are not shown.

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

GENERAL DESCRIPTION

The SMM665 is a highly integrated and accurate
power supply controller, monitor and sequencer. It
has the ability to automatically control, monitor and
cascade sequence up to six power supplies. Also, the
SMM665 can monitor the VDD input, the 12V input,
two general-purpose analog inputs and the internal
temperature sensor. The SMM665 has four operating
modes: Power-on sequencing mode, monitor mode,
supply margining mode using Active DC Output
Control (ADOC), and Power-off sequencing mode.
Power-on sequencing can be initiated via the
PWR_ON/OFF pin or I

C control. In this mode, the

SMM665 will sequence the power supply channels on
in any order by activating the PUP outputs and
monitoring the respective converter voltages to ensure
cascading of the supplies. Cascade sequencing is the
ability to hold off the next sequenced supply until the
first supply reaches a programmed threshold. A
programmable sequence termination timer can be set
to disable all channels if the Power-on sequence
stalls. Once all supplies have sequenced on and the
voltages are above the UV settings, the Active DC
Control, if enabled, will bring the supply voltages to
their nominal settings. During this mode, the
HEALTHY output will remain inactive and the RST
output will remain active.
Once the Power-on sequencing mode is complete, the
SMM665 enters monitor mode. In the monitor mode,
the SMM665 starts the ADOC control of the supplies
and adjusts the output voltage to the programmed
setting under all load conditions, especially useful for
supplies without sense lines. Typical converters have
±2% accuracy ratings for their output voltage, the
Active DC Output Control feature of the SMM665
increases the accuracy to

±0.2% (using a ±0.1%

external voltage reference). The part also enables the

triggering of outputs by monitored fault conditions.
The 10-bit ADC cycles through all 11 channels every
2ms and checks the conversions against the
programmed threshold limits. The results can be used
to trigger RST, HEALTHY and FAULT outputs as well
as to trigger a Power-off or a Force Shutdown
operation.
While the SMM665 is in its monitoring mode, an I

command to margin the supply voltages can bring the
part into margining mode. In margining mode the
SMM665 can margin six supply voltages in any
combination of nominal, high and low voltage settings
using the ADOC feature, all to within ±0.2% using a
±0.1% external reference. The margin high and
margin low voltage settings can range from 0.3V to
VDD around the converters' nominal output voltage
setting depending on the specified margin range of the
DC-DC converter. During this mode the HEALTHY
output is always active and the RST output is always
inactive regardless of the voltage threshold limit
settings and triggers. Furthermore, the triggers for
Power-off and Force Shutdown are temporarily
disabled.
The Power-off sequencing mode can only be entered
while the SMM665 is in the monitoring mode. It can
be initiated by either bringing the PWR_ON/OFF pin
inactive, through I

C control or triggered by a channel

exceeding its programmed thresholds. Once Power-
off is initiated, it will disable the Active DC Control and
sequence the PUP outputs off in either the same or
reverse order as Power-on sequencing and monitor
the supply voltages to ensure cascading of the
supplies as they turn off. The sequence termination
timer can be programmed to immediately disable all
channels if the Power-off sequencing stalls. The RST
output will remain active throughout this mode while
the HEALTHY output remains inactive.

Figure 2 Example Power Supply Sequencing and System Start-up Initialization using the SMM665. Any
order of supply sequencing can be applied using the SMM665. Power supply ordering, trimming and Active
DC control allows supply cascade sequencing, automatic level adjustment, margin testing and reset control.

2.5V

2.7V

1.8V

2.0V

1.5V

VDD (+2.7V to +5.5V)
or 12VIN ( +8V to +15V)

RST#

---

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

Pin

Number

Pin

Type

Pin Name

Pin Description

DATA SDA I

C Bi-directional data line

CLK SCL I

C Clock line

IN A2

The address pin is biased either to VDD_CAP or GND. When
communicating with the SMM665 over the 2-wire bus A2 provides a
mechanism for assigning a unique bus address.

IN MR

Programmable active high/low input. When asserted the RST output will be
go active. When de-asserted the RST output will go inactive immediately
after a reset timeout period (t

PRTO

) if there are no RST trigger sources active.

This timeout period makes it suitable to use a pushbutton for manual reset.

IN PWR_ON/OFF

Programmable active high/low input signals the start of the power
sequencing. When asserted the part will sequence the supplies on and
when de-asserted the part will sequence the supplies off.

IN FS

Programmable active high/low input. Force shutdown is used to immediately
turn off all converter enable signals (PUP outputs)

OUT FAULT

Programmable active high/low open drain Fault output. Active when a
programmed fault condition exists on AIN1, AIN2, or the internal temperature
sensor.

OUT HEALTHY

Programmable active high/low open drain Healthy output. Active when all
programmed power supply inputs and monitored inputs are within OV and
UV limits.

OUT RST

Programmable active high/low open drain Reset output. Active when a
programmed fault condition exists on any power supply inputs or monitored
inputs or when MR is active. RST has a programmable timeout period with
options for 0.64ms, 25ms, 100ms and 200ms.

IN AIN1

General purpose monitored analog input

IN AIN2

General purpose monitored analog input

GND GND Ground

IN VREF_ADC

Voltage reference input used for A/D conversion where:
(4XVREF_ADC) = Full Scale (FS) for VM

A-F

and VDD

(12XVREF_ADC) = FS for 12VIN
(2XVREF_ADC) = FS for AIN1 and AIN2.
VREF_ADC can be connected to VREF_CNTL in most applications.

I/O VREF_CNTL

Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V reference.

CAP FILT_CAP External capacitor input used to filter VM

inputs

41,36,
31,26,

21,16

IN VM

Positive converter sense line, VM

through VM

PIN DESCRIPTIONS

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

Pin

Number

Pin

Type

Pin Name

Pin Description

42,37,
32,27,

22,17

CAP CAP

External capacitor input used to filter the VM

inputs to the 10-bit ADC, CAP

through CAP

. This provides an RC filter where R = 25k.

43,38,
33,28,

23,18

OUT PUP

Programmable active high/low open drain converter enable output, PUP

through PUP

44,39,
34,29,

24,19

OUT TRIM

Output voltage used to control the output of DC/DC converters, TRIM

through TRIM

45,40,
35,30,

25,20

CAP TRIM_CAP

External sample and hold capacitor input used to set the voltage on the
TRIM pins, TRIM_CAP

through TRIM_CAP

PWR VDD Power supply of the part

PWR 12VIN 12V power supply input internally regulated to either 3.6V or 5.5V

CAP VDD_CAP External capacitor input used to filter the internal supply

PACKAGE AND PIN CONFIGURATION

48 LEAD TQFP

SDA

SCL

PWR_ON/OFF

FAULT

HEALTHY

RST

AIN1

AIN2

GND

VREF

I
M

VMB

TRIM_CAPC

TRIMC

PUPC

CAPC

VMC

TRIM_CAPD

TRIMD

PUPD

CAPD

VMD

TRIM_CAPE

DD_

I
N

I
M

PIN DESCRIPTIONS (Cont.)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ...................... -55

C to 125

Storage Temperature............................ -65

C to 150

Terminal Voltage with Respect to GND:
VDD Supply Voltage ..........................-0.3V to 6.0V
12VIN Supply Voltage......................-0.3V to 15.0V
All Others ................................-0.3V to V

+ 0.7V

Output Short Circuit Current ............................... 100mA
Lead Solder Temperature (10 secs).................... 300

Junction Temperature........................................150°C
ESD Rating per JEDEC.................................2000V
Latch-Up testing per JEDEC........................

100mA

Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.

RECOMMENDED OPERATING CONDITIONS

Temperature Range (Industrial)...........40

C to +85

(Commercial) ............5

C to +70

VDD Supply Voltage .................................. 2.7V to 5.5V
12VIN Supply Voltage (1) ........................ 8.0V to 14.0V
VIN ............................................................ GND to VDD
VOUT ...................................................... GND to 14.0V
Package Thermal Resistance (

)

48 Lead TQFP........................................80

C/W

Moisture Classification Level 1 (MSL 1) per J-STD- 020

Note 1 Range depends on internal regulator set to 3.6V or 5.5V,
see 12VIN specification below.

DC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol

Parameter

Notes

Min

Typ Max

Unit

VDD

Supply Voltage

2.7

5.5

Internally regulated to 5.5V

12VIN Supply

Voltage

Internally regulated to 3.6V

Power Supply Current from VDD

All TRIM pins floating,
12VIN floating

12VIN

Power Supply Current from 12VIN

All TRIM pins floating,
VDD floating

TRIM characteristics

TRIM Sourcing
Maximum Current

1.5

TRIM

TRIM output current through 100

1.0V

TRIM Sinking Maximum
Current

1.5

TRIM

Margin Control and ADOC Range

Depends on Trim range
of DC-DC Converter

VREF_CNTL/

VDD V

All other input and output characteristics

VDD = 2.7V

0.9xVDD

VDD

Input High Voltage (FS,
PWR_ON/OFF, MR#, SDA, SCL)

VDD = 5.0V

0.7xVDD

VDD

VDD = 2.7V

-0.1

0.1xVDD

Input Low Voltage (FS, PWR_ON/OFF,
MR#, SDA, SCL)

VDD = 5.0V

-0.1

0.3xVDD

Programmable Open Drain Outputs
(RST, HEALTHY, FAULT, PUPx)

SINK

= 1mA

0.4

Output Low Current

1.0

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

DC OPERATING CHARACTERISTICS (CONTINUED)

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter

Notes Min

Typ

Max

Unit

SENSE

Positive Sense Voltage

VM pin

+0.3

VDD_CAP

Monitor

Monitor Threshold Step Size

VM, AIN1/AIN2 pins

Monitor

Temperature Threshold Step Size Internal Temp Sensor

0.25

REF

Internal 1.25V

REF

Output Voltage

1.24

1.25

1.26

C to +85

-0.25 +0.25

REF

Internal V

REF

Temperature

Coefficient

C to +70

-0.15 +0.15

REF

ACC Internal V

REF

Accuracy

-0.4

+0.4

External
V

REF

External V

REF

Voltage Range

0.5

VDD_CAP

External VREF=1.25V, ±0.1%

-0.2

0.1

+0.2 %

ADOC

ACC

ADOC/Margin

Accuracy

Internal VREF=1.25V

-0.5

0.3

+0.5 %

AIN1/AIN2 ADC characteristics

N Resolution

10 Bits

MC Missing

Codes

Minimum resolution for which no
missing codes are guaranteed

10 Bits

S/N Signal-to-Noise

Ratio

Conversion rate = 500Hz

72 db

DNL Differential

Non-Linearity

-1/2 +1/2

LSB

INL Integral

Non-Linearity

-1 +1

LSB

GAIN

Positive full scale gain error

-0.5 +0.5

Offset Offset

Error

-1 +1

LSB

ZSE

Zero Scale Error

-1 +1

LSB

FSE

Full Scale Error

-1 +1

LSB

ADC_TC

Full Scale Temperature
Coefficient

±15

PPM/

ADC

Analog ADC Input Impedance

AIN1, AIN2

VREF_ADC

REF_ADC

Input Current

250

VREF_ADC

REF_ADC

Input Capacitance

200

VREF_ADC

REF_ADC

Input Impedance

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

AC OPERATING CHARACTERISTICS

Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4B and 4C Timing
diagrams.

Symbol Description

Conditions

Min

Typ

Max

Unit

DPON

= 0.64ms

DPON

= 12.5ms

DPON

= 25ms

DPON

Programmable Power-on delay from
VM

out-of-fault to PUP

active

DPON

= 50ms

-15 t

DPON

+15 %

DPOFF

= 0.64ms

DPOFF

= 12.5ms

DPOFF

= 25ms

DPOFF

Programmable Power-off delay from
VM

off to PUP

inactive

DPOFF

= 50ms

-15 t

DPOFF

+15 %

PRTO

= 0.64ms

PRTO

= 25ms

PRTO

= 100ms

PRTO

Programmable Reset Time-Out
Period

PRTO

= 200ms

-15 t

PRTO

+15 %

STT

= OFF

STT

= 100ms

STT

= 200ms

STT

Programmable Sequence
Termination Timer

STT

= 400ms

-15 t

STT

+15

ADC

10-bit ADC sampling period

Time for ADC conversion
of all 11 channels

DC_CONTROL

Active DC Control sampling period

Update period for Active
DC Control of channels
A F

1.7

settling

Settling Time

+ 10% change in voltage
with 0.1% ripple

100

Fast Margin,
TRIM_CAP=1

µF

100

MARGIN

Margin Time from Nominal to

Slow Margin,
TRIM_CAP=1

µF

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

C 2-WIRE SERIAL INTERFACE AC OPERATING

CHARACTERISTICS 100/400kHz

Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4A Timing Diagram.

100kHz 400kHz

Symbol Description

Conditions

Min Typ Max Min Typ Max Units

SCL

SCL Clock Frequency

100

400

KHz

LOW

Clock Low Period

4.7

1.3

µs

HIGH

Clock

High

Period

4.0 0.6 µs

BUF

Bus Free Time

Before New Transmission

Note 1/

4.7 1.3 µs

SU:STA

Start Condition Setup Time

4.7

0.6

µs

HD:STA

Start Condition Hold Time

4.0

0.6

µs

SU:STO

Stop Condition Setup Time

4.7

0.6

µs

Clock Edge to Data Valid

SCL low to valid
SDA (cycle n)

0.2 3.5 0.2 0.9 µs

Data Output Hold Time

SCL low (cycle n+1)
to SDA change

0.2 0.2 µs

SCL and SDA Rise Time

Note 1/

1000

SCL and SDA Fall Time

Note 1/

300 300 ns

SU:DAT

Data In Setup Time

250

150

HD:DAT

Data In Hold Time

Noise Filter SCL and SDA

Noise suppression

100

Write

Cycle

Time

Memory

Array

5 5 ms

Note: 1/ - Guaranteed by Design.

HIGH

LOW

SU:SDA

HD:SDA

SU:DAT

HD:DAT

SU:STO

BUF

SCL

SDA

(IN)

SDA

(OUT)

W R (For W rite Operation Only)

Figure 4A . Basic I

C Serial Interface Timing

TIMING DIAGRAMS

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

APPLICATIONS INFORMATION

DEVICE OPERATION

POWER SUPPLY
The SMM665 can be powered by either a 12V input
through the 12VIN pin or by a 3.3V or 5.0V input
through the VDD pin. The 12VIN pin feeds an internal
programmable regulator that internally generates
either 5.5V or 3.6V. A voltage arbitration circuit allows
the device to be powered by the highest voltage from
either the regulator output or the VDD input. This
voltage arbitration circuit continuously checks for these
voltages to determine which will power the SMM665.
The resultant internal power supply rail is connected to
the VDD_CAP pin that allows both filtering and hold-
up of the internal power supply.
MODES OF OPERATION
The SMM665 has four basic modes of operation
(shown in Figures 4B through 4E): Power-on cascade
sequencing mode, ongoing operations-monitoring
mode, supply margining mode and Power-off cascade
sequencing mode. In addition, there are two features:
ADOC and forced shutdown which can be used during
monitoring and margining mode. A detailed description
of each mode and feature follows.

ACTIVE DC OUTPUT CONTROL (ADOC)
The SMM665 can actively control the DC output
voltage of bricks or DC/DC converters that have a trim
pin during monitoring and margining mode. The
converter may be an off-the shelf compact device, or
may be a "roll your own" circuit on the application
board. In either case, the SMM665 dramatically
improves voltage accuracy (down to 0.2%) by
implementing closed-loop ADOC active control. This
utilizes the DC-DC's "trim" pin as shown in Figure 5A,
or an equivalent output voltage feedback adjustment
"VADJ" or "FB" node in a user's custom circuit, Figure
5B. Each of the TRIM

pins on the SMM665 is

connected to the trim input pins on the power supply
converters. A sense line from the channel's point-of-
load connects to the corresponding VM input. The
ADOC function cycles through all six channels (A-F)
every 1.7ms making slight adjustments to the voltage
on the associated TRIM

output pins based on the

voltage inputs on the VM

pins. These voltage

adjustments allow the SMM665 to control the output
voltage of power supply converters to within ±0.2%
when using a ±0.1% external voltage reference.

Figure 4D: Waveform showing four channels of the
SMM665 exhibiting Sequence-on to Nominal voltage,
Margin High or Low, Nominal voltage and then
sequence-off

Ch 1 = 2.5V DC-DC converter output (Yellow trace)
Ch 2 = 1.8V DC-DC converter output (Blue trace)
Ch 3 = 1.5V DC-DC converter output (Purple trace)
Ch 4 = 1.2V DC-DC converter output (Green trace

Figure 4E: Waveform showing two channels of the
SMM665 exhibiting Sequence-on to Nominal voltage,
Margin High and Low, Nominal voltage and then
sequence-off. Channel 3 shows the RST signal and
Channel 4 shows the HEALTHY signal.

Ch 1 = 2.5V DC-DC converter output (Yellow trace)
Ch 2 = 1.5V DC-DC converter output (Blue trace)
Ch 3 = RST signal output (Purple trace)
Ch 4 = HEALTHY signal output (Green trace

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

A pulse of current, either sourced or sunk for 5µs
every 1.7ms, to the capacitors connected to the
TRIM_CAP

pins adjusts the voltage output on the

TRIM

pins. The voltages on the TRIM_CAP

pins are

buffered and applied to the TRIM

pins. The voltage

adjustments on the TRIM

pins cause a slight ripple of

less than 1mV on the power supply voltages. The
amplitude of this ripple is a function of the TRIM_CAP
capacitor and the trim gain of the converter.

Application Note 37 details the calculation of the
TRIM_CAP capacitor to achieve a desired minimum
ripple.
Each channel can be programmed to either enable or
disable the Active DC Control function. When
disabled or not active, the TRIM

pins on the SMM665

are high impedance inputs. If disabled and not used,
they can be connected to ground. The voltages on the
TRIM

pins are buffered and applied to the

TRIM_CAP

pins charging the capacitors. This allows

a smooth transition from the converter powering up to
its nominal voltage; to the SMM665 controlling that
voltage, and to the Active DC Control nominal setting.
The pulse of current can be increased to a 10X pulse
of current until the power supply voltages are at their
nominal settings by selecting the programmable
Speed-Up Convergence option. As the name implies,
this option decreases the time required to bring a
supply voltage from the converter's nominal output
voltage to the Active DC Control nominal voltage
setting.
POWER-ON CASCADE SEQUENCING
The SMM665 can be programmed to sequence up to
six power supplies in any order. Each of these six
channels (A-F) has an associated open drain PUP
output that, when connected to a converter's enable
pin, controls the turn-on of the converter. The
channels are assigned sequence positions to
determine the order of the sequence. Any channel
can also be programmed to not take part in the
sequencing in applications with fewer than six
supplies. The polarity of each of the PUP

outputs is

programmable for use with various types of
converters.
Power-on sequencing can be initiated by the
PWR_ON/OFF pin or via I

C control. The polarity of

the PWR_ON/OFF pin is programmable. If hard wired
in its active state the SMM665 will automatically
initiate the Power-on sequence. Otherwise, toggling
the PWR_ON/OFF pin to its active state will initiate the

Power-on sequence. To enable software control of
the sequencing feature, the SMM665 offers an I

command to initiate Power-on sequencing while the
PWR_ON/OFF pin is in its inactive state.
The SMM665 can be programmed to wait until either
or both VDD and 12VIN inputs are within their
respective voltage threshold limits before Power-on
sequencing is allowed to begin. This ensures that the
converters have their full supply voltage before they
are enabled.
Once Power-on sequencing begins, the SMM665 will
wait a Power-on delay time (t

DPON

) for any channel in

the first sequence position (0) and then activate the
PUP

outputs for those channels. The Power-on

delay times are individually programmable for each
channel. The SMM665 will then wait until all VM

inputs of the channels assigned to the first sequence
position (0) are above their programmed UV1
thresholds which is called cascade sequencing. At
this point, the SMM665 will enter the second sequence
position (1) and begin to timeout the Power-on delay
times for the associated channels. This process
continues until all of channels in the sequence have
turned on and are above their UV1 threshold. The
status registers indicates that all sequenced power
supply channels have turned on. Once these
channels are above their UV1 thresholds, the
SMM665 will begin the Active DC Control of the
enabled channels. The Power-on sequencing mode
ends when the Active DC Controlled channels are at
their nominal voltage setting. The "Ready" bit in the
status registers signifies that the voltages are at their
set points.
The programmable sequence termination timer can be
used to protect against a stalled Power-on sequence.
This timer resets itself at the beginning of each
sequence position. All channels in the sequence
position must go above their UV1 threshold before the
sequence termination timer times out (t

STT

) or the

sequence will terminate and all PUP

outputs will be

switched to their inactive state. The status registers
contain bits that indicate the sequence has been
terminated and in which sequence position the timer
timed out. This timer has four settings of OFF, 100ms,
200ms and 400ms.
While the SMM665 is in the Power-on sequencing
mode the RST output is held active and the HEALTHY
output is held inactive regardless of trigger sources
(Figure 4E). The Power-off and Force Shutdown
trigger options are also disabled while in this mode.

APPLICATIONS INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

Furthermore, the SMM665 will not respond to activity
on the PWR_ON/OFF pin or to a Power-off I

command during Power-on sequencing mode.
ONGOING OPERATIONS-MONITORING MODE
During ongoing operations mode, the part can (1)
monitor (2) actively control via ADOC, and (3) use
force shutdown if necessary.
Once the Power-on sequence is complete and before
a Power-off sequence has been initiated, the SMM665
continues to monitor all VM

inputs, the VDD and

12VIN inputs, and two temperature sensor inputs with
a 10-bit ADC. Each of these inputs is sampled and
converted by the ADC every 2ms. The ADC input has
a range of 0V to four times the voltage on VREF_ADC
for inputs VM

A-F

and the VDD input. The range is

extended to 12 times VREF_ADC for the 12VIN input
and is reduced to two times VREF_ADC for the AIN1
and AIN2 inputs. The range of the internal
temperature sensor is fixed at 128.00°C to 127.75°C.
The SMM665 compares each resulting ADC
conversion with two programmable 10-bit under-
voltage limits (UV1, UV2) and two programmable 10-
bit over-voltage limits (OV1, OV2) for the
corresponding input. A consecutive conversion
counter is used to provide filtering of the ADC inputs.
Each limit can be programmed to require 1, 2, 4 or 6
consecutive out-of-limit conversions before it is said to
be in fault. One in-limit conversion will remove the
fault from the threshold limit. This provides digital
filtering of the monitored inputs. The ADC inputs VM

A-

can use additional filtering by connecting a capacitor

from the corresponding CAP

pins to ground to form

an analog RC filter (R=25k

). The input is considered

to be in a fault condition if any of its limit thresholds
are in fault. Setting an OV threshold limit to full-scale
(3FF

HEX

), or setting an UV threshold limit to 000

HEX

ensures that the limit can never be in fault. The status
registers provide the real-time status of all monitored
inputs.
The voltage threshold limits for inputs VM

A-F

, VDD and

12VIN can be programmed to trigger the RST and
HEALTHY outputs as well as a Force Shutdown and
Power-off operation when exceeded. The threshold
limits for the internal temperature sensor and the AIN1
and AIN2 inputs can be programmed to trigger the
RST, HEALTHY, and FAULT outputs.
The HEALTHY and FAULT outputs of the SMM665
are active as long as the triggering limit remains in a
fault condition. The RST output also remains active as
long as the triggering limit remains in a fault condition;

however, once the trigger source goes away the RST
will remain active for a reset timeout period (t

PRTO

MARGINING
The SMM665 has two additional Active DC Output
Control voltage settings for channels A-F; margin high
and margin low. The margin high and margin low
voltage settings can range from 0.3V to VDD of the
converters' nominal output voltage depending on the
specified margin range of the DC-DC converter.
These settings are stored in the configuration registers
and are loaded into the Active DC Control voltage
setting by margin commands issued via the I

C bus.

The channel must be enabled for Active DC Control in
order to enable margining. The margin command
registers contain two bits for each channel that decode
the commands to margin high, margin low, or control
to the nominal setting. Therefore, any combination of
margin high, margin low, and nominal control is
allowed in the margining mode.
Once the SMM665 receives the command to margin
the supply voltages, it begins adjusting the supply
voltages to move toward the desired setting. When all
channels are at their voltage setting, a bit is set in the
margin status registers.
Note: Configuration writes or reads of registers 00

HEX

to 0F

HEX

should not be performed while the SMM665 is

margining.
POWER-OFF CASCADE SEQUENCING
The SMM665 can be programmed to perform Power-
off sequencing in either the same order or reverse
order of Power-on cascade sequencing.
Power-off cascade sequencing can be initiated by the
PWR_ON/OFF pin, via I

C control or triggered by a

fault condition on any of the monitored inputs.

Toggling the PWR_ON/OFF pin to its inactive state will
initiate the Power-off sequence. To enable software
control of the Power-off sequencing feature, the
SMM665 offers an I

C command to initiate Power-off

sequencing regardless of the state of the
PWR_ON/OFF pin. Furthermore, Power-off
sequencing can be initiated by a fault condition on a
monitored input.
Once Power-off sequencing begins, the SMM665 will
wait a Power-off delay time (t

DPOFF

) for any channel in

the last sequence position (reverse order) and then
deactivate the PUP outputs for those channels. The
Power-off delay times are individually programmable
for each channel. The SMM665 will then wait until all

APPLICATIONS INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

inputs of the channels assigned to that sequence

position are below the programmed OFF thresholds.
At this point, the SMM665 will decrement to the next
sequence position and begin to timeout the Power-off
delay times for the associated channels. This process
continues until all of channels in the sequence have
turned off and are below their OFF thresholds. The
status register reveals that all sequenced channels
have turned off. The Power-off sequencing mode
ends when all sequenced supplies are below their
OFF thresholds.
The programmable sequence termination timer can be
used to protect against a stalled Power-off sequence.
This timer resets itself at the beginning of each
sequence position. All channels in the sequence
position must go below their OFF threshold before the
sequence termination timer times out (t

STT

) or the

sequence will terminate and all PUP outputs will be
switched to their inactive state. This timer has four
settings of OFF, 100ms, 200ms and 400ms. The
sequence termination timer can be disabled separately
for Power-off sequencing.
While the SMM665 is in the Power-off sequencing
mode the RST output is held active and the HEALTHY
output is held inactive regardless of trigger sources
(Figure 4E). The Force Shutdown trigger option is
also disabled while in this mode. Furthermore, the
SMM665 will not respond to activity on the
PWR_ON/OFF pin or to a Power-on I

C command

during Power-off sequencing mode.
FORCE SHUTDOWN
The Force Shutdown operation brings all PUP

outputs to their inactive state. This operation is used
for an emergency shutdown when there is not enough
time to sequence the supplies off. The Force
Shutdown operation shuts off all sequenced channels
and waits for the supply voltages to drop below their
respective OFF thresholds.
A Force Shutdown operation can be initiated by any
one of four events. The first two methods for initiating
a Force Shutdown are always enabled. Simply taking

the FS pin to its active state will initiate a Force
Shutdown operation and maintain it until the pin is
brought to its inactive state. An I

C Force Shutdown

command allows the Force Shutdown operation to be
initiated via software control. This I

C Force Shutdown

command sets a volatile register bit that triggers a
Force Shutdown. This bit is cleared after all
sequenced channels have dropped below their OFF
voltage threshold. During Power-on and Power-off
sequencing, the sequence termination timer can
initiate a Force Shutdown operation.
As described in the previous sections, the sequence
termination timer triggers a Force Shutdown operation
if it times out before the power supply voltages
surpass their voltage thresholds. This Force
Shutdown will remain active until all sequenced power
supply channels have dropped below their OFF
voltage threshold. While the SMM665 is in ongoing
operations-monitor mode, a programmed fault
condition on any power supply channel or on the
12VIN or VDD inputs can trigger a Force Shutdown. A
Force Shutdown resulting from this will remain active
until all sequenced power supply channels have
dropped below their OFF voltage threshold.
RESTART OF POWER-ON CASCADE
SEQUENCING
Once a Force Shutdown or Power-off operation has
completed, the SMM665 can restart the Power-on
cascade sequencing. The device can be programmed
to automatically restart after a Force Shutdown
provided the PWR_ON/OFF pin remains in the active
state or the I

C Power-on command remains in the

command register. If this option is not selected, the
SMM665 requires toggling of the PWR_ON/OFF pin or
toggling of the I

C commands by issuing a Power-off

command and then reissuing the Power-on command
in order to restart Power-on sequencing. In either
scenario, the FS pin will prevent the SMM665 from
restarting Power-on sequencing. In addition, the
device can be programmed to check that VDD and the
12VIN are within their programmed voltage thresholds
before restarting Power-on sequencing.

APPLICATIONS INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

TRIM

SMM665

iP1202

VSW1

SDA

SCL

I2C BUS

I
N

12V

VIN

FB1

VOUT1
1.5V

FB1S

Rtrim

1.6K

VSW2

FB2

VOUT2
2.5V

FB2S

Rtrim

3.3K

Not all components Shown, for interface purposes only
Part designators are from the International Rectifier
iP1202 Demo board .

SS2

PUP

SS1

PUP

R10

Figure 5B The SMM665 can be used to sequence and control discrete DC switching regulators. The ADOC
function sets the output voltage of the IR iP1202 Regulator through the FBX feedback pins. Accuracy is
improved even under full load, essentially acting as a "SENSE" pin. The sequence function is applied
through the iP1202 SSX soft start pins.

Figure 5C Ch1 is set to 2.5V and Ch2 is set to
1.5V on the ip1202 board. Ch1 is set to sequence
on first followed by Ch2 after 50ms. Then Ch1 is
margined high while Ch2 is margined low. Ch2 is
then sequenced off followed by Ch1 after 50ms.

Figure 5D This is the same function sequencing
on but shorter delay, the HEALTHY and RESET
flags are shown.

APPLICATIONS INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

The end user can obtain the Summit SMX3200
programming system for device prototype
development. The SMX3200 system consists of a
programming Dongle, cable and Windows

GUI

software. It can be ordered on the website or from a
local representative. The latest revisions of all
software and an application brief describing the
SMX3200 is available from the website
(

www.summitmicro.com

The SMX3200 programming Dongle/cable interfaces
directly between a PC's parallel port and the target
application. The device is then configured on-screen
via an intuitive graphical user interface employing
drop-down menus.

The Windows GUI software will generate the data and
send it in I

C serial bus format so that it can be directly

downloaded to the SMM665 via the programming
Dongle and cable. An example of the connection
interface is shown in Figure 6.
When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
test operations. This will ensure proper device
operation in the end application.

Pin 9, 5V

Pin 7, 10V

Pin 5, Reserved
Pin 3, GND
Pin 1, GND

Pin 6, MR#
Pin 4, SDA

Pin 2, SCL

Pin 8, Reserved

Pin 10, Reserved

Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.

9
7
5
3
1

8
6
4
2

SMM665

SDA

SCL

VDD_CAP

GND

0.1

Positive

Supply

Com m on

Ground

M R

Figure 6 SMX3200 Programmer I

C serial bus connections to program the SMM665. Note that the MR pin

does not need to be connected to pin 6 for programming purposes.

DEVELOPMENT HARDWARE & SOFTWARE

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I

C). SDA is a bi-directional data line and SCL is a

clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (t

HIGH

)

is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing. The address byte is
comprised of a 4-bit device type identifier (slave
address) and a 3-bit bus address. The remaining bit
indicates either a read or a write operation. Refer to
Table 1 for a description of the address bytes used by
the SMM665.
The device type identifier for the memory array is
generally set to 1010

BIN

following the industry standard

for a typical nonvolatile memory. There is an option to
change the identifier to 1011

BIN

allowing it to be used

on a bus that may be occupied by other memory
devices. The configuration registers are grouped with
the memory array and thus use 1010

BIN

or 1011

BIN

the device type identifier. The command and status
registers as well as the 10-bit ADC are accessible with
the separate device type identifier of 1001

BIN

The bus address bits A[1:0] are programmed into the
configuration registers. Bus address bit A[2] can be
programmed as either 0 or biased by the A2 pin. The
bus address accessed in the address byte of the serial
data stream must match the setting in the SMM665
and on the A2 pin.

Any access to the SMM665 on the I2C bus will
temporarily halt the monitoring function. This is true
not only during the monitor mode, but also during
Power-on and Power-off sequencing when the device
is monitoring the channels to determine if they have
turned on or turned off.
The SMM665 halts the monitor function from when it
acknowledges the address byte until a valid stop is
received.
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 8, 9, 11, 13 and 14. A Start
condition followed by the address byte is provided by
the host; the SMM665 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM665 responds with an acknowledge;
the host then clocks in on byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM665. This is accomplished by a issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 10, 12 and 15 for an
illustration of the read sequence.

C PROGRAMMING INFORMATION

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

WRITE PROTECTION
The SMM665 powers up into a write protected mode.
Writing a code to the volatile write protection register
can disable the write protection. The write protection
register is located at address 87

HEX

of slave address

1001

BIN

Writing 0101

BIN

to bits [7:4] of the write protection

BIN

to bits [3:0] allow writes to the

configuration registers. The write protection can re-
enable by writing other codes (not 0101

BIN

) to the write

protection register. Writing to the write protection
register is shown in Figure 7.
CONFIGURATION REGISTERS
The majority of the configuration registers are grouped
with the general-purpose memory located at either
slave address 1010

BIN

or 1011

BIN

. The bus address

bits, A[1:0], used to differentiate the general-purpose
memory from the configuration registers are set to
11

BIN

. Bus address bit A[2] can be programmed as

either 0 or biased by the A2 pin.
Two additional configuration registers are located at
addresses 83

HEX

and 84

HEX

of slave address 1001

BIN

Writing and reading the configuration registers is
shown in Figures 8, 9, 10,11 and 12.
Note: Configuration writes or reads of registers 00

HEX

to 0F

HEX

should not be performed while the SMM665 is

margining.
GENERAL-PURPOSE MEMORY
The 4k-bit general-purpose memory is located at
either slave address 1010

BIN

or 1011

BIN

. The bus

address bits, A[1:0], used to differentiate the general-
purpose memory from the configuration registers are
set to 00

BIN

for the first 2k-bits and 01

BIN

for the second

2k-bits. Bus address bit A[2] can be programmed as
either 0 or biased by the A2 pin.

The word address must be set each time the memory
is accessed. Memory writes and reads are shown in
Figures 13, 14 and 15.
COMMAND AND STATUS REGISTERS
The command and status registers are located at
slave address 1001

BIN

. Writes and reads of the

command and status registers are shown in Figures
16 and 17.
ADC CONVERSIONS
An ADC conversion on any monitored channel can be
performed and read over the I

C bus using the ADC

read command. The ADC read command, shown in
Figure 18, starts with a dummy write to the 1001

BIN

slave address. Bits [6:3] of the word address byte are
used to address the desired monitored input. Once
the device acknowledges the channel address, it
begins the ADC conversion of the addressed input.
This conversion requires 70

µs to complete. During

this conversion time, acknowledge polling can be
used. The SMM665 will not acknowledge the address
bytes until the conversion is complete. When the
conversion has completed, the SMM665 will
acknowledge the address byte and return the 10-bit
conversion along with a 4-bit channel address echo.
GRAPHICAL USER INTERFACE (GUI)
Device configuration utilizing the Windows based
SMM665 graphical user interface (GUI) is highly
recommended. The software is available from the
Summit website (

www.summitmicro.com

). Using the

GUI in conjunction with this datasheet and Application
Note 33, simplifies the process of device prototyping
and the interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from
Summit to communicate with the SMM665. The
Dongle connects directly to the parallel port of a PC
and programs the device through a cable using the I

bus protocol.

Slave Address Bus Address Register Type

1001

BIN

A2 A1 A0

Write Protection Register,
Command and Status Registers,
Two Configuration Registers,
ADC Conversion Readout

A2 0 0

2-k Bits of General-Purpose Memory

A2 0 1

2-k Bits of General-Purpose Memory

1010

BIN

1011

BIN

A2 1 1

Configuration Registers

Table 1 - Address bytes used by the SMM665.

C PROGRAMMING INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

S
T
A
R
T

A
C
K

M aster

Slave

A
C
K

Configuration

Register Address = 87

HEX

S
T

Data = 55

HEX

A
C
K

Bus Address

HEX

Unlocks

General Purpose

HEX

Unlocks

Configuration

Registers

W rite Protection

Register Address

HEX

Figure 7 Write Protection Register Write

S
T
A
R
T

Bus Address

A
C
K

Master

Slave

A
C
K

S
A

Configuration

Register Address

S
T

Data

A
C
K

Figure 8 Configuration Register Byte Write

S
T
A
R
T

Bus Address

A
C
K

S
T

Master

Slave

A
C
K

Data (16)

S
A

Configuration

Register Address

A
C
K

Data (1)

A
C
K

Data (2)

A
C
K

Figure 9 Configuration Register Page Write

C PROGRAMMING INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

S
T
A
R
T

Bus Address

A
C
K

S
T

N
A
C
K

Master

Slave

A
C
K

Data (n)

S
A

Configuration

Register Address

S
T
A
R
T

A
C
K

Bus Address

S
A

A
C
K

Data (1)

Figure 10 - Configuration Register Read

S
T
A
R
T

A
C
K

Master

Slave

A
C
K

Configuration

Register Address

S
T

Data

A
C
K

Bus Address

Figure 11 - Configuration Register with Slave Address 1001

BIN

Write

S
T
A
R
T

A
C
K

S
T

N
A
C
K

Master

Slave

A
C
K

Data (n)

Configuration

Register Address

S
T
A
R
T

A
C
K

Data (1)

Bus Address

Figure 12 - Configuration Register with Slave Address 1001

BIN

Read

C PROGRAMMING INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

S
T
A
R
T

Bus Address

A
C
K

Master

Slave

A
C
K

S
A

Configuration

Register Address

S
T

Data

A
C
K

Figure 13 General Purpose Memory Byte Write

Bus Address

S
T
A
R
T

A
C
K

S
T

Master

Slave

A
C
K

Data (16)

S
A

Configuration

Register Address

A
C
K

Data (1)

A
C
K

Data (2)

A
C
K

Figure 14 - General Purpose Memory Page Write

S
T
A
R
T

A
C
K

S
T

N
A
C
K

Master

Slave

A
C
K

Data (n)

S
A

Configuration

Register Address

S
T
A
R
T

A
C
K

S
A

A
C
K

Data (1)

Bus Address

Figure 15 - General Purpose Memory Read

C PROGRAMMING INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

S
T
A
R
T

A
C
K

Master

Slave

A
C
K

Command and Status

Register Address

S
T

Data

A
C
K

Bus Address

Figure 16 Command and Status Register Write

S
T
A
R
T

A
C
K

S
T

N
A
C
K

Master

Slave

A
C
K

Data (n)

Command and Status

Register Address

S
T
A
R
T

A
C
K

Data (1)

Bus Address

Figure 17 - Command and Status Register Read

S
T
A
R
T

Bus Address

C
H

A
C
K

S
T
A
R
T

Bus Address

S
T
A
R
T

Bus Address

C
H

S
T

N
A
C
K

Master

Slave

Channel Address Echo

Channel Address

A
C
K

10-Bit ADC Data

A
C
K

Figure 18 ADC Conversion Read

C PROGRAMMING INFORMATION (CONTINUED)

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

DEFAULT CONFIGURATION REGISTER SETTINGS SMM665-144

Register Contents Register Contents Register Contents Register Contents

R0 0D R42

0E R9C

29 RC5

R1 83 R43

39 R9D

9A RC6

R2 0D R44

0E R9E

11 RC7

R3 FF R45

A4 R9F

AE RC8

R4 0E R46

0F RA0

41 RC9

R5 61 R47

16 RA1

0B RCA

R6 0E R48

0F RA2

80 RCB

R7 C7 R49

B4 RA3

F6 RCC

R8 0F R4A

06 RA4

29 RCD

R9 54 R4B

7F RA5

5D RCE

RA 0B R4C

00 RA6 11 RCF

RB 22 R4D

12 RA7

71 RD0

RC 7F R4E

48 RA8 40 RD1

RD 3F R80 42 RA9 A4 RD2

RE 07 R81

48 RAA

80 RD3

RF 01 R82

82 RAB

8F RD4

R10 8F R83 3E RAC 29 RD5 D8
R11

9F R84

2A RAD

1F RD6

R12 AF R85 B8 RAE 11 RD7 D8
R13 BF R86 12 RAF 33 RE0 00
R14 CF R87 F6 RB0 2A RE1 3D
R15 DF R88 41 RB1 67 RE2 00
R18 00 R89 C8 RB2 0A RE3 3D
R19

00 R8A

81 RB3

52 RE4

R30 0D R8B B9 RB4 03

RE5 3D

R31 60 R8C 2A RB5 FF RE6 00
R32 0D R8D 34 RB6 03 RE7 3D
R33 DC R8E 12

RB7 FF RE8 00

R34 0E R8F 49 RB8 0D RE9 3D
R35 45 R90 49 RB9 9A REA 00
R36 0E R91 5C RBA 0D REB 3D
R37 A2 R92 81 RBB 56

R38

0F R93

52 RBC

R39 08 R94 29 RBD E0

R3A

0F R95

D7 RBE

R3B D6 R96 11 RBF E0

R3C 00

R97 EB RC0 0B

R3D

12 R98

41 RC1

R3E 48 R99 3E RC2 0B

R40 0D R9A 81 RC3 38

R41 B9 R9B 33 RC4 09

RC1

The default device ordering number is SMM665F-144, is programmed as described above
and tested over the commercial temperature range. Application Note 33 contains a
complete description of the Windows GUI and the default settings of each of the 154
individual Configuration Registers.

SMM665

Preliminary Information

Summit Microelectronics, Inc

2067 1.9 5/16/03

PART MARKING

SUMMIT

SMM665F

AYYWW

Pin 1

Annn

Summit Part Number

Date Code (YYW W )

Part Num ber suffix
(Contains Custom er specific ordering requirem ents)

Lot tracking code (Sum m it use)

Drawing not to scale

Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Sum m it Use)

Product Tracking Code (Sum m it use)

ORDERING INFORMATION

NOTICE

NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.

Revision 1.9 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at

www.summitmicro.com

for data sheet updates.

Power Management for CommunicationsTM

I2C is a trademark of Philips Corporation.

SMM665

nnn

Package

F=48 Lead TQFP

Part Number Suffix (see page 23)

Summit Part Number

Specific requirem ents are contained in the suffix
such as Com m ercial or Industrial Tem p Range,
Hex code, Hex code revision, etc.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SMM665